Hi All,
I see a big problem with the dac_fmc_ebz project hdl SPI interface setup when used with a AD917x FMC card.
I do not think anyone at Analog Devices actually test this design, unless I am really missing something.
The AD9172X series of FMC cards uses a HMC7044 as its clock source. The HMC7044 serial IO port is a three -wire interface with a single bidirectional data pin SDATA. SDATA is connected to the buffered MOSI signal into the FMC connector by U7 back to FPGA.
Now if you look at the dac_fmc_ebz system_top.v hdl for any of the Xilinx FPGA boards it supports, such as ZCU102, you can see the spi_mosi pin is setup as a output only.
There is no way to read data back from the HMC7044 over the SPI port since the spi_mosi pin is a output only. Of course the first thing the Linux iio/frequency/HMC7044 driver does is a test to write and read back of the HMC7044 scratchpad register, which fails because you cannot read back from it.
Now several of the hdl designs such a daq2 make use of a spi to three-wire hdl code module in their system_top.v. There is also ad_3w_spi.v in the library/common. Anyway something of this nature needs to be in the system_top.v for the dac_fmc_ebz project to be able to read back from the HMC7044 clock chip on the AD917X FMC card.
Also note the AD9172.c Linux iio driver and FMC card are setup with separate serial in and output data ports hence you need to have some spi to three-wire hdl code that is only enabled for the HMC7044 spi chip select.
I have to ask is if anyone did QA on this.
Hope to hear back,
James
