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dac_fmc_ebz hdl spi interface to HMC7044 on FMC ad917x not setup allow reading back

Category: Software
Product Number: AD917x FMC
Software Version: dac_fmc_ebz hdl and HMC7044 Linux/iio driver, current in AD github

Hi All,

 I see a big problem with the dac_fmc_ebz project hdl SPI interface setup when used with a AD917x FMC card.

 I do not think anyone at Analog Devices actually test this design, unless I am really missing something.

 The AD9172X series of FMC cards uses a HMC7044 as its clock source. The HMC7044 serial IO port is a three -wire interface with a single bidirectional data pin SDATA. SDATA is connected to the buffered MOSI signal into the FMC connector by U7 back to FPGA.

  Now if you look at the dac_fmc_ebz system_top.v  hdl for any of the Xilinx FPGA boards it supports, such as ZCU102, you can see the spi_mosi pin is setup as a output only. 

  There is no way to read data back from the HMC7044 over the SPI port since the spi_mosi pin is a output only. Of course the first thing the Linux iio/frequency/HMC7044 driver does is a test to write and read back of the HMC7044 scratchpad register, which fails because you cannot read back from it.

   Now several of the hdl designs such a daq2 make use of a spi to three-wire hdl code module in their system_top.v. There is also ad_3w_spi.v in the library/common. Anyway something of this nature needs to be in the system_top.v for the dac_fmc_ebz project to be able to read back from the HMC7044 clock chip on the AD917X FMC card.

   Also note the AD9172.c Linux iio driver and FMC card are setup with separate serial in and output data ports hence you need to have some spi to three-wire hdl code that is only enabled for the HMC7044 spi chip select.

   I have to ask is if anyone did QA on this.   

Hope to hear back,

James

Parents
  • Hi James,

    the project was tested for the 2019_r2 release.  The HMC7044 SPI operates in write only mode. The driver supports that unless something changed lately  in that regard.

    The eval board has a level shifter U7 with hardcoded direction pin T_R1_N , so the MOSI is always output so no reason to place a tree wire logic in the top level v.

    Laszlo

  • That's only a warning that is printed.

    https://github.com/analogdevicesinc/linux/commit/76d3d1240d4e1b97d66e315c1be174883879bb5b

    This won't error out, but will prevent bogus reads.

    -Michael

  • Michael,

      Thanks for your response. I see now that U7 is a 245-type part I thought it was a bidirectional level shifter. I am doing a custom design and had the AD9172 driver generate a clocking error, since I saw the HMC7044 driver report a read failure I assumed it was the problem.

      It might be nicer not to use the word failed. Perhaps read back not supported. If it had said Probe completed and HMC7044 setup was successful, read back not supported it would have been clearer that the issue was not the HMC7044.    

     I was trying to setup the AD9176 device I have to run a 2.4576GHz from 307.2MHz clock input from the HMC7044. I when back and set the dts/dtb  file to use 2.94912GHz, 368.64MHz from HMC7044,  as in the default dts/dtb for AD9172. The PLL in the Ad9176 locks now and driver for it completes. Looking at AD9176 data sheet I see the min VCO is 2.92GHz.

       Just to note, I have a custom design on Iwave g35d using DDR4 for waveform storage. I have it working with AD9136 FMC board running at 2.4GHz. Not sure I it the DDR4 can keep up with a faster data pull rate.

      I am looking at the AD9176 data sheet also not sure it can be operated at lower than 2.92GHz in 1x interpolation mode using VCO.

     

    Anyway

    Always thank you for quick response,

     James

Reply
  • Michael,

      Thanks for your response. I see now that U7 is a 245-type part I thought it was a bidirectional level shifter. I am doing a custom design and had the AD9172 driver generate a clocking error, since I saw the HMC7044 driver report a read failure I assumed it was the problem.

      It might be nicer not to use the word failed. Perhaps read back not supported. If it had said Probe completed and HMC7044 setup was successful, read back not supported it would have been clearer that the issue was not the HMC7044.    

     I was trying to setup the AD9176 device I have to run a 2.4576GHz from 307.2MHz clock input from the HMC7044. I when back and set the dts/dtb  file to use 2.94912GHz, 368.64MHz from HMC7044,  as in the default dts/dtb for AD9172. The PLL in the Ad9176 locks now and driver for it completes. Looking at AD9176 data sheet I see the min VCO is 2.92GHz.

       Just to note, I have a custom design on Iwave g35d using DDR4 for waveform storage. I have it working with AD9136 FMC board running at 2.4GHz. Not sure I it the DDR4 can keep up with a faster data pull rate.

      I am looking at the AD9176 data sheet also not sure it can be operated at lower than 2.92GHz in 1x interpolation mode using VCO.

     

    Anyway

    Always thank you for quick response,

     James

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