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AD9172 never leaves CGS

Category: Hardware
Product Number: AD9172

We're trying to bring up an AD9172 on a custom PCB.

We get through PLL and DLL lock. Using ADI IP on the FPGA and ADI linux drivers, the jesd_status tool reports the clocks OK, but the DAC never leaves the CGS state.

On the FPGA, we have looked at the data sent to the ADI XCVR and it is the /k/ characters as expected, but the SYNOUTB line never deasserts.

We've tried checking the Data lines using a PRBS pattern and the registers always respond with max errors.

Running the Internal Loop Back Test also results in max errors.



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[edited by: alanw00 at 10:54 PM (GMT -4) on 27 May 2022]

Top Replies

    •  Analog Employees 
    Jun 10, 2022 in reply to alanw00 +1 suggested

    Hi  

    on the evaluation board  the first four lanes have the polarity inverted on the PCB. To revert that in the physical layer (util_adxcvr) we set a lane inversion parameter (TX_LANE_INVERT) see…

  • Hello,

    "We've tried checking the Data lines using a PRBS pattern" - I assume you are performing a "PHY PRBS" test as described on page 46 of the rev C data sheet?  If not, try that test.  If PHY PRBS test fails and the device clock is the appropriate frequency, there is a signal integrity issue on at least one of the instantiated lanes.  If PHY PRBS test passes for each lane, then yoiu likely have  clock or configuration mismatch.  See the JESD204B debug guide for more assistance. I am also copying FormerMember , one of our FPGA engineers who has worked on the ADI IP just in case he has any further comments.

    Del

  • Could you please share the output of the jesd_status command ?

    And the clock summary:

    cat /sys/kernel/debug/clk/clk_summary

    Topically this happens when either the SYNC~ is not connected correctly or there is lane rate mismatch between the endpoints of the link.

    Thank you,

    Laszlo

  • Here is the relevant(hopefully) section of the clk_summary

                                     enable  prepare  protect                                duty
       clock                          count    count    count        rate   accuracy phase  cycle
    ---------------------------------------------------------------------------------------------
     clkin2_0                             0        0        0           0          0     0  50000
     clkin1_0                             0        0        0           0          0     0  50000
     xtal_0                               0        0        0           0          0     0  50000
        pll_0                             0        0        0           0          0     0  50000
           clk1_0                         0        0        0           0          0     0  50000
           clk0_0                         0        0        0           0          0     0  50000
     si570_mgt                            0        0        0   148499999          0     0  50000
     si570_user                           0        0        0   299999997          0     0  50000
     ltc6953_dac_gtx_ref                  0        0        0   750000000          0     0  50000
     ltc6953_extra_clk                    0        0        0   300000000          0     0  50000
     ltc6953_adc_gtx_ref                  0        0        0   375000000          0     0  50000
     ltc6953_fpga_sysref                  0        0        0     5859375          0     0  50000
     ltc6953_fpga_clk                     0        0        0   300000000          0     0  50000
     ltc6953_adc1_sysref                  0        0        0     5859375          0     0  50000
     ltc6953_adc1_clk                     0        0        0   375000000          0     0  50000
     ltc6953_adc0_sysref                  1        1        0    11718750          0     0  50000
     ltc6953_adc0_clk                     3        3        1   375000000          0     0  50000
        adc_gt_clk                        1        1        1     3750000          0     0  50000
           jesd_adc_lane_clk              1        1        0     3750000          0     0  50000
           rx_out_clk                     0        0        0    93750000          0     0  50000
     ltc6953_dac_sysref                   1        1        0     5859375          0     0  50000
     ltc6953_dac_clk                      3        3        1   750000000          0     0  50000
        tx_out_clk                        0        0        0   375000000          0     0  50000
        dac_gt_clk                        1        1        1    15000000          0     0  50000
           jesd_dac_lane_clk              1        1        0    15000000          0     0  50000

    Here is the result from the jesd_status tool

    ┌─────────────────────────────────────────────────────────────────────────────────┐
    │┌(DEVICES) Found 2 JESD204 Link Layer peripherals───────────────────────────────┐│
    ││                                                                               ││
    ││(0): axi-jesd204-rx/84aa0000.axi-jesd204-rx                                    ││
    ││(1): axi-jesd204-tx/84a90000.axi-jesd204-tx  [*]                               ││
    │└───────────────────────────────────────────────────────────────────────────────┘│
    │┌(STATUS)───────────────────────────────────────────────────────────────────────┐│
    ││Link is                      enabled                                           ││
    ││Link Status                  CGS                                               ││
    ││Measured Link Clock (MHz)    375.037                                           ││
    ││Reported Link Clock (MHz)    375.000                                           ││
    ││Measured Device Clock (MHz)  N/A                                               ││
    ││Reported Device Clock (MHz)  N/A                                               ││
    ││Desired Device Clock (MHz)   N/A                                               ││
    ││Lane rate (MHz)              15000.000                                         ││
    ││Lane rate / 40 (MHz)         375.000                                           ││
    ││LMFC rate (MHz)              46.875                                            ││
    ││SYSREF captured              Yes                                               ││
    ││SYSREF alignment error       No                                                ││
    ││SYNC~                        asserted                                          ││
    │└───────────────────────────────────────────────────────────────────────────────┘│
    │                                                                                 │
    │                                                                                 │
    │                                                                                 │
    │                                                                                 │
    │                                                                                 │
    │                                                                                 │
    │                                                                                 │
    │                                                                                 │

  • Yes, we have tried the test outlined on page 46. the PHY PRBS test fails. I believe the device clock is correct. The calculated lane rate from register reads on the DAC matches the lane rate reported via jesd_status. Does that suggest that there is an issue with the pcb traces?

  • Hi  

    on the evaluation board  the first four lanes have the polarity inverted on the PCB. To revert that in the physical layer (util_adxcvr) we set a lane inversion parameter (TX_LANE_INVERT) see here.

    Please make sure that on your design that is set accordingly.

    However that does not explains completely what you are observing, since even with inverted polarity you should pass the CGS stage,  but certainly affects the PRBS PHY testing.

    How are you testing the PRBS at the PHY level ? Are you using the procedure from axi_adxcvr through the Linux driver?

    Thank you,

    Laszlo

  • Thank you for your response.

    I believe the invert setting is set appropriately for our design.

    Yes, the PRBS test at the phy level is configured by directly writing the registers described on the axi_adxcvr wiki article section you referenced.