AD9176 Mode 2

Question

Hello, 
 I am trying to use the AD9176 + ZCU102 reference project but I want to use all 3 channels per DAC, so I changed the mode in config.tcl from the default of 04 to 02. Mode 4 works fine but mode 2 errors out when building the block design. I have tried both the 2019_r2 release as well as the latest on master. 
 ERROR: [IP_Flow 19-3461] Value '96' is out of the range for parameter 'Bus Width(DMA_DATA_WIDTH_DEST)' for BD Cell 'dac_dma' . Valid values are - 16, 32, 64, 128, 256, 512, 1024
INFO: [IP_Flow 19-3438] Customization errors found on 'dac_dma'. Restoring to previous valid configuration.
INFO: [Common 17-17] undo 'set_property'
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

 while executing
"rdi::add_properties -dict {CONFIG.DMA_TYPE_SRC 0 CONFIG.DMA_TYPE_DEST 1 CONFIG.DMA_DATA_WIDTH_SRC 64 CONFIG.DMA_DATA_WIDTH_DEST 96} /dac_dma"
 invoked from within
"set_property -dict $config $cell"
 invoked from within
"if {$i_params != {}} {
 set config {}
 # Add CONFIG. prefix to all config options
 foreach {k v} $i_params {
 lappend config "CONFIG.$k"..."
 (procedure "ad_ip_instance" line 4)
 invoked from within
"ad_ip_instance axi_dmac dac_dma [list \
 DMA_TYPE_SRC 0 \
 DMA_TYPE_DEST 1 \
 DMA_DATA_WIDTH_SRC 64 \
 DMA_DATA_WIDTH_DEST $dac_dma_data_width \
]"
 (file "../common/dac_fmc_ebz_bd.tcl" line 79) 
 Do you have any advice on getting this to work in mode 2? 
 Steps to reproduce: 
 
 clean copy of hdl repo 
 modify projects/dac_fmc_ebz/common/config.tcl to set mode 04 rather than mode 02 
 build zcu102 project 
 
 Thanks, Jason

AndreiDragomir · Accepted Answer

Hello,

You can run single-link Mode 2 by doing the following manual modifications:

- In config.tcl set mode to 02
- In dac_fmc_ebz_bd.tcl set DAC_DATA_WIDTH to the next available value (128 in this case)
- In the devicetree for mode4:
- set adi,jesd-link-mode = <2>
- remove adi,out-clk-select = <XCVR_REFCLK_DIV2>

This should be enough for the single link Mode 2 to work.
For dual-link it seems that the lack of support for 12 converters inside the tpl core could be a problem. I tried to find a way around it and I also used your idea, but couldn't get it to work.
For now, I'd say that the dual-link mode 2 is not supported, but any other mode should work fine.

> Do I need to change any of the clock rates for Mode 2?
No, just the changes mentioned above are enough.

> How does the JESD link "know" to double the lane rate? Is that just by the device tree setting?
It is calculated based on the JESD parameters which change according to the selected link mode.

> How is the internal FPGA clock configured to be half the input reference clock rate?
Not sure what you mean. The FPGA clock is 368.64 MHz by default. The device clock should be Lane_rate/40 and is derived from FPGA clock. To configure the device clock as half of FPGA clock, you use this setting in the devicetree - adi,out-clk-select = <XCVR_REFCLK_DIV2>

> Are the changes I proposed (double TPL core bytes per beat, JESD transmit input/output data widths) correct?
Might need to look into it a bit more, but from initial testing, they don't seem to work.

> Any other guidance on how to make Mode 2 work?
It should work with the changes described above if you want to keep the settings from mode 4, but if you want to play around with the settings, I suggest consulting the datasheet first.

Best regards,
Andrei

Electronic Design Services - PartnerZone

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AD9176 Mode 2

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