I am attempting to evaluate the ad9680 on the Xilinx zcu106 platform, using the ad9680 fmc evaluation board.
My sample rate clock is 1GHz.
M (Number of converters) = 2
N’ (ADC number of bits per sample) = 16
S (Samples per frame) = 1
L (Number of lanes) = 4
So my Lane line rate is 10GHz
And my reference clock is then 500MHz.
There is no example design for the ad90680, but there is one for the daq2, which uses the 9680.
So, I basically copied the pertinent block design logic into my design.
Now my question.
How do I configure the util_adxcvr parameters?
I cannot find the documentation for this.
I set the parameters to be the same as those in the daq2 design, except the rx lane rate which I set to 10G.
Attached are screen shots of the util_adxcvr values.
Any guidance regarding how to set these parameters would be greatly appreciated.