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What is standard assignment of JESD204B octets to lanes?

Category: Software
Product Number: AD9695

My hardware setup is an FMC with 2 AD9695 on an MicroTCA Xilinx kintex Ultrascale FPGA Carrier from an external vendor.

The ADCs share SPI and are simultaneously programmed with the same settings from FPGA (p. 79 in datasheet). I enabled ramp test mode on  JESD204 framer input by setting register 0x0573 to 0x08. I also disabled scrambler for the test

On FPGA Xilinx JESD204 PHY is used for physical layer and  for link layer. I don't use AXI. the link peripheral is configured by hardwiring the configuration inputs to constant values.

I instantiated the System ILA IP and monitor the physical interface of Xilinx IP as well as all outputs of each link peripheral.  

This is a follow up question to Same configuration but different output from AD9695 . The original problem is more or less solved but I still not sure whether the lanes are in necessary order.

What is standard order of lanes? that is, which octets are supposed to show up on lane 0, 1, 2, 3 respectively? What order does Analog Devices JESD204B/C Link Receive Peripheral expect?

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