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"ILA clock has stopped" error when trying to arm debug hab clocked by AD9361 l_clk

Category: Software
Software Version: Vivado 2018.2

Dear Colleagues,
I'm trying to observe signals on my IP core (call it SimpleQPSK), which generates IQ samples for axi_ad9361 block. My SimpleQPSK IP core is clocked directly by l_clk from axi_ad9361, as shown below.

The problem I'm facing is that usually I can't arm the debug hub in Vivado Hardware Manager, getting the message:

"[Labtools 27-3428] Ila core [hw_ila_0] clock has stopped. Unable to arm ILA core."

From that I infer that l_clk might be unstable when the sampling frequency is at a time of transition. Am I right? Could I ask for any advice how to overcome that issue?

Is it wrong to use l_clk to clock my IP? I don't think so since in the reference design there is only a simple clock divider in the middle.

Best regards,
Matt

  • Hello Matt,

    Does your design meet timing ? That may be creating the issue.

    Regards,

    Adrian

  • Thank you for your hint, Adrian, but the timing is clean, definitely:

    I'd like to add that the ad9361 l_clk runs with 61.44 MHz frequency on the target setup, but running it slower does not make the situation better. I guess it would help in the case of timing closure issues.

    Would you also advise me what is the role of clkout line of AD9364? Does it play any role in the reference design? Should it be running?

    Matt

  • Hello Matt,

    What FPGA are you using ? What evaluation board ?

    We don't use clk_out in the fmcomms2/3/5 reference designs.

    Regards,

    Adrian

  • Dear Adrian,

    in the current project we use an own-designed  PCB including AD9364 and Zynq xc7z030sbg485-1. However, we adopted the ADRV9361-Z7035 reference design from our previous project, wherein we used the standard SoC.

    Your suggestion about timing closure led us to a hypothesis that the problem might be caused by poor quality of l_clk clock itself. Our external 40 MHz oscillator, connected to XTAL_N, has just appeared to produce a signal with the peak-to-peak voltage far below 1.3V, suggested in UG-673 document. So, we claim that the whole BBPLL section might work unstable and, as a result, l_clk can be poor.

    Regards,
    Matt