I'm trying to observe signals on my IP core (call it SimpleQPSK), which generates IQ samples for axi_ad9361 block. My SimpleQPSK IP core is clocked directly by l_clk from axi_ad9361, as shown below.
The problem I'm facing is that usually I can't arm the debug hub in Vivado Hardware Manager, getting the message:
"[Labtools 27-3428] Ila core [hw_ila_0] clock has stopped. Unable to arm ILA core."
From that I infer that l_clk might be unstable when the sampling frequency is at a time of transition. Am I right? Could I ask for any advice how to overcome that issue?
Is it wrong to use l_clk to clock my IP? I don't think so since in the reference design there is only a simple clock divider in the middle.