AD9081 FMCA EBZ + ZC706 clocking

andrearu on May 4, 2022

Category: Software

Product Number: AD9081-FMCA-EBZ

Hi,

I have a AD9081-FMCA-EBZ mounted on a ZC706 board. I'm trying to set the data rate for TX and RX as slow as possible. The purpose is enable the transmission of data via Ethernet (limited bandwidth), without developing an extra interpolator and decimator on the PL. The goal would be to use the maximum decimation for the ADC (96x) while using all 8 converters, and something similar for the DAC path too.

I'm using the Petalinux flow to build the SW, using the meta-adi repository. I started from the reference design (hdl repo maaster branch, folder hdl/projects/ad9081_fmca_ebz/zc706 + petalinux + meta-adi maaster branch with KERNEL_DTB="zynq-zc706-adv7511-ad9081").

I compiled reference design without modifications and it worked ok (DAC: 12 GSa/s, ADC: 4 GSa/s, DAC interpolation: 48, ADC decimation:16, data rate after decimation: 250 MSa/s for both ADC and DAC).

I tried to halve the sample speed first (DAC: 6 GSa/s, ADC: 2 GSa/s) without changing the HDL and everything seems to work OK (using QPLL for both). The data rate (after decimation/interpolation) goes from 250 MSa/s to 125 MSa/s for both TX and RX. The JESD lanes are working at 5 GHz.

The reference design uses the QPLL for both adxcvr instances (tx and rx). In order to decrease the ADC data rate further for the RX channel, I tried to switch to CPLL for RX. I modified the hdl and connected the hmc7044 channel 8 (unused in the reference design) to the CPLL input. I recompiled the JESD link with 2 lanes instead of 4 and in the device tree I used JESD mode 4.00 for the ADC path that supports 2 lanes, 8 converters, 16 bit per sample with the 4x8 decimation. This configuration also seems to work fine, however jesd_status complains about "measured link clock" (shown in red in the status, it's not equal to the "reported link clock"). Am I missing something here? By the way, the systems seems to work fine (FFT looks ok with the IIO oscilloscope).

The diff for the HDL project is the following

diff --git a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
index 48fbbcb21..f3c224669 100644
--- a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
+++ b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
@@ -269,7 +269,8 @@ create_bd_port -dir I ref_clk_q1
 if {$ADI_PHY_SEL == 1} {
   for {set i 0} {$i < [expr max($TX_NUM_OF_LANES,$RX_NUM_OF_LANES)]} {incr i} {
     set quad_index [expr int($i / 4)]
-    ad_xcvrpll  ref_clk_q$quad_index  util_mxfe_xcvr/cpll_ref_clk_$i
+    #ad_xcvrpll  ref_clk_q$quad_index  util_mxfe_xcvr/cpll_ref_clk_$i
+    ad_xcvrpll  ref_clk_q1  util_mxfe_xcvr/cpll_ref_clk_$i
     if {[expr $i % 4] == 0} {
       ad_xcvrpll  ref_clk_q$quad_index  util_mxfe_xcvr/qpll_ref_clk_$i
     }
diff --git a/projects/ad9081_fmca_ebz/zc706/system_constr.xdc b/projects/ad9081_fmca_ebz/zc706/system_constr.xdc
index a3edb067d..f8dba9cd0 100644
--- a/projects/ad9081_fmca_ebz/zc706/system_constr.xdc
+++ b/projects/ad9081_fmca_ebz/zc706/system_constr.xdc
@@ -16,6 +16,8 @@ set_property         -dict {PACKAGE_PIN U27   IOSTANDARD LVDS_25  DIFF_TERM TRUE
 set_property         -dict {PACKAGE_PIN U26   IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports clkin6_p         ]    ; ## FMC0_CLK1_M2C_P     IO_L12P_T1_MRCC_13
 set_property         -dict {PACKAGE_PIN AD9                                     } [get_ports fpga_refclk_in_n ]    ; ## FMC0_GBTCLK0_M2C_N  MGTREFCLK0N_109
 set_property         -dict {PACKAGE_PIN AD10                                    } [get_ports fpga_refclk_in_p ]    ; ## FMC0_GBTCLK0_M2C_P  MGTREFCLK0P_109
+set_property         -dict {PACKAGE_PIN AA7                                     } [get_ports fpga_refclk2_in_n ]    ;
+set_property         -dict {PACKAGE_PIN AA8                                     } [get_ports fpga_refclk2_in_p ]    ;
 set_property  -quiet -dict {PACKAGE_PIN AG7                                     } [get_ports rx_data_n[2]     ]    ; ## FMC0_DP2_M2C_N      MGTXRXN2_109     FPGA_SERDIN_0_N
 set_property  -quiet -dict {PACKAGE_PIN AG8                                     } [get_ports rx_data_p[2]     ]    ; ## FMC0_DP2_M2C_P      MGTXRXP2_109     FPGA_SERDIN_0_P
 set_property  -quiet -dict {PACKAGE_PIN AH9                                     } [get_ports rx_data_n[0]     ]    ; ## FMC0_DP0_M2C_N      MGTXRXN0_109     FPGA_SERDIN_1_N
diff --git a/projects/ad9081_fmca_ebz/zc706/system_project.tcl b/projects/ad9081_fmca_ebz/zc706/system_project.tcl
index cbdbf89fa..37b9db85f 100644
--- a/projects/ad9081_fmca_ebz/zc706/system_project.tcl
+++ b/projects/ad9081_fmca_ebz/zc706/system_project.tcl
@@ -31,10 +31,10 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
 adi_project ad9081_fmca_ebz_zc706 0 [list \
   JESD_MODE    8B10B \
-  RX_LANE_RATE [get_env_param RX_RATE      10 ] \
-  TX_LANE_RATE [get_env_param TX_RATE      10 ] \
+  RX_LANE_RATE [get_env_param RX_RATE      5 ] \
+  TX_LANE_RATE [get_env_param TX_RATE      5 ] \
   RX_JESD_M    [get_env_param RX_JESD_M    8 ] \
-  RX_JESD_L    [get_env_param RX_JESD_L    4 ] \
+  RX_JESD_L    [get_env_param RX_JESD_L    2 ] \
   RX_JESD_S    [get_env_param RX_JESD_S    1 ] \
   RX_JESD_NP   [get_env_param RX_JESD_NP   16] \
   RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \

system-user.dtsi

/include/ "system-conf.dtsi"
/ {
};

&hmc7044 {
    channel@12 { adi,divider = <24>; //TX REF CLK 
        };
    channel@8 { adi,divider = <48>; //RX REF CLK 
        };
};

&axi_ad9081_adxcvr_rx {
    clocks = <&hmc7044 8>; //change source clock to channel 8 of hmc7044
    adi,sys-clk-select = <XCVR_CPLL>;
};

&ad9081_adc0 { adi,decimation = <4>; };
&ad9081_adc1 { adi,decimation = <4>; };
&ad9081_adc2 { adi,decimation = <4>; };
&ad9081_adc3 { adi,decimation = <4>; };

&ad9081_rx_fddc_chan0 { adi,decimation = <8>; };
&ad9081_rx_fddc_chan1 { adi,decimation = <8>; };
&ad9081_rx_fddc_chan4 { adi,decimation = <8>; };
&ad9081_rx_fddc_chan5 { adi,decimation = <8>; };

&trx0_ad9081 {
    adi,tx-dacs {
        adi,dac-frequency-hz = /bits/ 64 <6000000000>;
        };
    adi,rx-adcs {
        adi,adc-frequency-hz = /bits/ 64 <2000000000>;
        adi,jesd-links { link@0 {
                    //test with two lanes L=2 M=8, mode 4
                    //see https://www.analog.com/media/en/technical-documentation/user-guides/ad9081-ad9082-ug-1578.pdf page 130
                    adi,link-mode = <4>;                         // JESD Quick Configuration Mode
                    adi,subclass = <1>;                          // JESD SUBCLASS 0,1,2
                    adi,version = <1>;                           // JESD VERSION 0=204A,1=204B,2=204C
                    adi,dual-link = <0>;                         // JESD Dual Link Mode
                    adi,converters-per-device = <8>;             // JESD M
                    adi,octets-per-frame = <8>;                  // JESD F
                    adi,frames-per-multiframe = <32>;            // JESD K
                    adi,converter-resolution = <16>;             // JESD N
                    adi,bits-per-sample = <16>;                  // JESD NP'
                    adi,control-bits-per-sample = <0>;           // JESD CS
                    adi,lanes-per-device = <2>;                  // JESD L
                    adi,samples-per-converter-per-frame = <1>;   // JESD S
                    adi,high-density = <0>;                      // JESD HD
            }; };
        };
};

Relevant part of the dmesg output:

hmc7044 spi1.0: PLL1: Locked, CLKIN0 @ 100000000 Hz, PFD: 10000 kHz - PLL2: Locked @ 3000.000000 MHz
jesd204: /axi/spi@e0007000/hmc7044@0,jesd204:1,parent=spi1.0: Using as SYSREF provider
axi_adxcvr 44a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.05.a) using CPLL on GTX2 at 0x44A60000. Number of lanes: 2.
axi_adxcvr 44b60000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.05.a) using QPLL on GTX2 at 0x44B60000. Number of lanes: 4.
axi-jesd204-rx 44a90000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0x44A90000. Encoder 8b10b, width 4/8, lanes 2, jesd204-fsm.
axi-jesd204-tx 44b90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a) at 0x44B90000. Encoder 8b10b, width 4/4, lanes 4, jesd204-fsm.
axi_sysid 45000000.axi-sysid-0: AXI System ID core version (1.01.a) found
axi_sysid 45000000.axi-sysid-0: [ad9081_fmca_ebz] on [zc706] git branch <master> git <a0098acc5a49d49677ddb86a5bd0bd4abacf4b08> clean [2022-05-03 08:50:06] UTC
fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
usbcore: registered new interface driver snd-usb-audio
NET: Registered protocol family 10
Segment Routing with IPv6
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 36
Key type dns_resolver registered
Registering SWP/SWPB emulation handler
of-fpga-region fpga-full: FPGA Region probed
[drm] Initialized axi_hdmi_drm 1.0.0 20120930 for 70e00000.axi_hdmi on minor 0
Console: switching to colour frame buffer device 240x67
axi-hdmi 70e00000.axi_hdmi: [drm] fb0: axi_hdmi_drmdrm frame buffer device
ad9081 spi0.0: supply vdd not found, using dummy regulator
usb 1-1: new high-speed USB device number 2 using ci_hdrc
usb 1-1: New USB device found, idVendor=2109, idProduct=2813, bcdDevice=90.11
usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 1-1: Product: USB2.0 Hub
usb 1-1: Manufacturer: VIA Labs, Inc.
hub 1-1:1.0: USB hub found
hub 1-1:1.0: 4 ports detected
usb 1-1.1: new low-speed USB device number 3 using ci_hdrc
usb 1-1.1: New USB device found, idVendor=046d, idProduct=c00e, bcdDevice=11.10
usb 1-1.1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 1-1.1: Product: USB-PS/2 Optical Mouse
usb 1-1.1: Manufacturer: Logitech
input: Logitech USB-PS/2 Optical Mouse as /devices/soc0/axi/e0002000.usb/ci_hdrc.0/usb1/1-1/1-1.1/1-1.1:1.0/0003:046D:C00E.0001/input/input0
hid-generic 0003:046D:C00E.0001: input,hidraw0: USB HID v1.10 Mouse [Logitech USB-PS/2 Optical Mouse] on usb-ci_hdrc.0-1.1/input0
usb 1-1.2: new low-speed USB device number 4 using ci_hdrc
usb 1-1.2: New USB device found, idVendor=09da, idProduct=0260, bcdDevice= 2.50
usb 1-1.2: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 1-1.2: Product: USB Keyboard
usb 1-1.2: Manufacturer:
input:   USB Keyboard as /devices/soc0/axi/e0002000.usb/ci_hdrc.0/usb1/1-1/1-1.2/1-1.2:1.0/0003:09DA:0260.0002/input/input1
hid-generic 0003:09DA:0260.0002: input,hidraw1: USB HID v1.10 Keyboard [  USB Keyboard] on usb-ci_hdrc.0-1.2/input0
input:   USB Keyboard System Control as /devices/soc0/axi/e0002000.usb/ci_hdrc.0/usb1/1-1/1-1.2/1-1.2:1.1/0003:09DA:0260.0003/input/input2
input:   USB Keyboard Consumer Control as /devices/soc0/axi/e0002000.usb/ci_hdrc.0/usb1/1-1/1-1.2/1-1.2:1.1/0003:09DA:0260.0003/input/input3
hid-generic 0003:09DA:0260.0003: input,hidraw2: USB HID v1.10 Device [  USB Keyboard] on usb-ci_hdrc.0-1.2/input1
ad9081 spi0.0: AD9081 Rev. 3 Grade 10 (API 1.2.2) probed
cf_axi_dds 44b10000.axi-ad9081-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x44B10000 mapped to 0xf1f310c6, probed DDS AD9081
cf_axi_adc 44a10000.axi-ad9081-rx-hpc: ADI AIM (10.01.b) at 0x44A10000 mapped to 0xbf799acc, probed ADC AD9081 as MASTER
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_init -> link_supported
hmc7044 spi1.0: hmc7044_jesd204_link_pre_setup: Link2 forcing continuous SYSREF mode
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_setup -> opt_setup_stage1
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_setup -> opt_setup_stage1
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition opt_setup_stage1 -> opt_setup_stage2
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage3
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage4
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage5
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition opt_setup_stage5 -> clocks_enable
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition clocks_enable -> link_enable
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition clocks_enable -> link_enable
ad9081 spi0.0: JESD RX (JTX) Link2 in DATA, SYNC deasserted, PLL locked, PHASE established, MODE valid
ad9081 spi0.0: JESD TX (JRX) Link0 0xF lanes in DATA
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_enable -> link_running
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_enable -> link_running
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_running -> opt_post_running_stage
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_running -> opt_post_running_stage
input: gpio_keys as /devices/soc0/gpio_keys/input/input4
of_cfs_init
of_cfs_init: OK
ALSA device list:
  #0: HDMI monitor
Warning: unable to open an initial console.
Freeing unused kernel memory: 40960K
Run /init as init process
  with arguments:
    /init
  with environment:
    HOME=/
    TERM=linux
udevd[92]: starting version 3.2.9
udevd[93]: starting eudev-3.2.9
FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
macb e000b000.ethernet eth0: PHY [e000b000.ethernet-ffffffff:07] driver [Marvell 88E1116R] (irq=POLL)
macb e000b000.ethernet eth0: configuring for phy/rgmii-id link mode
macb e000b000.ethernet eth0: Link is Up - 1Gbps/Full - flow control tx
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready

So the questions are:

1) is the configuration ok so far (see the measured link clock problem)?

2) how could I increase the decimation? I will put the information about the current failed attempt in a separate message.

Top Replies

andrearu Jun 21, 2022 in reply to lnagy +2 verified

Hello, we gave up this effort, and we are planning to implement a decimator and interpolator on the FPGA fabric.

It would still be interesting to find a trick to get a higher decimation for the ADC.

Parents

0 lnagy

on May 4, 2022 1:42 PM
On the RX link the Reported Link clock is incorrect.

In 8b/10b encoding (aka 204B) the Link Clock should be always lane rate / 40, in this case 125 MHz.

Since the design is using a configuration with F=8 , the device clock is half of the link clock. So the link layer core runs on two clocks, but this is not reflected in the device tree, see here.

You need to update it as below:

clocks = <&clkc 16>, <&axi_ad9081_adxcvr_rx 1>, <&hmc7044 10>, <&axi_ad9081_adxcvr_rx 0>; clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk";

similar tho this.

Thank you,

Laszlo
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0 andrearu on May 5, 2022 8:16 AM in reply to lnagy

Thanks, your suggestion solves the problem of the link clock in jesd_status!

As I mentioned before, I am trying to use a higher decimation rate (4x16) which should be supported. The error I'm getting is "In supported link got error from cb: -22". The lane rate should work at 2.5 GHz for RX. I recompiled the HDL with 2 lanes as before (JESD mode 4 for RX) and lane rate 2.5 GHz.

Dmesg output:

jesd204: /axi/spi@e0007000/hmc7044@0,jesd204:1,parent=spi1.0: Using as SYSREF provider
axi_adxcvr 44a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.05.a) using CPLL on GTX2 at 0x44A60000. Number of lanes: 2.
axi_adxcvr 44b60000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.05.a) using QPLL on GTX2 at 0x44B60000. Number of lanes: 4.
axi-jesd204-rx 44a90000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0x44A90000. Encoder 8b10b, width 4/8, lanes 2, jesd204-fsm.
axi-jesd204-tx 44b90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a) at 0x44B90000. Encoder 8b10b, width 4/4, lanes 4, jesd204-fsm.
axi_sysid 45000000.axi-sysid-0: AXI System ID core version (1.01.a) found
axi_sysid 45000000.axi-sysid-0: [ad9081_fmca_ebz] on [zc706] git branch <master> git <619e8043d06d08aaf647203d131fb1f0af021e5b> clean [2022-05-04 13:23:06] UTC
fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
usbcore: registered new interface driver snd-usb-audio
NET: Registered protocol family 10
Segment Routing with IPv6
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 36
Key type dns_resolver registered
Registering SWP/SWPB emulation handler
of-fpga-region fpga-full: FPGA Region probed
[drm] Initialized axi_hdmi_drm 1.0.0 20120930 for 70e00000.axi_hdmi on minor 0
Console: switching to colour frame buffer device 240x67
axi-hdmi 70e00000.axi_hdmi: [drm] fb0: axi_hdmi_drmdrm frame buffer device
ad9081 spi0.0: supply vdd not found, using dummy regulator
usb 1-1: new high-speed USB device number 2 using ci_hdrc
usb 1-1: New USB device found, idVendor=2109, idProduct=2813, bcdDevice=90.11
usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 1-1: Product: USB2.0 Hub
usb 1-1: Manufacturer: VIA Labs, Inc.
hub 1-1:1.0: USB hub found
hub 1-1:1.0: 4 ports detected
usb 1-1.1: new low-speed USB device number 3 using ci_hdrc
usb 1-1.1: New USB device found, idVendor=046d, idProduct=c00e, bcdDevice=11.10
usb 1-1.1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 1-1.1: Product: USB-PS/2 Optical Mouse
usb 1-1.1: Manufacturer: Logitech
input: Logitech USB-PS/2 Optical Mouse as /devices/soc0/axi/e0002000.usb/ci_hdrc.0/usb1/1-1/1-1.1/1-1.1:1.0/0003:046D:C00E.0001/input/input0
hid-generic 0003:046D:C00E.0001: input,hidraw0: USB HID v1.10 Mouse [Logitech USB-PS/2 Optical Mouse] on usb-ci_hdrc.0-1.1/input0
usb 1-1.2: new low-speed USB device number 4 using ci_hdrc
usb 1-1.2: New USB device found, idVendor=09da, idProduct=0260, bcdDevice= 2.50
usb 1-1.2: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 1-1.2: Product: USB Keyboard
usb 1-1.2: Manufacturer:
input:   USB Keyboard as /devices/soc0/axi/e0002000.usb/ci_hdrc.0/usb1/1-1/1-1.2/1-1.2:1.0/0003:09DA:0260.0002/input/input1
hid-generic 0003:09DA:0260.0002: input,hidraw1: USB HID v1.10 Keyboard [  USB Keyboard] on usb-ci_hdrc.0-1.2/input0
input:   USB Keyboard System Control as /devices/soc0/axi/e0002000.usb/ci_hdrc.0/usb1/1-1/1-1.2/1-1.2:1.1/0003:09DA:0260.0003/input/input2
input:   USB Keyboard Consumer Control as /devices/soc0/axi/e0002000.usb/ci_hdrc.0/usb1/1-1/1-1.2/1-1.2:1.1/0003:09DA:0260.0003/input/input3
hid-generic 0003:09DA:0260.0003: input,hidraw2: USB HID v1.10 Device [  USB Keyboard] on usb-ci_hdrc.0-1.2/input1
ad9081 spi0.0: AD9081 Rev. 3 Grade 10 (API 1.2.2) probed
cf_axi_dds 44b10000.axi-ad9081-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x44B10000 mapped to 0x081afb04, probed DDS AD9081
cf_axi_adc 44a10000.axi-ad9081-rx-hpc: ADI AIM (10.01.b) at 0x44A10000 mapped to 0x2c0a28e0, probed ADC AD9081 as MASTER
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition device_init -> link_init
jesd204: /axi/spi@e0007000/hmc7044@0,jesd204:1,parent=spi1.0: JESD204[0:0] In link_supported got error from cb: -22
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: Rolling back from 'link_init', got error -22
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition idle -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition idle -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition device_init -> link_init
jesd204: /axi/spi@e0007000/hmc7044@0,jesd204:1,parent=spi1.0: JESD204[0:0] In link_supported got error from cb: -22
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: Rolling back from 'link_init', got error -22
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition idle -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition idle -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition device_init -> link_init
jesd204: /axi/spi@e0007000/hmc7044@0,jesd204:1,parent=spi1.0: JESD204[0:0] In link_supported got error from cb: -22
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: Rolling back from 'link_init', got error -22
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition idle -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition idle -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition device_init -> link_init
jesd204: /axi/spi@e0007000/hmc7044@0,jesd204:1,parent=spi1.0: JESD204[0:0] In link_supported got error from cb: -22
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: Rolling back from 'link_init', got error -22
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: FSM completed with error -22
input: gpio_keys as /devices/soc0/gpio_keys/input/input4
of_cfs_init
of_cfs_init: OK
ALSA device list:
  #0: HDMI monitor
Warning: unable to open an initial console.
Freeing unused kernel memory: 40960K
Run /init as init process
udevd[94]: starting version 3.2.9
udevd[95]: starting eudev-3.2.9
FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
macb e000b000.ethernet eth0: PHY [e000b000.ethernet-ffffffff:07] driver [Marvell 88E1116R] (irq=POLL)
macb e000b000.ethernet eth0: configuring for phy/rgmii-id link mode
macb e000b000.ethernet eth0: Link is Up - 1Gbps/Full - flow control tx
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready

root@xilinx-zc706-2021_1:~#

Here is the new system-user.dtsi that includes the fix you suggested and the 4x16 decimation setting:

/include/ "system-conf.dtsi"
/ {
};

&hmc7044 {
    channel@12 { adi,divider = <24>; //TX REF CLK 
        };
    channel@8 { adi,divider = <48>; //RX REF CLK 
        };
};

&axi_ad9081_adxcvr_rx {
    clocks = <&hmc7044 8>; //change source clock to channel 8 of hmc7044
    adi,sys-clk-select = <XCVR_CPLL>;
};

&ad9081_adc0 { adi,decimation = <4>; };
&ad9081_adc1 { adi,decimation = <4>; };
&ad9081_adc2 { adi,decimation = <4>; };
&ad9081_adc3 { adi,decimation = <4>; };

&ad9081_rx_fddc_chan0 { adi,decimation = <16>; };
&ad9081_rx_fddc_chan1 { adi,decimation = <16>; };
&ad9081_rx_fddc_chan4 { adi,decimation = <16>; };
&ad9081_rx_fddc_chan5 { adi,decimation = <16>; };


&axi_ad9081_rx_jesd {
            clocks = <&clkc 16>, <&axi_ad9081_adxcvr_rx 1>, <&hmc7044 10>, <&axi_ad9081_adxcvr_rx 0>;
            clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk";
};

&axi_ad9081_tx_jesd {
            clocks = <&clkc 16>, <&axi_ad9081_adxcvr_tx 1>, <&hmc7044 6>, <&axi_ad9081_adxcvr_tx 0>;
            clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk";
};


&trx0_ad9081 {
    adi,tx-dacs {
        adi,dac-frequency-hz = /bits/ 64 <6000000000>;
        };
    adi,rx-adcs {
        adi,adc-frequency-hz = /bits/ 64 <2000000000>;
        adi,jesd-links { link@0 {
                    //test with two lanes L=2 M=8, mode 4
                    //see https://www.analog.com/media/en/technical-documentation/user-guides/ad9081-ad9082-ug-1578.pdf page 130
                    adi,link-mode = <4>;                         // JESD Quick Configuration Mode
                    adi,subclass = <1>;                          // JESD SUBCLASS 0,1,2
                    adi,version = <1>;                           // JESD VERSION 0=204A,1=204B,2=204C
                    adi,dual-link = <0>;                         // JESD Dual Link Mode
                    adi,converters-per-device = <8>;             // JESD M
                    adi,octets-per-frame = <8>;                  // JESD F
                    adi,frames-per-multiframe = <32>;            // JESD K
                    adi,converter-resolution = <16>;             // JESD N
                    adi,bits-per-sample = <16>;                  // JESD NP'
                    adi,control-bits-per-sample = <0>;           // JESD CS
                    adi,lanes-per-device = <2>;                  // JESD L
                    adi,samples-per-converter-per-frame = <1>;   // JESD S
                    adi,high-density = <0>;                      // JESD HD
            }; };
        };
};

HDL project diff (the only difference with the previous one is the RX rate parameter set to 2.5 GHz):

diff --git a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
index 17ce78089..4529d04ca 100644
--- a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
+++ b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
@@ -277,7 +277,8 @@ create_bd_port -dir I ref_clk_q1
 if {$ADI_PHY_SEL == 1} {
   for {set i 0} {$i < [expr max($TX_NUM_OF_LANES,$RX_NUM_OF_LANES)]} {incr i} {
     set quad_index [expr int($i / 4)]
-    ad_xcvrpll  ref_clk_q$quad_index  util_mxfe_xcvr/cpll_ref_clk_$i
+    #ad_xcvrpll  ref_clk_q$quad_index  util_mxfe_xcvr/cpll_ref_clk_$i
+    ad_xcvrpll  ref_clk_q1  util_mxfe_xcvr/cpll_ref_clk_$i
     if {[expr $i % 4] == 0} {
       ad_xcvrpll  ref_clk_q$quad_index  util_mxfe_xcvr/qpll_ref_clk_$i
     }
diff --git a/projects/ad9081_fmca_ebz/zc706/system_constr.xdc b/projects/ad9081_fmca_ebz/zc706/system_constr.xdc
index a3edb067d..7fde06e38 100644
--- a/projects/ad9081_fmca_ebz/zc706/system_constr.xdc
+++ b/projects/ad9081_fmca_ebz/zc706/system_constr.xdc
@@ -16,6 +16,8 @@ set_property         -dict {PACKAGE_PIN U27   IOSTANDARD LVDS_25  DIFF_TERM TRUE
 set_property         -dict {PACKAGE_PIN U26   IOSTANDARD LVDS_25  DIFF_TERM TRUa.rugliancich@temp-EXPERT:~/hdl_wiser5/projects/ad9081_fmca_ebz/zc706$ git diff
diff --git a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
index 17ce78089..4529d04ca 100644
--- a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
+++ b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
@@ -277,7 +277,8 @@ create_bd_port -dir I ref_clk_q1
 if {$ADI_PHY_SEL == 1} {
   for {set i 0} {$i < [expr max($TX_NUM_OF_LANES,$RX_NUM_OF_LANES)]} {incr i} {
     set quad_index [expr int($i / 4)]
-    ad_xcvrpll  ref_clk_q$quad_index  util_mxfe_xcvr/cpll_ref_clk_$i
+    #ad_xcvrpll  ref_clk_q$quad_index  util_mxfe_xcvr/cpll_ref_clk_$i
+    ad_xcvrpll  ref_clk_q1  util_mxfe_xcvr/cpll_ref_clk_$i
     if {[expr $i % 4] == 0} {
       ad_xcvrpll  ref_clk_q$quad_index  util_mxfe_xcvr/qpll_ref_clk_$i
     }
diff --git a/projects/ad9081_fmca_ebz/zc706/system_constr.xdc b/projects/ad9081_fmca_ebz/zc706/system_constr.xdc
index a3edb067d..7fde06e38 100644
--- a/projects/ad9081_fmca_ebz/zc706/system_constr.xdc
+++ b/projects/ad9081_fmca_ebz/zc706/system_constr.xdc
@@ -16,6 +16,8 @@ set_property         -dict {PACKAGE_PIN U27   IOSTANDARD LVDS_25  DIFF_TERM TRUE
 set_property         -dict {PACKAGE_PIN U26   IOSTANDARD LVDS_25  DIFF_TERM TRU:...skipping...
diff --git a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
index 17ce78089..4529d04ca 100644
--- a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
+++ b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
@@ -277,7 +277,8 @@ create_bd_port -dir I ref_clk_q1
 if {$ADI_PHY_SEL == 1} {
   for {set i 0} {$i < [expr max($TX_NUM_OF_LANES,$RX_NUM_OF_LANES)]} {incr i} {
     set quad_index [expr int($i / 4)]
-    ad_xcvrpll  ref_clk_q$quad_index  util_mxfe_xcvr/cpll_ref_clk_$i
+    #ad_xcvrpll  ref_clk_q$quad_index  util_mxfe_xcvr/cpll_ref_clk_$i
+    ad_xcvrpll  ref_clk_q1  util_mxfe_xcvr/cpll_ref_clk_$i
     if {[expr $i % 4] == 0} {
       ad_xcvrpll  ref_clk_q$quad_index  util_mxfe_xcvr/qpll_ref_clk_$i
     }
diff --git a/projects/ad9081_fmca_ebz/zc706/system_constr.xdc b/projects/ad9081_fmca_ebz/zc706/system_constr.xdc
index a3edb067d..7fde06e38 100644
--- a/projects/ad9081_fmca_ebz/zc706/system_constr.xdc
+++ b/projects/ad9081_fmca_ebz/zc706/system_constr.xdc
@@ -16,6 +16,8 @@ set_property         -dict {PACKAGE_PIN U27   IOSTANDARD LVDS_25  DIFF_TERM TRUE
 set_property         -dict {PACKAGE_PIN U26   IOSTANDARD LVDS_25  DIFF_TERM TRUE} [get_ports clkin6_p         ]    ; ## FMC0_CLK1_M2C_P     IO_L12P_T1_MRCC_13
 set_property         -dict {PACKAGE_PIN AD9                                     } [get_ports fpga_refclk_in_n ]    ; ## FMC0_GBTCLK0_M2C_N  MGTREFCLK0N_109
 set_property         -dict {PACKAGE_PIN AD10                                    } [get_ports fpga_refclk_in_p ]    ; ## FMC0_GBTCLK0_M2C_P  MGTREFCLK0P_109
+set_property         -dict {PACKAGE_PIN AA7                                     } [get_ports fpga_refclk2_in_n ]    ; 
+set_property         -dict {PACKAGE_PIN AA8                                     } [get_ports fpga_refclk2_in_p ]    ; 
 set_property  -quiet -dict {PACKAGE_PIN AG7                                     } [get_ports rx_data_n[2]     ]    ; ## FMC0_DP2_M2C_N      MGTXRXN2_109     FPGA_SERDIN_0_N
 set_property  -quiet -dict {PACKAGE_PIN AG8                                     } [get_ports rx_data_p[2]     ]    ; ## FMC0_DP2_M2C_P      MGTXRXP2_109     FPGA_SERDIN_0_P
 set_property  -quiet -dict {PACKAGE_PIN AH9                                     } [get_ports rx_data_n[0]     ]    ; ## FMC0_DP0_M2C_N      MGTXRXN0_109     FPGA_SERDIN_1_N
diff --git a/projects/ad9081_fmca_ebz/zc706/system_project.tcl b/projects/ad9081_fmca_ebz/zc706/system_project.tcl
index cbdbf89fa..fe2c32863 100644
--- a/projects/ad9081_fmca_ebz/zc706/system_project.tcl
+++ b/projects/ad9081_fmca_ebz/zc706/system_project.tcl
@@ -31,10 +31,10 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
 adi_project ad9081_fmca_ebz_zc706 0 [list \
   JESD_MODE    8B10B \
-  RX_LANE_RATE [get_env_param RX_RATE      10 ] \
-  TX_LANE_RATE [get_env_param TX_RATE      10 ] \
+  RX_LANE_RATE [get_env_param RX_RATE      2.5 ] \
+  TX_LANE_RATE [get_env_param TX_RATE      5 ] \
   RX_JESD_M    [get_env_param RX_JESD_M    8 ] \
-  RX_JESD_L    [get_env_param RX_JESD_L    4 ] \
+  RX_JESD_L    [get_env_param RX_JESD_L    2 ] \
   RX_JESD_S    [get_env_param RX_JESD_S    1 ] \
   RX_JESD_NP   [get_env_param RX_JESD_NP   16] \
   RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \
diff --git a/projects/ad9081_fmca_ebz/zc706/system_top.v b/projects/ad9081_fmca_ebz/zc706/system_top.v
index a6f834daf..4182129d6 100644
--- a/projects/ad9081_fmca_ebz/zc706/system_top.v
+++ b/projects/ad9081_fmca_ebz/zc706/system_top.v

The jesd_status utility shows that the both links are disabled, of course (the FSM failed).

(DEVICES) Found 2 JESD204 Link Layer peripherals

  (0): axi-jesd204-rx/44a90000.axi-jesd204-rx  [*]
  (1): axi-jesd204-tx/44b90000.axi-jesd204-tx

  (STATUS)
  Link is                      disabled
  Link Status
  Measured Link Clock (MHz)    62.500
  Reported Link Clock (MHz)    62.500
  Measured Device Clock (MHz)  250.000
  Reported Device Clock (MHz)  250.000
  Desired Device Clock (MHz)   15.625
  Lane rate (MHz)
  Lane rate / 40 (MHz)
  LMFC rate (MHz)
  SYSREF captured
  SYSREF alignment error
  SYNC~

  (LANE STATUS)
  Lane#                             0      1
  Errors                            0      0
  Latency (Multiframes/Octets)      0/0    0/0
  CGS State                         INIT   INIT
  Initial Frame Sync                No     No
  Initial Lane Alignment Sequence

  (DEVICES) Found 2 JESD204 Link Layer peripherals

  (0): axi-jesd204-rx/44a90000.axi-jesd204-rx
  (1): axi-jesd204-tx/44b90000.axi-jesd204-tx  [*]

  (STATUS)
  Link is                      disabled
  Link Status
  Measured Link Clock (MHz)    125.000
  Reported Link Clock (MHz)    125.000
  Measured Device Clock (MHz)  249.998
  Reported Device Clock (MHz)  250.000
  Desired Device Clock (MHz)   62.500
  Lane rate (MHz)
  Lane rate / 40 (MHz)
  LMFC rate (MHz)
  SYSREF captured
  SYSREF alignment error
  SYNC~

Do I perhaps need to retune the parameters of the JESD (see https://wiki.analog.com/resources/fpga/docs/xgt_wizard) besides the ones set via "system_project.tcl"?

Thanks for your help.

Andrea R.

0 lnagy

on May 5, 2022 1:56 PM in reply to andrearu
Your Rx and Tx link clock look correct, however the Device clock in both links is 250 instead of 62.5 MHz for Tx and 32.250 MHz for Rx.

Re-tuning of the xcvr parameters is a good idea, however first you should fix the device clocks.

Thank you,

Laszlo
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0 andrearu on May 9, 2022 4:40 PM in reply to lnagy

Hi,

I believe that the device clocks are wrong because the FSM fails and they are left unconfigured by the driver.

I made a step forward about the error "In supported link got error from cb: -22" when I tried to set the ADC clock to 2 GHz, decimation=64.

I put #define DEBUG in the hmc7044.c driver in the kernel to get the debug messages. I found out that there is some code that chooses a SYSREF clock frequency that is a submultiple of local multi frame clock LMFC of both links (see AD9081 user guide, pag.28 SYSREF modes).

If the LMFC frequencies (in Hz) have a fractional part, the code may fail to compute a valid setting. In my case LMFC for the ADC is LMFC = (DACLK/(K*DECIMATION)) = 2000000000/(32*64) = 976562.5 Hz , the .5 fractional part gets truncated and code fails to compute a valid SYSREF setting.

I changed the main DAC clock from 6 GHz to 6.144 GHz and the ADC clock from 2 to 2.048 GHz to avoid this problem.

The new error is now: "cannot set lane rate 2560000 kHz".

part of dmesg:

jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_init -> link_supported
hmc7044 spi1.0: hmc7044_jesd204_link_pre_setup: Link2 forcing continuous SYSREF mode
axi-jesd204-rx 44a90000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_pre_setup: Link2 set lane rate 2560000 kHz failed (-22)
jesd204: /fpga-axi@0/axi-jesd204-rx@44a90000,jesd204:4,parent=44a90000.axi-jesd204-rx: JESD204[0:2] In link_pre_setup got error from cb: -22

The system-user.dtsi that I'm using is:

/include/ "system-conf.dtsi"
/ {
};

&hmc7044 {
    adi,pll2-output-frequency = <3072000000>;
    channel@12 { adi,divider = <24>; //TX REF CLK 
        };
    channel@8 { adi,divider = <96>; //RX REF CLK 
        };
};

&axi_ad9081_adxcvr_rx {
    clocks = <&hmc7044 8>; //change source clock to channel 8 of hmc7044
    adi,sys-clk-select = <XCVR_CPLL>;
    //adi,out-clk-select = <XCVR_REFCLK_DIV2>;
};

&ad9081_adc0 { adi,decimation = <4>; };
&ad9081_adc1 { adi,decimation = <4>; };
&ad9081_adc2 { adi,decimation = <4>; };
&ad9081_adc3 { adi,decimation = <4>; };

&ad9081_rx_fddc_chan0 { adi,decimation = <16>; };
&ad9081_rx_fddc_chan1 { adi,decimation = <16>; };
&ad9081_rx_fddc_chan4 { adi,decimation = <16>; };
&ad9081_rx_fddc_chan5 { adi,decimation = <16>; };


&axi_ad9081_rx_jesd {
            clocks = <&clkc 16>, <&axi_ad9081_adxcvr_rx 1>, <&hmc7044 10>, <&axi_ad9081_adxcvr_rx 0>;
            clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk";
};

&axi_ad9081_tx_jesd {
            clocks = <&clkc 16>, <&axi_ad9081_adxcvr_tx 1>, <&hmc7044 6>, <&axi_ad9081_adxcvr_tx 0>;
            clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk";
};

&trx0_ad9081 {
    adi,tx-dacs {
        adi,dac-frequency-hz = /bits/ 64 <6144000000>;
        };
    adi,rx-adcs {
        adi,adc-frequency-hz = /bits/ 64 <2048000000>;
        adi,jesd-links { link@0 {
                    //test with two lanes L=2 M=8, mode 4
                    //see https://www.analog.com/media/en/technical-documentation/user-guides/ad9081-ad9082-ug-1578.pdf page 130
                    adi,link-mode = <4>;                         // JESD Quick Configuration Mode
                    adi,subclass = <1>;                          // JESD SUBCLASS 0,1,2
                    adi,version = <1>;                           // JESD VERSION 0=204A,1=204B,2=204C
                    adi,dual-link = <0>;                         // JESD Dual Link Mode
                    adi,converters-per-device = <8>;             // JESD M
                    adi,octets-per-frame = <8>;                  // JESD F
                    adi,frames-per-multiframe = <32>;            // JESD K
                    adi,converter-resolution = <16>;             // JESD N
                    adi,bits-per-sample = <16>;                  // JESD NP'
                    adi,control-bits-per-sample = <0>;           // JESD CS
                    adi,lanes-per-device = <2>;                  // JESD L
                    adi,samples-per-converter-per-frame = <1>;   // JESD S
                    adi,high-density = <0>;                      // JESD HD
            }; };
        };
};

Jesd status RX

  (DEVICES) Found 2 JESD204 Link Layer peripherals

  (0): axi-jesd204-rx/44a90000.axi-jesd204-rx  [*]
  (1): axi-jesd204-tx/44b90000.axi-jesd204-tx

  (STATUS)
  Link is                      disabled
  Link Status
  Measured Link Clock (MHz)    64.000
  Reported Link Clock (MHz)    64.000
  Measured Device Clock (MHz)  31.999
  Reported Device Clock (MHz)  32.000
  Desired Device Clock (MHz)   16.000
  Lane rate (MHz)
  Lane rate / 40 (MHz)
  LMFC rate (MHz)
  SYSREF captured
  SYSREF alignment error
  SYNC~

  (LANE STATUS)
  Lane#                             0      1
  Errors                            0      0
  Latency (Multiframes/Octets)      0/0    0/0
  CGS State                         INIT   INIT
  Initial Frame Sync                No     No
  Initial Lane Alignment Sequence

Jesd status TX

(DEVICES) Found 2 JESD204 Link Layer peripherals

  (0): axi-jesd204-rx/44a90000.axi-jesd204-rx
  (1): axi-jesd204-tx/44b90000.axi-jesd204-tx  [*]

  (STATUS)
  Link is                      disabled
  Link Status
  Measured Link Clock (MHz)    127.998
  Reported Link Clock (MHz)    128.000
  Measured Device Clock (MHz)  255.998
  Reported Device Clock (MHz)  256.000
  Desired Device Clock (MHz)   64.000
  Lane rate (MHz)
  Lane rate / 40 (MHz)
  LMFC rate (MHz)
  SYSREF captured
  SYSREF alignment error
  SYNC~

I noticed that if I put a higher (but wrong) REFCLK the lane can go to 2.5 GHz and also JESD link goes up, so I guess this is related to the REFCLK.

Thank you

Andrea R.

0 andrearu on May 10, 2022 12:10 PM in reply to andrearu

Ok, I just checked, with the CPLL and 64 MHz refclock I cannot generate a lane rate of 2.56 GHz (see Xilinx UG476 p.48). See also xilinx_transceiver.c source. To reach the minimum VCO frequency of 1.6 GHz I need N1=5, N2=5, M=1 and I get VCO=1.6 GHz (the minimum allowed). The lane rate is then 3.2 GHz or a submultiple (1.6 GHz, etc.), see equation 2.2.

To use all the converters (M=8) I need to find a different clocking configuration (it would help to have F=4, but there is no such configuration with 2 lanes), or maybe explore the configurations with 12 bits (NP=12).
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0 lnagy

on Jun 20, 2022 9:50 AM in reply to andrearu
Did you managed to find a solution to your problem ?

Thanks,

Laszlo
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+1 andrearu on Jun 21, 2022 2:50 PM in reply to lnagy

Hello, we gave up this effort, and we are planning to implement a decimator and interpolator on the FPGA fabric.

It would still be interesting to find a trick to get a higher decimation for the ADC.
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+1 andrearu on Jun 21, 2022 2:50 PM in reply to lnagy

Hello, we gave up this effort, and we are planning to implement a decimator and interpolator on the FPGA fabric.

It would still be interesting to find a trick to get a higher decimation for the ADC.
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