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Zynq processor settings in the HDL

Dear all,

        We downloaded the HDL code for capturing ADRV9009 data in ZC706 processor.Then we wanted to add FFT example into HDL code. This FFT example interfaces with the zynq processor through AXI_DMA.

Firstly, we tested the standalone FFT example.

Then we opened the ADRV9009 HDL project in the Vivado tool and deleted all the modules from the HDL except, Zynq processor and added fft example code into the project. The FFT example does not work.

Then we also deleted the Zynq processor from the ADRV9009 HDL project, and added new Zynq processor with default configuration/settings. The FFT example starts working.

This debugging process pointed out that there are some default setting of Zynq processor in HDL code that are hindering AXI-DMA core from working in the FFT example.

Can anyone guide us that what are the settings of the Zynq processor in HDL core that are hindering AXI-DMA core from working?

Many thanks,

Best regards,

Avais

Parents Reply
  • We have further narrowed down the problem.

    In the design, where we use Zynq initialized by ADI in HDL project, and Zynq does not get interrupt. We found that when we remove the concat ip core (core used to connect interrupts from DMA), and connect one of the interrupts of the DMA with the ZYNQ. The ZYNQ gets the interrupt.

    This shows that some Zynq setting by the ADI in the HDL project is not working with concat ip core

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