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Any idea of adding custom codes on User Logic RX/TX in FPGA HDL core?


When I was reading the presentation slides of "ARM PlutoSDR With Custom Applications" by MICHAEL HENNERICH, I noticed there is user logic RX/TX in FPGA HDL cores.

And I believe that we could add our own customized codes there. Does any one know how should I do that? Anyone has tried it?

I added the link to the slides. What I am asking is in page 7 and 8, "User Logic RX/TX".