HMC7043
Recommended for New Designs
The HMC7043 is designed to meet the requirements of multicarrier GSM and LTE base station designs, and offers a wide range of clock management and distribution...
Datasheet
HMC7043 on Analog.com
Hi there,
I'm currently working on developing a design that works with the Quad MxFE with a single Tx and Rx channel operating per MxFE.
My setup and JESD parameters are as follows:
1Txs / 1Rxs per MxFE
DAC_CLK = 12GSPS
ADC_CLK = 3GSPS
Tx I/Q Rate: 3 GSPS (Interpolation of 4x1)
Rx I/Q Rate: 1.5 GSPS (Decimation of 2x1)
DAC JESD204C: Mode 12, L=4, M=2, N=N'=16
ADC JESD204C: Mode 7, L=2, M=2, N=N'=16
DAC-Side JESD204C Lane Rate: 24.75Gbps
ADC-Side JESD204C Lane Rate: 24.75Gbps
I have compiled a new FPGA bitfile for this setup, with the following compilation parameters:
JESD_MODE=64B66B
RX_RATE=24.75
TX_RATE=24.75
RX_PLL_SEL=1
TX_PLL_SEL=1
REF_CLK_RATE=250
RX_JESD_L=2
RX_JESD_M=2
RX_JESD_S=1
RX_JESD_NP=16
TX_JESD_L=4
TX_JESD_M=2
TX_JESD_S=1
TX_JESD_NP=16
RX_KS_PER_CHANNEL=16
TX_KS_PER_CHANNEL=16
Synthesis and implementation of the design went without trouble, and I created a new device tree to set things up correctly:
// SPDX-License-Identifier: GPL-2.0
/*
* Analog Devices Quad-MxFE
* https://wiki.analog.com/resources/eval/user-guides/quadmxfe
* https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9081
* https://wiki.analog.com/resources/eval/user-guides/ad_quadmxfe1_ebz/ad_quadmxfe1_ebz_hdl
*
* hdl_project: <ad_quadmxfe1_ebz/vcu118>
* board_revision: <>
*
* Copyright (C) 2019-2020 Analog Devices Inc.
*
* Adapted by Dr. Kari Clark for 4x ADC and 4x DAC operation in February 2022
*/
#include <dt-bindings/iio/frequency/hmc7044.h>
#include <dt-bindings/iio/adc/adi,ad9081.h>
#include <dt-bindings/gpio/gpio.h>
#include "vcu118_quad_ad9081.dtsi"
// This setup assumes 500MHz clock into J41 (0 dBm)
// ad9081_204c_4dac_12gsps_4adc_6gsps_iq:
// * 1Txs / 1Rxs per MxFE
// * DAC_CLK = 12GSPS
// * ADC_CLK = 3GSPS
// * Tx I/Q Rate: 3 GSPS (Interpolation of 4x1)
// * Rx I/Q Rate: 1.5 GSPS (Decimation of 2x1)
// * DAC JESD204C: Mode 12, L=4, M=2, N=N'=16
// * ADC JESD204C: Mode 7, L=2, M=2, N=N'=16
// * DAC-Side JESD204C Lane Rate: 24.75Gbps
// * ADC-Side JESD204C Lane Rate: 24.75Gbps
// HDL Synthesis Parameters:
// JESD_MODE=64B66B
// RX_RATE=24.75
// TX_RATE=24.75
// REF_CLK_RATE=250
// RX_JESD_M=2
// RX_JESD_L=2
// RX_JESD_S=1
// RX_JESD_NP=16
// TX_JESD_M=2
// TX_JESD_L=4
// TX_JESD_S=1
// TX_JESD_NP=16
// RX_PLL_SEL=1
// TX_PLL_SEL=1
// RX_KS_PER_CHANNEL=2 (maybe 4?)
// TX_KS_PER_CHANNEL=32
#define ADRF4360_RF16_FREQUENCY_HZ 12000000000
#define HMC7043_FPGA_XCVR_CLKDIV 2
#define HMC7043_FPGA_LINK_CLKDIV_TX 2
#define HMC7043_FPGA_LINK_CLKDIV_RX 2
#define HMC7043_SYSREF_CLKDIV 1024
#define AD9081_DAC_FREQUENCY ADRF4360_RF16_FREQUENCY_HZ
#define AD9081_ADC_FREQUENCY 3000000000
/* TX path */
#define AD9081_TX_LANERATE_KHZ 24750000
#define AD9081_TX_LINK_CLK 375000000
#define AD9081_TX_MAIN_INTERPOLATION 4
#define AD9081_TX_CHAN_INTERPOLATION 1
#ifndef AD9081_TX_MAIN_NCO_SHIFT
#define AD9081_TX_MAIN_NCO_SHIFT 3000000000
#endif
#ifndef AD9081_TX_CHAN_NCO_SHIFT
#define AD9081_TX_CHAN_NCO_SHIFT 0
#endif
#define AD9081_GAIN 1024
#define AD9081_TX_JESD_MODE 12
#define AD9081_TX_JESD_SUBCLASS 1
#define AD9081_TX_JESD_VERSION 2
#define AD9081_TX_JESD_M 2
#define AD9081_TX_JESD_F 1
#define AD9081_TX_JESD_K 256
#define AD9081_TX_JESD_N 16
#define AD9081_TX_JESD_NP 16
#define AD9081_TX_JESD_CS 0
#define AD9081_TX_JESD_L 4
#define AD9081_TX_JESD_S 1
#define AD9081_TX_JESD_HD 1
#define AD9081_JRX_TPL_PHASE_ADJUST 16
/* RX path */
#define AD9081_RX_LANERATE_KHZ 24750000
#define AD9081_RX_LINK_CLK 375000000
#define AD9081_RX_MAIN_DECIMATION 2
#define AD9081_RX_CHAN_DECIMATION 1
#ifndef AD9081_RX_MAIN_NCO_SHIFT
#define AD9081_RX_MAIN_NCO_SHIFT 1000000000
#endif
#ifndef AD9081_RX_CHAN_NCO_SHIFT
#define AD9081_RX_CHAN_NCO_SHIFT 0
#endif
#ifndef AD9081_ADC_NYQUIST_ZONE
#define AD9081_ADC_NYQUIST_ZONE AD9081_ADC_NYQUIST_ZONE_EVEN
#endif
#define AD9081_RX_JESD_MODE 7
#define AD9081_RX_JESD_SUBCLASS 1
#define AD9081_RX_JESD_VERSION 2
#define AD9081_RX_JESD_M 2
#define AD9081_RX_JESD_F 2
#define AD9081_RX_JESD_K 128
#define AD9081_RX_JESD_N 16
#define AD9081_RX_JESD_NP 16
#define AD9081_RX_JESD_CS 0
#define AD9081_RX_JESD_L 2
#define AD9081_RX_JESD_S 1
#define AD9081_RX_JESD_HD 0
/ {
model = "Analog Devices AD-QUADMXFE1-EBZ Rev.C";
};
&gpio_hmc425a {
compatible = "adi,hmc540s";
ctrl-gpios = <&axi_gpio 38 GPIO_ACTIVE_HIGH>,
<&axi_gpio 37 GPIO_ACTIVE_HIGH>,
<&axi_gpio 36 GPIO_ACTIVE_HIGH>,
<&axi_gpio 35 GPIO_ACTIVE_HIGH>;
};
&fmc_i2c {
current_limiter@58 {
compatible = "adi,adm1177-iio";
reg = <0x58>;
adi,r-sense-mohm = <10>; /* 10 mOhm */
adi,shutdown-threshold-ma = <10000>; /* 10 A */
adi,vrange-high-enable;
};
};
/ {
rx_fixed_linerate: clock@2 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <AD9081_RX_LANERATE_KHZ>;
clock-output-names = "rx_lane_clk";
};
tx_fixed_linerate: clock@3 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <AD9081_TX_LANERATE_KHZ>;
clock-output-names = "tx_lane_clk";
};
rx_fixed_link_clk: clock@4 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <AD9081_RX_LINK_CLK>;
clock-output-names = "rx_link_clk";
};
tx_fixed_link_clk: clock@5 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <AD9081_TX_LINK_CLK>;
clock-output-names = "tx_link_clk";
};
};
/delete-node/ &axi_ad9081_adxcvr_rx;
/delete-node/ &axi_ad9081_adxcvr_tx;
&axi_ad9081_rx_jesd {
clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";
clocks = <&clk_bus_0>, <&hmc7043 2>, <&rx_fixed_link_clk>, <&rx_fixed_linerate>;
jesd204-inputs = <&hmc7043 0 FRAMER_LINK0_RX>; /* omit axi_ad9081_adxcvr_rx */
};
&axi_ad9081_tx_jesd {
clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";
clocks = <&clk_bus_0>, <&hmc7043 4>, <&tx_fixed_link_clk>, <&tx_fixed_linerate>;
jesd204-inputs = <&hmc7043 0 DEFRAMER_LINK0_TX>; /* omit axi_ad9081_adxcvr_tx */
};
&rx_dma {
/delete-node/ adi,channels; /* This comes from the synthesis paramtes */
};
&tx_dma {
/delete-node/ adi,channels; /* This comes from the synthesis paramtes */
};
&adf4371_clk0 {
channel@2 {
reg = <2>;
adi,power-up-frequency = /bits/ 64 <ADRF4360_RF16_FREQUENCY_HZ>;
};
};
&adf4371_clk1 {
channel@2 {
reg = <2>;
adi,power-up-frequency = /bits/ 64 <ADRF4360_RF16_FREQUENCY_HZ>;
};
};
&adf4371_clk2 {
channel@2 {
reg = <2>;
adi,power-up-frequency = /bits/ 64 <ADRF4360_RF16_FREQUENCY_HZ>;
};
};
&adf4371_clk3 {
channel@2 {
reg = <2>;
adi,power-up-frequency = /bits/ 64 <ADRF4360_RF16_FREQUENCY_HZ>;
};
};
&hmc7043 {
hmc7043_c0: channel@0 {
reg = <0>;
adi,extended-name = "FPGA_REFCLK";
adi,divider = <HMC7043_FPGA_XCVR_CLKDIV>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7043_c1: channel@1 {
reg = <1>;
adi,extended-name = "SYSREF_FPGA";
adi,divider = <HMC7043_SYSREF_CLKDIV>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVPECL>;
adi,coarse-digital-delay = <0>;
adi,fine-analog-delay = <0>;
adi,output-mux-mode = <0>;
adi,jesd204-sysref-chan;
};
hmc7043_c2: channel@2 {
reg = <2>;
adi,extended-name = "RX_CORE_LINK_CLK";
adi,divider = <HMC7043_FPGA_LINK_CLKDIV_RX>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
/delete-node/ hmc7043_c3;
hmc7043_c4: channel@4 {
reg = <4>;
adi,extended-name = "TX_CORE_LINK_CLK";
adi,divider = <HMC7043_FPGA_LINK_CLKDIV_TX>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
/delete-node/ hmc7043_c5;
/delete-node/ hmc7043_c6;
hmc7043_c7: channel@7 {
reg = <7>;
adi,extended-name = "SYSREF_MXFE0";
adi,divider = <HMC7043_SYSREF_CLKDIV>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVPECL>;
adi,coarse-digital-delay = <0>;
adi,fine-analog-delay = <0>;
adi,output-mux-mode = <0>;
adi,jesd204-sysref-chan;
};
/delete-node/ hmc7043_c8;
hmc7043_c9: channel@9 {
reg = <9>;
adi,extended-name = "SYSREF_MXFE1";
adi,divider = <HMC7043_SYSREF_CLKDIV>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVPECL>;
adi,coarse-digital-delay = <0>;
adi,fine-analog-delay = <0>;
adi,output-mux-mode = <0>;
adi,jesd204-sysref-chan;
};
/delete-node/ hmc7043_c10;
hmc7043_c11: channel@11 {
reg = <11>;
adi,extended-name = "SYSREF_MXFE2";
adi,divider = <HMC7043_SYSREF_CLKDIV>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVPECL>;
adi,coarse-digital-delay = <0>;
adi,fine-analog-delay = <0>;
adi,output-mux-mode = <0>;
adi,jesd204-sysref-chan;
};
/delete-node/ hmc7043_c12;
hmc7043_c13: channel@13 {
reg = <13>;
adi,extended-name = "SYSREF_MXFE3";
adi,divider = <HMC7043_SYSREF_CLKDIV>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVPECL>;
adi,coarse-digital-delay = <0>;
adi,fine-analog-delay = <0>;
adi,output-mux-mode = <0>;
adi,jesd204-sysref-chan;
};
};
&trx0_ad9081 {
/delete-property/ adi,jesd-sync-pins-01-swap-enable;
adi,jesd-sync-pin-0a-cmos-enable;
adi,tx-dacs {
#size-cells = <0>;
#address-cells = <1>;
adi,dac-frequency-hz = /bits/ 64 <AD9081_DAC_FREQUENCY>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <AD9081_TX_MAIN_INTERPOLATION>;
trx0_ad9081_dac0: dac@0 {
reg = <0>;
adi,crossbar-select = <&trx0_ad9081_tx_fddc_chan0>;
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_MAIN_NCO_SHIFT>;
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <AD9081_TX_CHAN_INTERPOLATION>;
trx0_ad9081_tx_fddc_chan0: channel@0 {
reg = <0>;
adi,gain = <AD9081_GAIN>; /* gain_dB = 20*log_10(value/2048) */
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_CHAN_NCO_SHIFT>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
trx0_ad9081_tx_jesd_l0: link@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
adi,tpl-phase-adjust = <AD9081_JRX_TPL_PHASE_ADJUST>;
adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
adi,link-mode = <AD9081_TX_JESD_MODE>; /* JESD Quick Configuration Mode */
adi,subclass = <AD9081_TX_JESD_SUBCLASS>; /* JESD SUBCLASS 0,1,2 */
adi,version = <AD9081_TX_JESD_VERSION>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,converters-per-device = <AD9081_TX_JESD_M>; /* JESD M */
adi,octets-per-frame = <AD9081_TX_JESD_F>; /* JESD F */
adi,frames-per-multiframe = <AD9081_TX_JESD_K>; /* JESD K */
adi,converter-resolution = <AD9081_TX_JESD_N>; /* JESD N */
adi,bits-per-sample = <AD9081_TX_JESD_N>; /* JESD NP' */
adi,control-bits-per-sample = <AD9081_TX_JESD_CS>; /* JESD CS */
adi,lanes-per-device = <AD9081_TX_JESD_L>; /* JESD L */
adi,samples-per-converter-per-frame = <AD9081_TX_JESD_S>; /* JESD S */
adi,high-density = <AD9081_TX_JESD_HD>; /* JESD HD */
};
};
};
adi,rx-adcs {
#size-cells = <0>;
#address-cells = <1>;
adi,adc-frequency-hz = /bits/ 64 <AD9081_ADC_FREQUENCY>;
adi,nyquist-zone = <AD9081_ADC_NYQUIST_ZONE>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
trx0_ad9081_adc2: adc@2 {
reg = <2>;
adi,decimation = <AD9081_RX_MAIN_DECIMATION>;
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_RX_MAIN_NCO_SHIFT>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
trx0_ad9081_rx_fddc_chan4: channel@4 {
reg = <4>;
adi,decimation = <AD9081_RX_CHAN_DECIMATION>;
adi,gain = <AD9081_GAIN>; /* gain_dB = 20*log_10(value/2048) */
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_RX_CHAN_NCO_SHIFT>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
trx0_ad9081_rx_jesd_l0: link@0 {
reg = <0>;
adi,converter-select =
<&trx0_ad9081_rx_fddc_chan4 FDDC_I>, <&trx0_ad9081_rx_fddc_chan4 FDDC_Q>;
adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
adi,link-mode = <AD9081_RX_JESD_MODE>; /* JESD Quick Configuration Mode */
adi,subclass = <AD9081_RX_JESD_SUBCLASS>; /* JESD SUBCLASS 0,1,2 */
adi,version = <AD9081_RX_JESD_VERSION>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,device-id = <3>;
adi,converters-per-device = <AD9081_RX_JESD_M>; /* JESD M */
adi,octets-per-frame = <AD9081_RX_JESD_F>; /* JESD F */
adi,frames-per-multiframe = <AD9081_RX_JESD_K>; /* JESD K */
adi,converter-resolution = <AD9081_RX_JESD_N>; /* JESD N */
adi,bits-per-sample = <AD9081_RX_JESD_NP>; /* JESD NP' */
adi,control-bits-per-sample = <AD9081_RX_JESD_CS>; /* JESD CS */
adi,lanes-per-device = <AD9081_RX_JESD_L>; /* JESD L */
adi,samples-per-converter-per-frame = <AD9081_RX_JESD_S>; /* JESD S */
adi,high-density = <AD9081_RX_JESD_HD>; /* JESD HD */
};
};
};
};
&trx1_ad9081 {
/delete-property/ adi,jesd-sync-pins-01-swap-enable;
adi,jesd-sync-pin-0a-cmos-enable;
adi,tx-dacs {
#size-cells = <0>;
#address-cells = <1>;
adi,dac-frequency-hz = /bits/ 64 <AD9081_DAC_FREQUENCY>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <AD9081_TX_MAIN_INTERPOLATION>;
trx1_ad9081_dac0: dac@0 {
reg = <0>;
adi,crossbar-select = <&trx1_ad9081_tx_fddc_chan0>;
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_MAIN_NCO_SHIFT>;
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <AD9081_TX_CHAN_INTERPOLATION>;
trx1_ad9081_tx_fddc_chan0: channel@0 {
reg = <0>;
adi,gain = <AD9081_GAIN>; /* gain_dB = 20*log_10(value/2048) */
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_CHAN_NCO_SHIFT>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
trx1_ad9081_tx_jesd_l0: link@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
adi,tpl-phase-adjust = <AD9081_JRX_TPL_PHASE_ADJUST>;
adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
adi,link-mode = <AD9081_TX_JESD_MODE>; /* JESD Quick Configuration Mode */
adi,subclass = <AD9081_TX_JESD_SUBCLASS>; /* JESD SUBCLASS 0,1,2 */
adi,version = <AD9081_TX_JESD_VERSION>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,converters-per-device = <AD9081_TX_JESD_M>; /* JESD M */
adi,octets-per-frame = <AD9081_TX_JESD_F>; /* JESD F */
adi,frames-per-multiframe = <AD9081_TX_JESD_K>; /* JESD K */
adi,converter-resolution = <AD9081_TX_JESD_N>; /* JESD N */
adi,bits-per-sample = <AD9081_TX_JESD_N>; /* JESD NP' */
adi,control-bits-per-sample = <AD9081_TX_JESD_CS>; /* JESD CS */
adi,lanes-per-device = <AD9081_TX_JESD_L>; /* JESD L */
adi,samples-per-converter-per-frame = <AD9081_TX_JESD_S>; /* JESD S */
adi,high-density = <AD9081_TX_JESD_HD>; /* JESD HD */
};
};
};
adi,rx-adcs {
#size-cells = <0>;
#address-cells = <1>;
adi,adc-frequency-hz = /bits/ 64 <AD9081_ADC_FREQUENCY>;
adi,nyquist-zone = <AD9081_ADC_NYQUIST_ZONE>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
trx1_ad9081_adc2: adc@2 {
reg = <2>;
adi,decimation = <AD9081_RX_MAIN_DECIMATION>;
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_RX_MAIN_NCO_SHIFT>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
trx1_ad9081_rx_fddc_chan4: channel@4 {
reg = <4>;
adi,decimation = <AD9081_RX_CHAN_DECIMATION>;
adi,gain = <AD9081_GAIN>; /* gain_dB = 20*log_10(value/2048) */
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_RX_CHAN_NCO_SHIFT>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
trx1_ad9081_rx_jesd_l0: link@0 {
reg = <0>;
adi,converter-select =
<&trx1_ad9081_rx_fddc_chan4 FDDC_I>, <&trx1_ad9081_rx_fddc_chan4 FDDC_Q>;
adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
adi,link-mode = <AD9081_RX_JESD_MODE>; /* JESD Quick Configuration Mode */
adi,subclass = <AD9081_RX_JESD_SUBCLASS>; /* JESD SUBCLASS 0,1,2 */
adi,version = <AD9081_RX_JESD_VERSION>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,device-id = <3>;
adi,converters-per-device = <AD9081_RX_JESD_M>; /* JESD M */
adi,octets-per-frame = <AD9081_RX_JESD_F>; /* JESD F */
adi,frames-per-multiframe = <AD9081_RX_JESD_K>; /* JESD K */
adi,converter-resolution = <AD9081_RX_JESD_N>; /* JESD N */
adi,bits-per-sample = <AD9081_RX_JESD_NP>; /* JESD NP' */
adi,control-bits-per-sample = <AD9081_RX_JESD_CS>; /* JESD CS */
adi,lanes-per-device = <AD9081_RX_JESD_L>; /* JESD L */
adi,samples-per-converter-per-frame = <AD9081_RX_JESD_S>; /* JESD S */
adi,high-density = <AD9081_RX_JESD_HD>; /* JESD HD */
};
};
};
};
&trx2_ad9081 {
/delete-property/ adi,jesd-sync-pins-01-swap-enable;
adi,jesd-sync-pin-0a-cmos-enable;
adi,tx-dacs {
#size-cells = <0>;
#address-cells = <1>;
adi,dac-frequency-hz = /bits/ 64 <AD9081_DAC_FREQUENCY>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <AD9081_TX_MAIN_INTERPOLATION>;
trx2_ad9081_dac0: dac@0 {
reg = <0>;
adi,crossbar-select = <&trx2_ad9081_tx_fddc_chan0>;
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_MAIN_NCO_SHIFT>;
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <AD9081_TX_CHAN_INTERPOLATION>;
trx2_ad9081_tx_fddc_chan0: channel@0 {
reg = <0>;
adi,gain = <AD9081_GAIN>; /* gain_dB = 20*log_10(value/2048) */
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_CHAN_NCO_SHIFT>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
trx2_ad9081_tx_jesd_l0: link@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
adi,tpl-phase-adjust = <AD9081_JRX_TPL_PHASE_ADJUST>;
adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
adi,link-mode = <AD9081_TX_JESD_MODE>; /* JESD Quick Configuration Mode */
adi,subclass = <AD9081_TX_JESD_SUBCLASS>; /* JESD SUBCLASS 0,1,2 */
adi,version = <AD9081_TX_JESD_VERSION>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,converters-per-device = <AD9081_TX_JESD_M>; /* JESD M */
adi,octets-per-frame = <AD9081_TX_JESD_F>; /* JESD F */
adi,frames-per-multiframe = <AD9081_TX_JESD_K>; /* JESD K */
adi,converter-resolution = <AD9081_TX_JESD_N>; /* JESD N */
adi,bits-per-sample = <AD9081_TX_JESD_N>; /* JESD NP' */
adi,control-bits-per-sample = <AD9081_TX_JESD_CS>; /* JESD CS */
adi,lanes-per-device = <AD9081_TX_JESD_L>; /* JESD L */
adi,samples-per-converter-per-frame = <AD9081_TX_JESD_S>; /* JESD S */
adi,high-density = <AD9081_TX_JESD_HD>; /* JESD HD */
};
};
};
adi,rx-adcs {
#size-cells = <0>;
#address-cells = <1>;
adi,adc-frequency-hz = /bits/ 64 <AD9081_ADC_FREQUENCY>;
adi,nyquist-zone = <AD9081_ADC_NYQUIST_ZONE>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
trx2_ad9081_adc2: adc@2 {
reg = <2>;
adi,decimation = <AD9081_RX_MAIN_DECIMATION>;
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_RX_MAIN_NCO_SHIFT>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
trx2_ad9081_rx_fddc_chan4: channel@4 {
reg = <4>;
adi,decimation = <AD9081_RX_CHAN_DECIMATION>;
adi,gain = <AD9081_GAIN>; /* gain_dB = 20*log_10(value/2048) */
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_RX_CHAN_NCO_SHIFT>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
trx2_ad9081_rx_jesd_l0: link@0 {
reg = <0>;
adi,converter-select =
<&trx2_ad9081_rx_fddc_chan4 FDDC_I>, <&trx2_ad9081_rx_fddc_chan4 FDDC_Q>;
adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
adi,link-mode = <AD9081_RX_JESD_MODE>; /* JESD Quick Configuration Mode */
adi,subclass = <AD9081_RX_JESD_SUBCLASS>; /* JESD SUBCLASS 0,1,2 */
adi,version = <AD9081_RX_JESD_VERSION>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,device-id = <3>;
adi,converters-per-device = <AD9081_RX_JESD_M>; /* JESD M */
adi,octets-per-frame = <AD9081_RX_JESD_F>; /* JESD F */
adi,frames-per-multiframe = <AD9081_RX_JESD_K>; /* JESD K */
adi,converter-resolution = <AD9081_RX_JESD_N>; /* JESD N */
adi,bits-per-sample = <AD9081_RX_JESD_NP>; /* JESD NP' */
adi,control-bits-per-sample = <AD9081_RX_JESD_CS>; /* JESD CS */
adi,lanes-per-device = <AD9081_RX_JESD_L>; /* JESD L */
adi,samples-per-converter-per-frame = <AD9081_RX_JESD_S>; /* JESD S */
adi,high-density = <AD9081_RX_JESD_HD>; /* JESD HD */
};
};
};
};
&trx3_ad9081 {
/delete-property/ adi,jesd-sync-pins-01-swap-enable;
adi,jesd-sync-pin-0a-cmos-enable;
adi,tx-dacs {
#size-cells = <0>;
#address-cells = <1>;
adi,dac-frequency-hz = /bits/ 64 <AD9081_DAC_FREQUENCY>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <AD9081_TX_MAIN_INTERPOLATION>;
trx3_ad9081_dac0: dac@0 {
reg = <0>;
adi,crossbar-select = <&trx3_ad9081_tx_fddc_chan0>;
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_MAIN_NCO_SHIFT>;
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <AD9081_TX_CHAN_INTERPOLATION>;
trx3_ad9081_tx_fddc_chan0: channel@0 {
reg = <0>;
adi,gain = <AD9081_GAIN>; /* gain_dB = 20*log_10(value/2048) */
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_CHAN_NCO_SHIFT>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
trx3_ad9081_tx_jesd_l0: link@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
adi,tpl-phase-adjust = <AD9081_JRX_TPL_PHASE_ADJUST>;
adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
adi,link-mode = <AD9081_TX_JESD_MODE>; /* JESD Quick Configuration Mode */
adi,subclass = <AD9081_TX_JESD_SUBCLASS>; /* JESD SUBCLASS 0,1,2 */
adi,version = <AD9081_TX_JESD_VERSION>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,converters-per-device = <AD9081_TX_JESD_M>; /* JESD M */
adi,octets-per-frame = <AD9081_TX_JESD_F>; /* JESD F */
adi,frames-per-multiframe = <AD9081_TX_JESD_K>; /* JESD K */
adi,converter-resolution = <AD9081_TX_JESD_N>; /* JESD N */
adi,bits-per-sample = <AD9081_TX_JESD_N>; /* JESD NP' */
adi,control-bits-per-sample = <AD9081_TX_JESD_CS>; /* JESD CS */
adi,lanes-per-device = <AD9081_TX_JESD_L>; /* JESD L */
adi,samples-per-converter-per-frame = <AD9081_TX_JESD_S>; /* JESD S */
adi,high-density = <AD9081_TX_JESD_HD>; /* JESD HD */
};
};
};
adi,rx-adcs {
#size-cells = <0>;
#address-cells = <1>;
adi,adc-frequency-hz = /bits/ 64 <AD9081_ADC_FREQUENCY>;
adi,nyquist-zone = <AD9081_ADC_NYQUIST_ZONE>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
trx3_ad9081_adc2: adc@2 {
reg = <2>;
adi,decimation = <AD9081_RX_MAIN_DECIMATION>;
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_RX_MAIN_NCO_SHIFT>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
trx3_ad9081_rx_fddc_chan4: channel@4 {
reg = <4>;
adi,decimation = <AD9081_RX_CHAN_DECIMATION>;
adi,gain = <AD9081_GAIN>; /* gain_dB = 20*log_10(value/2048) */
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_RX_CHAN_NCO_SHIFT>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
trx3_ad9081_rx_jesd_l0: link@0 {
reg = <0>;
adi,converter-select =
<&trx3_ad9081_rx_fddc_chan4 FDDC_I>, <&trx3_ad9081_rx_fddc_chan4 FDDC_Q>;
adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
adi,link-mode = <AD9081_RX_JESD_MODE>; /* JESD Quick Configuration Mode */
adi,subclass = <AD9081_RX_JESD_SUBCLASS>; /* JESD SUBCLASS 0,1,2 */
adi,version = <AD9081_RX_JESD_VERSION>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,device-id = <3>;
adi,converters-per-device = <AD9081_RX_JESD_M>; /* JESD M */
adi,octets-per-frame = <AD9081_RX_JESD_F>; /* JESD F */
adi,frames-per-multiframe = <AD9081_RX_JESD_K>; /* JESD K */
adi,converter-resolution = <AD9081_RX_JESD_N>; /* JESD N */
adi,bits-per-sample = <AD9081_RX_JESD_NP>; /* JESD NP' */
adi,control-bits-per-sample = <AD9081_RX_JESD_CS>; /* JESD CS */
adi,lanes-per-device = <AD9081_RX_JESD_L>; /* JESD L */
adi,samples-per-converter-per-frame = <AD9081_RX_JESD_S>; /* JESD S */
adi,high-density = <AD9081_RX_JESD_HD>; /* JESD HD */
};
};
};
};
However, when I actually run the design, I'm getting a tonne of unexpected noise / weird behaviour that I'm unable to explain - see MATLAB FFT output below:
Digging more deeply and playing about with the various test modes for the Rx, I'm seeing some very strange behaviour. When I run neg_fullscale and post_fullscale tests, I get a deterministic fall/rise to 0 of the signal (which may partly explain the above noise).
None of my other designs are showing this behaviour - they all work fine. Any idea what might be going on here, and what steps should I try to fix this?
Thanks,
Kari
