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AD9173 DAC TPL core input format


I removed DMA+FIFO and want to feed both DACs with IQ data from my own DSP core. With original DDS it looks good, but not with my DSP. Datawidth 256bit and rate 250MHz matches together.

What do I need to configure and how do I need to map the 256bits to my quadphase complex DDS with signed 4x16bit I and 4x16bit Q outputs. I already figured out, that i need to set DAC_DDS_SEL on register 0x418, 0x458, 0x498 and 0x4d8 to 0x2 for DMA input.