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AD-FMCDAQ2: Analog waveform received seems from DAC seems to be having dips and spikes

Hi team

I am using ADI-FMCDAQ2 module and loopback test for my design to test the interoperability of DAC and ADC with our FPGA device. The data path is like ADC--> FPGA (loopback)-->DAC. I am providing clean analog input (sinewave, ramp, sqaure wave  etc) at the input side (both port A and B or either of the them) of FMCDAQ2 and i received the below waveform from DAC when measured on oscilloscope. Sine wave doesn't look clean and there are spikes and dip.

Here is my configuration at the ADC and DAC side

ADC (AD9680) L=4, M=2, F=2 ,S=2, N'=16(reg 570=0x89), N=14(Converter resolution), subclass=0, reg 561=0

Lane Line Rate= M x N' x 1.25 x fout / L

where fout = fadc_clk/decimation ratio
fadc_clk=625 Mhz
decimation=1

so fout = 625 Mhz

Lane line rate = 6250 Mbps

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DAC (AD9144) L=4, M=2, F=2,S=2,N'=16 (Mode 5) N=16 (converter resolution), subclass=0, binary format

DataRate = (DACRate)/(InterpolationFactor)
LaneRate = (20 × DataRate × M)/L

InterpolationFactor=1
if DACRate=625 Mhz

LaneRate= 6250 Mbps (design not working, DAC side link is down)

If DACRate=312.5 Mhz

LaneRate= 3125 Mbps (design is working, DAC side link is up and i see the attached waveform) but ADC lane rate not equal to DAC lane rate. This is strange for me. What i am missing here?

JESD Rx config (on FPGA) = ADC (JESD tx) config  and JESD Tx (FPGA side) = DAC (JESD) config.

Any ideas or suggestions will be helpful. Looking forward to hear from the team.

-trs



Added some imp information
[edited by: Trs at 3:46 PM (GMT -5) on 11 Mar 2022]