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failed to create project using HDL workflow for "Frequency Hopping Example Design"

Hello,

I am using the ADRV9361-Z7035 with the FMC, Matlab R2018b, and Vivado 2018.2.

I am trying to use HDL workflow advisor to target "Frequency Hopping Example Design [Analog Devices Wiki]"

i can go through all steps successfully, but on step "4.1: Create Project" i am getting this error

" Failed Required file "E:\hdl\vendor\AnalogDevices\vivado\library" is not available.”

I tried to find a solution over ADI Engineer Zone but I couldn’t.  

   - Could anyone suggest how can I solve this issue?

   - Could i complete this example using Matlab R2018b, and Vivado 2018.2 since these are available for me now and i couldn't upgrade for newest versions ?

thanks a lot

regards

Parents
  • R2018b has not been verified with Transceiver Toolbox and is pretty far outside our support window. Please upgrade to the latest if you can.

    -Travis

  • Hello,

    first, thanks for quick reply.

    second, so this error mostly due to Matlab version. The latest combination that i could get until now according to MATLAB releases and the respective Xilinx Vivado versions is R2019a and vivado 2018.2 is it ok?  for "Frequency Hopping Example Design [Analog Devices Wiki]"

    last think which is not far from this issue, i tried to perform other HW/SW Co-Design example  (QPSK Transmit and Receive Using Analog Devices) but unfortunately I stuck in the same step 4.1 but get another  error  

    "ERROR: [BD 41-758] The following clock pins are not connected to a valid clock source:
    /axi_i2s_adi/s_axi_aclk"

    as per the attached log file

    i am still using R2018b, and Vivado 2018.2.

    Do you think this error also due to this combination ? 

    thanks,

    regards.

    workflow_task_CreateProject.log

  • Please look at the releases here that were tests with specific versions of MATLAB: https://github.com/analogdevicesinc/TransceiverToolbox/releases

    HW/SW Co-Design example  (QPSK Transmit and Receive Using Analog Devices) b

    This demo was written and maintained by MathWorks and does not use Transceiver Toolbox, so there is limited support we can offer on EZ. But to me it looks like you are modifying the HDL Workflow to include and LED driver which is usually not in the default design.

    -Travis

  • hello

    related to the main issue "

    failed to create project using HDL workflow for "Frequency Hopping Example Design"

    Now, I am using this configuration :

      - The same HW which is  ADRV9361-Z7035 with the FMC

      - SW are Vivado 2019.1, Matlab R2020b and transceiver Toolbox v20.2.1 (github.com)

    Unfortunately  I am still stuck at point 4.1 Create project .

    I got this error 

    ERROR: [BD 41-701] connect_bd_net requires at least two pins/ports, or one pin/port and a net
    ERROR: [BD 5-4] Error: running connect_bd_net.
    ERROR: [Common 17-39] 'connect_bd_net' failed due to earlier errors.
    
        while executing
    "connect_bd_net -net [get_bd_nets -of_objects [get_bd_pins axi_ad9361_adc_dma/s_axis_ready]] [get_bd_pins $HDLCODERIPINST/dma_rdy] [get_bd_pins axi_ad9..."
        (file "vivado_insert_ip.tcl" line 18)

     

    Failed Create Project.
    
    Task "Create Project" unsuccessful. See log for details.
    Generated logfile: hdl_prj\hdlsrc\frequency_hopping\workflow_task_CreateProject.log
    
    ****** Vivado v2019.1 (64-bit)
      **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
      **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
        ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
    
    source vivado_create_prj.tcl -notrace
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/ipcore'.
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2019.1/data/ip'.
    INFO: [IP_Flow 19-1839] IP Catalog is up to date.
    CRITICAL WARNING: vivado version mismatch; expected 2018.3, got 2019.1.
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/ipcore'.
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog.com_user_util_mux_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_ad_ip_jesd204_tpl_adc_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_ad_ip_jesd204_tpl_dac_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_axi_jesd204_common_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_axi_jesd204_rx_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_axi_jesd204_tx_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_common_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_tx_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_tx_static_config_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad5766_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad6676_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad7616_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9122_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9144_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9152_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9162_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9250_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9265_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9361_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9371_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9434_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9467_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9625_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9680_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9684_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9739a_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9963_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_adc_decimate_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_adc_trigger_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_adrv9009_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_clkgen_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_dac_interpolate_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_dmac_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_fan_control_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_fmcadc5_sync_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_generic_adc_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_gpreg_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_hdmi_rx_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_hdmi_tx_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_i2s_adi_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_intr_monitor_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_laser_driver_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_logic_analyzer_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_mc_controller_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_mc_current_monitor_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_mc_speed_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_pulse_gen_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_rd_wr_combiner_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_spdif_rx_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_spdif_tx_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_sysid_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_usb_fx3_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_cordic_demod_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_sysid_rom_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_adcfifo_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_axis_fifo_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_axis_resize_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_axis_upscale_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_bsplit_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_cdc_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_cic_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_dacfifo_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_dec256sinc24b_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_delay_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_extract_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_fir_dec_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_fir_int_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_gmii_to_rgmii_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_i2c_mixer_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_mfifo_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_pulse_gen_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_rfifo_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_sigma_delta_spi_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_tdd_sync_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_var_fifo_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_util_wfifo_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_xilinx.com_user_axi_adcfifo_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_xilinx.com_user_axi_adxcvr_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [Common 17-14] Message 'IP_Flow 19-1663' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_xilinx.com_user_axi_dacfifo_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_xilinx.com_user_axi_xcvrlb_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_xilinx.com_user_util_adxcvr_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    INFO: [IP_Flow 19-949] Unzipped 'E:/hdl_prj/vivado_ip_prj/library/analog_xilinx.com_user_util_clkdiv_1.0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd> 
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    create_bd_net sys_cpu_clk
    connect_bd_net -net /sys_cpu_clk /sys_ps7/FCLK_CLK0
    create_bd_net sys_200m_clk
    connect_bd_net -net /sys_200m_clk /sys_ps7/FCLK_CLK1
    create_bd_net sys_cpu_reset
    connect_bd_net -net /sys_cpu_reset /sys_rstgen/peripheral_reset
    create_bd_net sys_cpu_resetn
    connect_bd_net -net /sys_cpu_resetn /sys_rstgen/peripheral_aresetn
    connect_bd_net -net /sys_cpu_clk /sys_rstgen/slowest_sync_clk
    connect_bd_net /sys_rstgen/ext_reset_in /sys_ps7/FCLK_RESET0_N
    connect_bd_intf_net /ddr /sys_ps7/DDR
    connect_bd_net /gpio_i /sys_ps7/GPIO_I
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/GPIO_I is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0
    connect_bd_net /gpio_o /sys_ps7/GPIO_O
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/GPIO_O is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0
    connect_bd_net /gpio_t /sys_ps7/GPIO_T
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/GPIO_T is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0
    connect_bd_intf_net /fixed_io /sys_ps7/FIXED_IO
    connect_bd_intf_net /iic_main /axi_iic_main/IIC
    connect_bd_net /sys_logic_inv/Res /sys_ps7/USB0_VBUS_PWRFAULT
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/USB0_VBUS_PWRFAULT is being overridden by the user. This pin will not be connected as a part of interface connection USBIND_0
    connect_bd_net /sys_logic_inv/Op1 /otg_vbusoc
    connect_bd_net /spi0_csn_2_o /sys_ps7/SPI0_SS2_O
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS2_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    connect_bd_net /spi0_csn_1_o /sys_ps7/SPI0_SS1_O
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS1_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    connect_bd_net /spi0_csn_0_o /sys_ps7/SPI0_SS_O
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    connect_bd_net /spi0_csn_i /sys_ps7/SPI0_SS_I
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    connect_bd_net /spi0_clk_i /sys_ps7/SPI0_SCLK_I
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SCLK_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    connect_bd_net /spi0_clk_o /sys_ps7/SPI0_SCLK_O
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SCLK_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    connect_bd_net /spi0_sdo_i /sys_ps7/SPI0_MOSI_I
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_MOSI_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    connect_bd_net /spi0_sdo_o /sys_ps7/SPI0_MOSI_O
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_MOSI_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    connect_bd_net /spi0_sdi_i /sys_ps7/SPI0_MISO_I
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_MISO_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    connect_bd_net /spi1_csn_2_o /sys_ps7/SPI1_SS2_O
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS2_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    connect_bd_net /spi1_csn_1_o /sys_ps7/SPI1_SS1_O
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS1_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    connect_bd_net /spi1_csn_0_o /sys_ps7/SPI1_SS_O
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    connect_bd_net /spi1_csn_i /sys_ps7/SPI1_SS_I
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    connect_bd_net /spi1_clk_i /sys_ps7/SPI1_SCLK_I
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SCLK_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    connect_bd_net /spi1_clk_o /sys_ps7/SPI1_SCLK_O
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SCLK_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    connect_bd_net /spi1_sdo_i /sys_ps7/SPI1_MOSI_I
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_MOSI_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    connect_bd_net /spi1_sdo_o /sys_ps7/SPI1_MOSI_O
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_MOSI_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    connect_bd_net /spi1_sdi_i /sys_ps7/SPI1_MISO_I
    INFO: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_MISO_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    connect_bd_net /axi_sysid_0/rom_addr /rom_sys_0/rom_addr
    connect_bd_net /axi_sysid_0/sys_rom_data /rom_sys_0/rom_data
    connect_bd_net -net /sys_cpu_clk /rom_sys_0/clk
    connect_bd_net /sys_concat_intc/dout /sys_ps7/IRQ_F2P
    connect_bd_net GND_1/dout sys_concat_intc/In15
    connect_bd_net /sys_concat_intc/In14 /axi_iic_main/iic2intc_irpt
    connect_bd_net GND_1/dout sys_concat_intc/In13
    connect_bd_net GND_1/dout sys_concat_intc/In12
    connect_bd_net GND_1/dout sys_concat_intc/In11
    connect_bd_net GND_1/dout sys_concat_intc/In10
    connect_bd_net GND_1/dout sys_concat_intc/In9
    connect_bd_net GND_1/dout sys_concat_intc/In8
    connect_bd_net GND_1/dout sys_concat_intc/In7
    connect_bd_net GND_1/dout sys_concat_intc/In6
    connect_bd_net GND_1/dout sys_concat_intc/In5
    connect_bd_net GND_1/dout sys_concat_intc/In4
    connect_bd_net GND_1/dout sys_concat_intc/In3
    connect_bd_net GND_1/dout sys_concat_intc/In2
    connect_bd_net GND_1/dout sys_concat_intc/In1
    connect_bd_net GND_1/dout sys_concat_intc/In0
    connect_bd_net -net /sys_cpu_clk /sys_ps7/M_AXI_GP0_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/ACLK
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/S00_ACLK
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/S00_ARESETN
    connect_bd_intf_net /axi_cpu_interconnect/S00_AXI /sys_ps7/M_AXI_GP0
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M00_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_sysid_0/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M00_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_sysid_0/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M00_AXI /axi_sysid_0/s_axi
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M01_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_iic_main/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M01_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_iic_main/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M01_AXI /axi_iic_main/S_AXI
    connect_bd_net -net /sys_200m_clk /axi_ad9361/delay_clk
    connect_bd_net /axi_ad9361/l_clk /axi_ad9361/clk
    connect_bd_net /enable /axi_ad9361/enable
    connect_bd_net /txnrx /axi_ad9361/txnrx
    connect_bd_net /up_enable /axi_ad9361/up_enable
    connect_bd_net /up_txnrx /axi_ad9361/up_txnrx
    connect_bd_net -net /sys_cpu_clk /util_ad9361_tdd_sync/clk
    connect_bd_net -net /sys_cpu_resetn /util_ad9361_tdd_sync/rstn
    connect_bd_net /util_ad9361_tdd_sync/sync_out /axi_ad9361/tdd_sync
    connect_bd_net /util_ad9361_tdd_sync/sync_mode /axi_ad9361/tdd_sync_cntr
    connect_bd_net /tdd_sync_t /axi_ad9361/tdd_sync_cntr
    connect_bd_net /tdd_sync_o /util_ad9361_tdd_sync/sync_out
    connect_bd_net /tdd_sync_i /util_ad9361_tdd_sync/sync_in
    connect_bd_net /gps_pps /axi_ad9361/gps_pps
    WARNING: [BD 41-1753] The name 'util_ad9361_divclk_sel_concat' you have specified is long. The Windows OS has path length limitations. It is recommended you use shorter names(less than 25 characters) to reduce the likelihood of issues when/if running on windows OS.
    connect_bd_net /axi_ad9361/adc_r1_mode /util_ad9361_divclk_sel_concat/In0
    connect_bd_net /axi_ad9361/dac_r1_mode /util_ad9361_divclk_sel_concat/In1
    connect_bd_net /util_ad9361_divclk_sel_concat/dout /util_ad9361_divclk_sel/Op1
    connect_bd_net /util_ad9361_divclk_sel/Res /util_ad9361_divclk/clk_sel
    connect_bd_net /axi_ad9361/l_clk /util_ad9361_divclk/clk
    connect_bd_net /sys_rstgen/peripheral_aresetn /util_ad9361_divclk_reset/ext_reset_in
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_divclk_reset/slowest_sync_clk
    connect_bd_net /axi_ad9361/l_clk /util_ad9361_adc_fifo/din_clk
    connect_bd_net /axi_ad9361/rst /util_ad9361_adc_fifo/din_rst
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_adc_fifo/dout_clk
    connect_bd_net /util_ad9361_divclk_reset/peripheral_aresetn /util_ad9361_adc_fifo/dout_rstn
    connect_bd_net /axi_ad9361/adc_enable_i0 /util_ad9361_adc_fifo/din_enable_0
    connect_bd_net /axi_ad9361/adc_valid_i0 /util_ad9361_adc_fifo/din_valid_0
    connect_bd_net /axi_ad9361/adc_data_i0 /util_ad9361_adc_fifo/din_data_0
    connect_bd_net /axi_ad9361/adc_enable_q0 /util_ad9361_adc_fifo/din_enable_1
    connect_bd_net /axi_ad9361/adc_valid_q0 /util_ad9361_adc_fifo/din_valid_1
    connect_bd_net /axi_ad9361/adc_data_q0 /util_ad9361_adc_fifo/din_data_1
    connect_bd_net /axi_ad9361/adc_enable_i1 /util_ad9361_adc_fifo/din_enable_2
    connect_bd_net /axi_ad9361/adc_valid_i1 /util_ad9361_adc_fifo/din_valid_2
    connect_bd_net /axi_ad9361/adc_data_i1 /util_ad9361_adc_fifo/din_data_2
    connect_bd_net /axi_ad9361/adc_enable_q1 /util_ad9361_adc_fifo/din_enable_3
    connect_bd_net /axi_ad9361/adc_valid_q1 /util_ad9361_adc_fifo/din_valid_3
    connect_bd_net /axi_ad9361/adc_data_q1 /util_ad9361_adc_fifo/din_data_3
    connect_bd_net /util_ad9361_adc_fifo/din_ovf /axi_ad9361/adc_dovf
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_adc_pack/clk
    connect_bd_net /util_ad9361_divclk_reset/peripheral_reset /util_ad9361_adc_pack/reset
    connect_bd_net /util_ad9361_adc_fifo/dout_valid_0 /util_ad9361_adc_pack/fifo_wr_en
    connect_bd_net /util_ad9361_adc_pack/fifo_wr_overflow /util_ad9361_adc_fifo/dout_ovf
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_0 /util_ad9361_adc_pack/enable_0
    connect_bd_net /util_ad9361_adc_fifo/dout_data_0 /util_ad9361_adc_pack/fifo_wr_data_0
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_1 /util_ad9361_adc_pack/enable_1
    connect_bd_net /util_ad9361_adc_fifo/dout_data_1 /util_ad9361_adc_pack/fifo_wr_data_1
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_2 /util_ad9361_adc_pack/enable_2
    connect_bd_net /util_ad9361_adc_fifo/dout_data_2 /util_ad9361_adc_pack/fifo_wr_data_2
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_3 /util_ad9361_adc_pack/enable_3
    connect_bd_net /util_ad9361_adc_fifo/dout_data_3 /util_ad9361_adc_pack/fifo_wr_data_3
    connect_bd_net /util_ad9361_divclk/clk_out /axi_ad9361_adc_dma/fifo_wr_clk
    connect_bd_intf_net /util_ad9361_adc_pack/packed_fifo_wr /axi_ad9361_adc_dma/fifo_wr
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_adc_dma/m_dest_axi_aresetn
    connect_bd_net /axi_ad9361/l_clk /axi_ad9361_dac_fifo/dout_clk
    connect_bd_net /axi_ad9361/rst /axi_ad9361_dac_fifo/dout_rst
    connect_bd_net /util_ad9361_divclk/clk_out /axi_ad9361_dac_fifo/din_clk
    connect_bd_net /util_ad9361_divclk_reset/peripheral_aresetn /axi_ad9361_dac_fifo/din_rstn
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_0 /axi_ad9361/dac_enable_i0
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_0 /axi_ad9361/dac_valid_i0
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_0 /axi_ad9361/dac_data_i0
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_1 /axi_ad9361/dac_enable_q0
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_1 /axi_ad9361/dac_valid_q0
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_1 /axi_ad9361/dac_data_q0
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_2 /axi_ad9361/dac_enable_i1
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_2 /axi_ad9361/dac_valid_i1
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_2 /axi_ad9361/dac_data_i1
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_3 /axi_ad9361/dac_enable_q1
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_3 /axi_ad9361/dac_valid_q1
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_3 /axi_ad9361/dac_data_q1
    connect_bd_net /axi_ad9361_dac_fifo/dout_unf /axi_ad9361/dac_dunf
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_dac_upack/clk
    connect_bd_net /util_ad9361_divclk_reset/peripheral_reset /util_ad9361_dac_upack/reset
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_en /axi_ad9361_dac_fifo/din_valid_0
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_underflow /axi_ad9361_dac_fifo/din_unf
    connect_bd_net /util_ad9361_dac_upack/enable_0 /axi_ad9361_dac_fifo/din_enable_0
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_0
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_0 /axi_ad9361_dac_fifo/din_data_0
    connect_bd_net /util_ad9361_dac_upack/enable_1 /axi_ad9361_dac_fifo/din_enable_1
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_1
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_1 /axi_ad9361_dac_fifo/din_data_1
    connect_bd_net /util_ad9361_dac_upack/enable_2 /axi_ad9361_dac_fifo/din_enable_2
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_2
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_2 /axi_ad9361_dac_fifo/din_data_2
    connect_bd_net /util_ad9361_dac_upack/enable_3 /axi_ad9361_dac_fifo/din_enable_3
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_3
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_3 /axi_ad9361_dac_fifo/din_data_3
    connect_bd_net /util_ad9361_divclk/clk_out /axi_ad9361_dac_dma/m_axis_aclk
    connect_bd_intf_net /axi_ad9361_dac_dma/m_axis /util_ad9361_dac_upack/s_axis
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_dac_dma/m_src_axi_aresetn
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M02_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_ad9361/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M02_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M02_AXI /axi_ad9361/s_axi
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M03_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_adc_dma/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M03_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_adc_dma/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M03_AXI /axi_ad9361_adc_dma/s_axi
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M04_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_dac_dma/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M04_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_dac_dma/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M04_AXI /axi_ad9361_dac_dma/s_axi
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    connect_bd_net -net /sys_cpu_resetn /axi_hp1_interconnect/aresetn
    connect_bd_net -net /sys_cpu_clk /axi_hp1_interconnect/aclk
    connect_bd_intf_net /axi_hp1_interconnect/M00_AXI /sys_ps7/S_AXI_HP1
    connect_bd_net -net /sys_cpu_clk /sys_ps7/S_AXI_HP1_ACLK
    connect_bd_intf_net /axi_hp1_interconnect/S00_AXI /axi_ad9361_adc_dma/m_dest_axi
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_adc_dma/m_dest_axi_aclk
    Slave segment </sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM> is being mapped into address space </axi_ad9361_adc_dma/m_dest_axi> at <0x0000_0000 [ 1G ]>
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    connect_bd_net -net /sys_cpu_resetn /axi_hp2_interconnect/aresetn
    connect_bd_net -net /sys_cpu_clk /axi_hp2_interconnect/aclk
    connect_bd_intf_net /axi_hp2_interconnect/M00_AXI /sys_ps7/S_AXI_HP2
    connect_bd_net -net /sys_cpu_clk /sys_ps7/S_AXI_HP2_ACLK
    connect_bd_intf_net /axi_hp2_interconnect/S00_AXI /axi_ad9361_dac_dma/m_src_axi
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_dac_dma/m_src_axi_aclk
    Slave segment </sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM> is being mapped into address space </axi_ad9361_dac_dma/m_src_axi> at <0x0000_0000 [ 1G ]>
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In13
    connect_bd_net /sys_concat_intc/In13 /axi_ad9361_adc_dma/irq
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In12
    connect_bd_net /sys_concat_intc/In12 /axi_ad9361_dac_dma/irq
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In11
    connect_bd_net /sys_concat_intc/In11 /axi_ad9361/gps_pps_irq
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [BD 41-721] Attempt to set value '0' on disabled parameter 'SYNC_TRANSFER_START' of cell '/axi_hdmi_dma' is ignored
    connect_bd_net -net /sys_200m_clk /axi_hdmi_clkgen/clk
    connect_bd_intf_net /sys_ps7/MDIO_ETHERNET_1 /sys_rgmii/MDIO_GEM
    connect_bd_intf_net /sys_ps7/GMII_ETHERNET_1 /sys_rgmii/GMII
    connect_bd_intf_net /sys_rgmii/MDIO_PHY /eth1_mdio
    connect_bd_intf_net /sys_rgmii/RGMII /eth1_rgmii
    connect_bd_net /sys_ps7/ENET1_EXT_INTIN /eth1_intn
    connect_bd_net -net /sys_200m_clk /sys_rgmii_rstgen/slowest_sync_clk
    connect_bd_net -net /sys_200m_clk /sys_rgmii/clkin
    connect_bd_net /sys_rgmii_rstgen/ext_reset_in /sys_ps7/FCLK_RESET0_N
    connect_bd_net /sys_rgmii_rstgen/peripheral_reset /sys_rgmii/tx_reset
    connect_bd_net /sys_rgmii_rstgen/peripheral_reset /sys_rgmii/rx_reset
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_core/vdma_clk
    connect_bd_net /axi_hdmi_core/hdmi_clk /axi_hdmi_clkgen/clk_0
    connect_bd_net /axi_hdmi_core/hdmi_out_clk /hdmi_out_clk
    connect_bd_net /axi_hdmi_core/hdmi_16_hsync /hdmi_hsync
    connect_bd_net /axi_hdmi_core/hdmi_16_vsync /hdmi_vsync
    connect_bd_net /axi_hdmi_core/hdmi_16_data_e /hdmi_data_e
    connect_bd_net /axi_hdmi_core/hdmi_16_data /hdmi_data
    connect_bd_intf_net /axi_hdmi_dma/m_axis /axi_hdmi_core/s_axis
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_dma/s_axi_aresetn
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_dma/m_src_axi_aresetn
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_dma/s_axi_aclk
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_dma/m_src_axi_aclk
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_dma/m_axis_aclk
    connect_bd_net -net /sys_cpu_clk /axi_spdif_tx_core/dma_req_aclk
    connect_bd_net -net /sys_cpu_clk /sys_ps7/DMA0_ACLK
    connect_bd_net -net /sys_cpu_resetn /axi_spdif_tx_core/dma_req_rstn
    connect_bd_intf_net /sys_ps7/DMA0_REQ /axi_spdif_tx_core/dma_req
    connect_bd_intf_net /sys_ps7/DMA0_ACK /axi_spdif_tx_core/dma_ack
    connect_bd_net -net /sys_200m_clk /sys_audio_clkgen/clk_in1
    connect_bd_net -net /sys_cpu_resetn /sys_audio_clkgen/resetn
    connect_bd_net /sys_audio_clkgen/clk_out1 /axi_spdif_tx_core/spdif_data_clk
    connect_bd_net /spdif /axi_spdif_tx_core/spdif_tx_o
    connect_bd_net -net /sys_cpu_clk /axi_i2s_adi/dma_req_rx_aclk
    connect_bd_net -net /sys_cpu_clk /axi_i2s_adi/dma_req_tx_aclk
    connect_bd_net -net /sys_cpu_clk /sys_ps7/DMA1_ACLK
    connect_bd_net -net /sys_cpu_clk /sys_ps7/DMA2_ACLK
    connect_bd_net -net /sys_cpu_resetn /axi_i2s_adi/dma_req_rx_rstn
    connect_bd_net -net /sys_cpu_resetn /axi_i2s_adi/dma_req_tx_rstn
    connect_bd_intf_net /sys_ps7/DMA1_REQ /axi_i2s_adi/dma_req_tx
    connect_bd_intf_net /sys_ps7/DMA1_ACK /axi_i2s_adi/dma_ack_tx
    connect_bd_intf_net /sys_ps7/DMA2_REQ /axi_i2s_adi/dma_req_rx
    connect_bd_intf_net /sys_ps7/DMA2_ACK /axi_i2s_adi/dma_ack_rx
    connect_bd_net /sys_audio_clkgen/clk_out1 /i2s_mclk
    connect_bd_net /sys_audio_clkgen/clk_out1 /axi_i2s_adi/data_clk_i
    connect_bd_intf_net /i2s /axi_i2s_adi/i2s
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In15
    connect_bd_net /sys_concat_intc/In15 /axi_hdmi_dma/irq
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M05_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_clkgen/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M05_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_clkgen/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M05_AXI /axi_hdmi_clkgen/s_axi
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M06_ACLK
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M06_ARESETN
    connect_bd_intf_net /axi_cpu_interconnect/M06_AXI /axi_hdmi_dma/s_axi
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M07_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_core/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M07_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_core/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M07_AXI /axi_hdmi_core/s_axi
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M08_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_spdif_tx_core/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M08_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_spdif_tx_core/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M08_AXI /axi_spdif_tx_core/s_axi
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M09_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_i2s_adi/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M09_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_i2s_adi/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M09_AXI /axi_i2s_adi/s_axi
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    connect_bd_net -net /sys_cpu_resetn /axi_hp0_interconnect/aresetn
    connect_bd_net -net /sys_cpu_clk /axi_hp0_interconnect/aclk
    connect_bd_intf_net /axi_hp0_interconnect/M00_AXI /sys_ps7/S_AXI_HP0
    connect_bd_net -net /sys_cpu_clk /sys_ps7/S_AXI_HP0_ACLK
    connect_bd_intf_net /axi_hp0_interconnect/S00_AXI /axi_hdmi_dma/m_src_axi
    Slave segment </sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM> is being mapped into address space </axi_hdmi_dma/m_src_axi> at <0x0000_0000 [ 1G ]>
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M10_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_pz_xcvrlb/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M10_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_pz_xcvrlb/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M10_AXI /axi_pz_xcvrlb/s_axi
    connect_bd_net /axi_pz_xcvrlb/ref_clk /gt_ref_clk_0
    connect_bd_net /axi_pz_xcvrlb/rx_p /gt_rx_p
    connect_bd_net /axi_pz_xcvrlb/rx_n /gt_rx_n
    connect_bd_net /axi_pz_xcvrlb/tx_p /gt_tx_p
    connect_bd_net /axi_pz_xcvrlb/tx_n /gt_tx_n
    connect_bd_net /clk_0 /axi_gpreg/d_clk_0
    connect_bd_net /clk_1 /axi_gpreg/d_clk_1
    connect_bd_net /gt_ref_clk_1 /axi_gpreg/d_clk_2
    connect_bd_net /gp_in_0 /axi_gpreg/up_gp_in_0
    connect_bd_net /gp_in_1 /axi_gpreg/up_gp_in_1
    connect_bd_net /gp_out_0 /axi_gpreg/up_gp_out_0
    connect_bd_net /gp_out_1 /axi_gpreg/up_gp_out_1
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M11_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_gpreg/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M11_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_gpreg/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M11_AXI /axi_gpreg/s_axi
    WARNING: [BD 5-230] No cells matched 'get_bd_cells ila_adc'
    connect_bd_net /rx_clk_in_p /axi_ad9361/rx_clk_in_p
    connect_bd_net /rx_clk_in_n /axi_ad9361/rx_clk_in_n
    connect_bd_net /rx_frame_in_p /axi_ad9361/rx_frame_in_p
    connect_bd_net /rx_frame_in_n /axi_ad9361/rx_frame_in_n
    connect_bd_net /rx_data_in_p /axi_ad9361/rx_data_in_p
    connect_bd_net /rx_data_in_n /axi_ad9361/rx_data_in_n
    connect_bd_net /tx_clk_out_p /axi_ad9361/tx_clk_out_p
    connect_bd_net /tx_clk_out_n /axi_ad9361/tx_clk_out_n
    connect_bd_net /tx_frame_out_p /axi_ad9361/tx_frame_out_p
    connect_bd_net /tx_frame_out_n /axi_ad9361/tx_frame_out_n
    connect_bd_net /tx_data_out_p /axi_ad9361/tx_data_out_p
    connect_bd_net /tx_data_out_n /axi_ad9361/tx_data_out_n
    connect_bd_net -net /sys_cpu_clk /sys_cpu_clk_out
    WARNING: [BD 5-234] No nets matched 'get_bd_nets util_ad9361_dac_upack_dac_data_0'
    WARNING: [BD 5-234] No nets matched 'get_bd_nets util_ad9361_dac_upack_dac_data_1'
    WARNING: [BD 5-234] No nets matched 'get_bd_nets util_ad9361_dac_upack_dac_data_2'
    WARNING: [BD 5-234] No nets matched 'get_bd_nets util_ad9361_dac_upack_dac_data_3'
    WARNING: [BD 41-597] NET <Net> has no source
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd> 
    CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [#UNDEF] When using EMIO pins for SPI_0 tie SSIN High in the PL bitstream
    WARNING: [#UNDEF] When using EMIO pins for SPI_1 tie SSIN High in the PL bitstream
    WARNING: [BD 41-927] Following properties on pin /axi_sysid_0/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /rom_sys_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/delay_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK1 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/l_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_tdd_sync/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk_out have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	POLARITY=ACTIVE_HIGH 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_pack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	POLARITY=ACTIVE_HIGH 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_dac_upack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_hdmi_clkgen_0_clk_0 
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_out_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_hdmi_core_0_hdmi_out_clk 
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/vdma_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/spdif_data_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1 
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/dma_req_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/data_clk_i have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1 
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_tx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_rx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_pz_xcvrlb/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_gpreg/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
    Please check your design and connect them as needed: 
    /axi_ad9361_dac_fifo/din_valid_in_0
    /axi_ad9361_dac_fifo/din_valid_in_1
    /axi_ad9361_dac_fifo/din_valid_in_2
    /axi_ad9361_dac_fifo/din_valid_in_3
    
    validate_bd_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 834.129 ; gain = 122.051
    INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run.
    CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
    Please check your design and connect them as needed: 
    /axi_ad9361_dac_fifo/din_valid_in_0
    /axi_ad9361_dac_fifo/din_valid_in_1
    /axi_ad9361_dac_fifo/din_valid_in_2
    /axi_ad9361_dac_fifo/din_valid_in_3
    
    WARNING: [BD 41-597] NET <Net> has no source
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd> 
    CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/rom_sys_0/rom_addr'(6) to net 'axi_sysid_0_rom_addr'(9) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
    WARNING: [BD 41-166] Source port for the net:Net is NULL! Connection will be grounded!
    VHDL Output written to : E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/synth/system.v
    CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/rom_sys_0/rom_addr'(6) to net 'axi_sysid_0_rom_addr'(9) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
    WARNING: [BD 41-166] Source port for the net:Net is NULL! Connection will be grounded!
    VHDL Output written to : E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/sim/system.v
    VHDL Output written to : E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/hdl/system_wrapper.v
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_ps7 .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_iic_main .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_concat_intc .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_rstgen .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_logic_inv .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_sysid_0 .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block rom_sys_0 .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block GND_1 .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/xbar .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361 .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_tdd_sync .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk_sel_concat .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk_sel .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk_reset .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_adc_fifo .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_adc_pack .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361_adc_dma .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361_dac_fifo .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_dac_upack .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361_dac_dma .
    Exporting to file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/hw_handoff/system_axi_hp1_interconnect_0.hwh
    Generated Block Design Tcl file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/hw_handoff/system_axi_hp1_interconnect_0_bd.tcl
    Generated Hardware Definition File e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/synth/system_axi_hp1_interconnect_0.hwdef
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hp1_interconnect .
    Exporting to file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/hw_handoff/system_axi_hp2_interconnect_0.hwh
    Generated Block Design Tcl file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/hw_handoff/system_axi_hp2_interconnect_0_bd.tcl
    Generated Hardware Definition File e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/synth/system_axi_hp2_interconnect_0.hwdef
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hp2_interconnect .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_rgmii .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_rgmii_rstgen .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hdmi_clkgen .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hdmi_core .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hdmi_dma .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_audio_clkgen .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_spdif_tx_core .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_i2s_adi .
    Exporting to file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/hw_handoff/system_axi_hp0_interconnect_0.hwh
    Generated Block Design Tcl file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/hw_handoff/system_axi_hp0_interconnect_0_bd.tcl
    Generated Hardware Definition File e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/synth/system_axi_hp0_interconnect_0.hwdef
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hp0_interconnect .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_pz_xcvrlb .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpreg .
    WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_pc_12/system_auto_pc_12_ooc.xdc'
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/s00_couplers/auto_pc .
    WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_pc_0/system_auto_pc_0_ooc.xdc'
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/m00_couplers/auto_pc .
    WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_pc_1/system_auto_pc_1_ooc.xdc'
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/m01_couplers/auto_pc .
    WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_pc_2/system_auto_pc_2_ooc.xdc'
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/m02_couplers/auto_pc .
    WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_pc_3/system_auto_pc_3_ooc.xdc'
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/m03_couplers/auto_pc .
    WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_pc_4/system_auto_pc_4_ooc.xdc'
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/m04_couplers/auto_pc .
    WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_pc_5/system_auto_pc_5_ooc.xdc'
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/m05_couplers/auto_pc .
    WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_pc_6/system_auto_pc_6_ooc.xdc'
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/m06_couplers/auto_pc .
    WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_pc_7/system_auto_pc_7_ooc.xdc'
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/m07_couplers/auto_pc .
    WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_pc_8/system_auto_pc_8_ooc.xdc'
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/m08_couplers/auto_pc .
    WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_pc_9/system_auto_pc_9_ooc.xdc'
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/m09_couplers/auto_pc .
    WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_pc_10/system_auto_pc_10_ooc.xdc'
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/m10_couplers/auto_pc .
    WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_pc_11/system_auto_pc_11_ooc.xdc'
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/m11_couplers/auto_pc .
    Exporting to file E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/hw_handoff/system.hwh
    Generated Block Design Tcl file E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl
    Generated Hardware Definition File E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/synth/system.hwdef
    generate_target: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1162.465 ; gain = 328.336
    INFO: [Common 17-206] Exiting Vivado at Wed Mar 16 21:52:17 2022...
    
    Elapsed time is 77.4279 seconds.
    
    ****** Vivado v2019.1 (64-bit)
      **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
      **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
        ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
    
    source vivado_insert_ip.tcl -notrace
    Scanning sources...
    Finished scanning sources
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/ipcore'.
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'.
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2019.1/data/ip'.
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    open_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 346.988 ; gain = 42.363
    INFO: [IP_Flow 19-949] Unzipped './ipcore/HDL_DUT_ip_v1_0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/ipcore'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/ipcore'
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:jesd204_rx_static_config:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_interfaces_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_jesd.com_user_jesd204_rx_static_config_1.0
    WARNING: [IP_Flow 19-1663] Duplicate IP found for 'analog.com:user:axi_ad9671:1.0'. The one found in IP location 'e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_axi_ad9671_1.0' will take precedence over the same IP in location e:/hdl_prj/vivado_ip_prj/library/analog_lib.com_user_interfaces_1.0
    INFO: [IP_Flow 19-1839] IP Catalog is up to date.
    Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - sys_ps7
    Adding component instance block -- xilinx.com:ip:axi_iic:2.0 - axi_iic_main
    Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - sys_concat_intc
    Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - sys_rstgen
    Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - sys_logic_inv
    Adding component instance block -- analog.com:user:axi_sysid:1.0 - axi_sysid_0
    Adding component instance block -- analog.com:user:sysid_rom:1.0 - rom_sys_0
    Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - GND_1
    Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_cpu_interconnect
    Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
    Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
    Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
    Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
    Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
    Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
    Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
    Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
    Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
    Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
    Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
    Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
    Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
    Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
    Adding component instance block -- analog.com:user:axi_ad9361:1.0 - axi_ad9361
    Adding component instance block -- analog.com:user:util_tdd_sync:1.0 - util_ad9361_tdd_sync
    Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - util_ad9361_divclk_sel_concat
    Adding component instance block -- xilinx.com:ip:util_reduced_logic:2.0 - util_ad9361_divclk_sel
    Adding component instance block -- analog.com:user:util_clkdiv:1.0 - util_ad9361_divclk
    Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - util_ad9361_divclk_reset
    Adding component instance block -- analog.com:user:util_wfifo:1.0 - util_ad9361_adc_fifo
    Adding component instance block -- analog.com:user:util_cpack2:1.0 - util_ad9361_adc_pack
    Adding component instance block -- analog.com:user:axi_dmac:1.0 - axi_ad9361_adc_dma
    Adding component instance block -- analog.com:user:util_rfifo:1.0 - axi_ad9361_dac_fifo
    Adding component instance block -- analog.com:user:util_upack2:1.0 - util_ad9361_dac_upack
    Adding component instance block -- analog.com:user:axi_dmac:1.0 - axi_ad9361_dac_dma
    Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_hp1_interconnect
    Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_hp2_interconnect
    Adding component instance block -- xilinx.com:ip:gmii_to_rgmii:4.0 - sys_rgmii
    Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - sys_rgmii_rstgen
    Adding component instance block -- analog.com:user:axi_clkgen:1.0 - axi_hdmi_clkgen
    Adding component instance block -- analog.com:user:axi_hdmi_tx:1.0 - axi_hdmi_core
    Adding component instance block -- analog.com:user:axi_dmac:1.0 - axi_hdmi_dma
    Adding component instance block -- xilinx.com:ip:clk_wiz:6.0 - sys_audio_clkgen
    Adding component instance block -- analog.com:user:axi_spdif_tx:1.0 - axi_spdif_tx_core
    Adding component instance block -- analog.com:user:axi_i2s_adi:1.0 - axi_i2s_adi
    Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_hp0_interconnect
    Adding component instance block -- analog.com:user:axi_xcvrlb:1.0 - axi_pz_xcvrlb
    Adding component instance block -- analog.com:user:axi_gpreg:1.0 - axi_gpreg
    Successfully read diagram <system> from BD file <E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/system.bd>
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /gpio_status'
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /gpio_ctl'
    WARNING: [BD 5-235] No pins matched 'get_bd_pins axi_ad9361_adc_dma/s_axis_ready'
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects {}'
    WARNING: [BD 5-235] No pins matched 'get_bd_pins axi_ad9361_adc_dma/s_axis_ready'
    ERROR: [BD 41-701] connect_bd_net requires at least two pins/ports, or one pin/port and a net
    ERROR: [BD 5-4] Error: running connect_bd_net.
    ERROR: [Common 17-39] 'connect_bd_net' failed due to earlier errors.
    
        while executing
    "connect_bd_net -net [get_bd_nets -of_objects [get_bd_pins axi_ad9361_adc_dma/s_axis_ready]] [get_bd_pins $HDLCODERIPINST/dma_rdy] [get_bd_pins axi_ad9..."
        (file "vivado_insert_ip.tcl" line 18)
    INFO: [Common 17-206] Exiting Vivado at Wed Mar 16 21:52:28 2022...
    
    Elapsed time is 10.0101 seconds.

    i tried with another combination of SW (Vivado 2019.2, R2020b ) but i got the same error. 

     I tried a lot to resolve this error but what i could find is attributable to using different  Vivado versions, but i think i am using the right SW as recommended in toolbox documents.

    Really I need help to go through  or workaround this issue, second issue pls. explain thoroughly  since this is my first project with this stuff

    thank you

    Regards

  • Only 2018.3 was supported for the v20.2.1 release and other versions of Vivado will likely not work. As you can see from the log:

    CRITICAL WARNING: vivado version mismatch; expected 2018.3, got 2019.1.

    Supported Vivado versions are listed on the release notes. See for v20.2.1 https://github.com/analogdevicesinc/TransceiverToolbox/releases/tag/v20.2.1


    -Travis

  • Hello

    I am using  Vivado 2019.1Matlab R2021b and transceiver Toolbox V21.2.1

    which is Supported Tool Versions:

    • MATLAB R2021b
    • Xilinx Vivado 2019.1

    but ERROR in step 4.1 still stand

    i got these errors

    ERROR: [BD 41-701] connect_bd_net requires at least two pins/ports, or one pin/port and a net
    ERROR: [BD 5-4] Error: running connect_bd_net.
    ERROR: [Common 17-39] 'connect_bd_net' failed due to earlier errors.
    
        while executing
    "connect_bd_net -net [get_bd_nets -of_objects [get_bd_pins axi_ad9361_adc_dma/s_axis_ready]] [get_bd_pins $HDLCODERIPINST/dma_rdy] [get_bd_pins axi_ad9..."
        (file "vivado_insert_ip.tcl" line 24)
    Failed Create Project.
    
    Task "Create Project" unsuccessful. See log for details.
    Generated logfile: hdl_prj\hdlsrc\frequency_hopping\workflow_task_CreateProject.log
    
    ****** Vivado v2019.1 (64-bit)
      **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
      **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
        ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
    
    source vivado_create_prj.tcl -notrace
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/ipcore'.
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2019.1/data/ip'.
    INFO: [IP_Flow 19-1839] IP Catalog is up to date.
    Starting Transceiver Toolbox HDL build
    Building:
    - axi_ad9361
    - axi_clkgen
    - axi_dmac
    - axi_gpreg
    - axi_hdmi_tx
    - axi_i2s_adi
    - axi_spdif_tx
    - axi_sysid
    - sysid_rom
    - util_pack/util_cpack2
    - util_pack/util_upack2
    - util_rfifo
    - util_tdd_sync
    - util_wfifo
    - xilinx/axi_xcvrlb
    - xilinx/util_clkdiv
    Please wait, this might take a few minutes
    - Done building axi_ad9361
    - Done building axi_clkgen
    - Done building util_cdc
    - Done building util_axis_fifo
    - Done building axi_dmac
    - Done building axi_gpreg
    - Done building axi_hdmi_tx
    - Done building axi_i2s_adi
    - Done building axi_spdif_tx
    - Done building axi_sysid
    - Done building sysid_rom
    - Done building util_pack/util_cpack2
    - Done building util_pack/util_upack2
    - Done building util_rfifo
    - Done building util_tdd_sync
    - Done building util_wfifo
    - Done building xilinx/axi_xcvrlb
    - Done building xilinx/util_clkdiv
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/ipcore'.
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'.
    WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/hdl_prj/ghdl/library'; Can't find the specified path.
    If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd> 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    create_bd_net sys_cpu_clk
    connect_bd_net -net /sys_cpu_clk /sys_ps7/FCLK_CLK0
    create_bd_net sys_200m_clk
    connect_bd_net -net /sys_200m_clk /sys_ps7/FCLK_CLK1
    create_bd_net sys_cpu_reset
    connect_bd_net -net /sys_cpu_reset /sys_rstgen/peripheral_reset
    create_bd_net sys_cpu_resetn
    connect_bd_net -net /sys_cpu_resetn /sys_rstgen/peripheral_aresetn
    connect_bd_net -net /sys_cpu_clk /sys_rstgen/slowest_sync_clk
    connect_bd_net /sys_rstgen/ext_reset_in /sys_ps7/FCLK_RESET0_N
    connect_bd_intf_net /ddr /sys_ps7/DDR
    connect_bd_net /gpio_i /sys_ps7/GPIO_I
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/GPIO_I is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0
    connect_bd_net /gpio_o /sys_ps7/GPIO_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/GPIO_O is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0
    connect_bd_net /gpio_t /sys_ps7/GPIO_T
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/GPIO_T is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0
    connect_bd_intf_net /fixed_io /sys_ps7/FIXED_IO
    connect_bd_intf_net /iic_main /axi_iic_main/IIC
    connect_bd_net /sys_logic_inv/Res /sys_ps7/USB0_VBUS_PWRFAULT
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/USB0_VBUS_PWRFAULT is being overridden by the user. This pin will not be connected as a part of interface connection USBIND_0
    connect_bd_net /sys_logic_inv/Op1 /otg_vbusoc
    connect_bd_net /spi0_csn_2_o /sys_ps7/SPI0_SS2_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS2_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    connect_bd_net /spi0_csn_1_o /sys_ps7/SPI0_SS1_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS1_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    connect_bd_net /spi0_csn_0_o /sys_ps7/SPI0_SS_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    connect_bd_net /spi0_csn_i /sys_ps7/SPI0_SS_I
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    connect_bd_net /spi0_clk_i /sys_ps7/SPI0_SCLK_I
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SCLK_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    connect_bd_net /spi0_clk_o /sys_ps7/SPI0_SCLK_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SCLK_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    connect_bd_net /spi0_sdo_i /sys_ps7/SPI0_MOSI_I
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_MOSI_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    connect_bd_net /spi0_sdo_o /sys_ps7/SPI0_MOSI_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_MOSI_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    connect_bd_net /spi0_sdi_i /sys_ps7/SPI0_MISO_I
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_MISO_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    connect_bd_net /spi1_csn_2_o /sys_ps7/SPI1_SS2_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS2_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    connect_bd_net /spi1_csn_1_o /sys_ps7/SPI1_SS1_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS1_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    connect_bd_net /spi1_csn_0_o /sys_ps7/SPI1_SS_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    connect_bd_net /spi1_csn_i /sys_ps7/SPI1_SS_I
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    connect_bd_net /spi1_clk_i /sys_ps7/SPI1_SCLK_I
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SCLK_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    connect_bd_net /spi1_clk_o /sys_ps7/SPI1_SCLK_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SCLK_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    connect_bd_net /spi1_sdo_i /sys_ps7/SPI1_MOSI_I
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_MOSI_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    connect_bd_net /spi1_sdo_o /sys_ps7/SPI1_MOSI_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_MOSI_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    connect_bd_net /spi1_sdi_i /sys_ps7/SPI1_MISO_I
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_MISO_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    connect_bd_net /axi_sysid_0/rom_addr /rom_sys_0/rom_addr
    connect_bd_net /axi_sysid_0/sys_rom_data /rom_sys_0/rom_data
    connect_bd_net -net /sys_cpu_clk /rom_sys_0/clk
    connect_bd_net /sys_concat_intc/dout /sys_ps7/IRQ_F2P
    connect_bd_net GND_1/dout sys_concat_intc/In15
    connect_bd_net /sys_concat_intc/In14 /axi_iic_main/iic2intc_irpt
    connect_bd_net GND_1/dout sys_concat_intc/In13
    connect_bd_net GND_1/dout sys_concat_intc/In12
    connect_bd_net GND_1/dout sys_concat_intc/In11
    connect_bd_net GND_1/dout sys_concat_intc/In10
    connect_bd_net GND_1/dout sys_concat_intc/In9
    connect_bd_net GND_1/dout sys_concat_intc/In8
    connect_bd_net GND_1/dout sys_concat_intc/In7
    connect_bd_net GND_1/dout sys_concat_intc/In6
    connect_bd_net GND_1/dout sys_concat_intc/In5
    connect_bd_net GND_1/dout sys_concat_intc/In4
    connect_bd_net GND_1/dout sys_concat_intc/In3
    connect_bd_net GND_1/dout sys_concat_intc/In2
    connect_bd_net GND_1/dout sys_concat_intc/In1
    connect_bd_net GND_1/dout sys_concat_intc/In0
    connect_bd_net -net /sys_cpu_clk /sys_ps7/M_AXI_GP0_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/ACLK
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/S00_ACLK
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/S00_ARESETN
    connect_bd_intf_net /axi_cpu_interconnect/S00_AXI /sys_ps7/M_AXI_GP0
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M00_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_sysid_0/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M00_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_sysid_0/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M00_AXI /axi_sysid_0/s_axi
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M01_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_iic_main/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M01_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_iic_main/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M01_AXI /axi_iic_main/S_AXI
    connect_bd_net -net /sys_200m_clk /axi_ad9361/delay_clk
    connect_bd_net /axi_ad9361/l_clk /axi_ad9361/clk
    connect_bd_net /enable /axi_ad9361/enable
    connect_bd_net /txnrx /axi_ad9361/txnrx
    connect_bd_net /up_enable /axi_ad9361/up_enable
    connect_bd_net /up_txnrx /axi_ad9361/up_txnrx
    connect_bd_net -net /sys_cpu_clk /util_ad9361_tdd_sync/clk
    connect_bd_net -net /sys_cpu_resetn /util_ad9361_tdd_sync/rstn
    connect_bd_net /util_ad9361_tdd_sync/sync_out /axi_ad9361/tdd_sync
    connect_bd_net /util_ad9361_tdd_sync/sync_mode /axi_ad9361/tdd_sync_cntr
    connect_bd_net /tdd_sync_t /axi_ad9361/tdd_sync_cntr
    connect_bd_net /tdd_sync_o /util_ad9361_tdd_sync/sync_out
    connect_bd_net /tdd_sync_i /util_ad9361_tdd_sync/sync_in
    connect_bd_net /gps_pps /axi_ad9361/gps_pps
    WARNING: [BD 41-1753] The name 'util_ad9361_divclk_sel_concat' you have specified is long. The Windows OS has path length limitations. It is recommended you use shorter names(less than 25 characters) to reduce the likelihood of issues when/if running on windows OS.
    connect_bd_net /axi_ad9361/adc_r1_mode /util_ad9361_divclk_sel_concat/In0
    connect_bd_net /axi_ad9361/dac_r1_mode /util_ad9361_divclk_sel_concat/In1
    connect_bd_net /util_ad9361_divclk_sel_concat/dout /util_ad9361_divclk_sel/Op1
    connect_bd_net /util_ad9361_divclk_sel/Res /util_ad9361_divclk/clk_sel
    connect_bd_net /axi_ad9361/l_clk /util_ad9361_divclk/clk
    connect_bd_net /sys_rstgen/peripheral_aresetn /util_ad9361_divclk_reset/ext_reset_in
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_divclk_reset/slowest_sync_clk
    connect_bd_net /axi_ad9361/l_clk /util_ad9361_adc_fifo/din_clk
    connect_bd_net /axi_ad9361/rst /util_ad9361_adc_fifo/din_rst
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_adc_fifo/dout_clk
    connect_bd_net /util_ad9361_divclk_reset/peripheral_aresetn /util_ad9361_adc_fifo/dout_rstn
    connect_bd_net /axi_ad9361/adc_enable_i0 /util_ad9361_adc_fifo/din_enable_0
    connect_bd_net /axi_ad9361/adc_valid_i0 /util_ad9361_adc_fifo/din_valid_0
    connect_bd_net /axi_ad9361/adc_data_i0 /util_ad9361_adc_fifo/din_data_0
    connect_bd_net /axi_ad9361/adc_enable_q0 /util_ad9361_adc_fifo/din_enable_1
    connect_bd_net /axi_ad9361/adc_valid_q0 /util_ad9361_adc_fifo/din_valid_1
    connect_bd_net /axi_ad9361/adc_data_q0 /util_ad9361_adc_fifo/din_data_1
    connect_bd_net /axi_ad9361/adc_enable_i1 /util_ad9361_adc_fifo/din_enable_2
    connect_bd_net /axi_ad9361/adc_valid_i1 /util_ad9361_adc_fifo/din_valid_2
    connect_bd_net /axi_ad9361/adc_data_i1 /util_ad9361_adc_fifo/din_data_2
    connect_bd_net /axi_ad9361/adc_enable_q1 /util_ad9361_adc_fifo/din_enable_3
    connect_bd_net /axi_ad9361/adc_valid_q1 /util_ad9361_adc_fifo/din_valid_3
    connect_bd_net /axi_ad9361/adc_data_q1 /util_ad9361_adc_fifo/din_data_3
    connect_bd_net /util_ad9361_adc_fifo/din_ovf /axi_ad9361/adc_dovf
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_adc_pack/clk
    connect_bd_net /util_ad9361_divclk_reset/peripheral_reset /util_ad9361_adc_pack/reset
    connect_bd_net /util_ad9361_adc_fifo/dout_valid_0 /util_ad9361_adc_pack/fifo_wr_en
    connect_bd_net /util_ad9361_adc_pack/fifo_wr_overflow /util_ad9361_adc_fifo/dout_ovf
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_0 /util_ad9361_adc_pack/enable_0
    connect_bd_net /util_ad9361_adc_fifo/dout_data_0 /util_ad9361_adc_pack/fifo_wr_data_0
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_1 /util_ad9361_adc_pack/enable_1
    connect_bd_net /util_ad9361_adc_fifo/dout_data_1 /util_ad9361_adc_pack/fifo_wr_data_1
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_2 /util_ad9361_adc_pack/enable_2
    connect_bd_net /util_ad9361_adc_fifo/dout_data_2 /util_ad9361_adc_pack/fifo_wr_data_2
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_3 /util_ad9361_adc_pack/enable_3
    connect_bd_net /util_ad9361_adc_fifo/dout_data_3 /util_ad9361_adc_pack/fifo_wr_data_3
    connect_bd_net /util_ad9361_divclk/clk_out /axi_ad9361_adc_dma/fifo_wr_clk
    connect_bd_intf_net /util_ad9361_adc_pack/packed_fifo_wr /axi_ad9361_adc_dma/fifo_wr
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_adc_dma/m_dest_axi_aresetn
    connect_bd_net /axi_ad9361/l_clk /axi_ad9361_dac_fifo/dout_clk
    connect_bd_net /axi_ad9361/rst /axi_ad9361_dac_fifo/dout_rst
    connect_bd_net /util_ad9361_divclk/clk_out /axi_ad9361_dac_fifo/din_clk
    connect_bd_net /util_ad9361_divclk_reset/peripheral_aresetn /axi_ad9361_dac_fifo/din_rstn
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_0 /axi_ad9361/dac_enable_i0
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_0 /axi_ad9361/dac_valid_i0
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_0 /axi_ad9361/dac_data_i0
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_1 /axi_ad9361/dac_enable_q0
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_1 /axi_ad9361/dac_valid_q0
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_1 /axi_ad9361/dac_data_q0
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_2 /axi_ad9361/dac_enable_i1
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_2 /axi_ad9361/dac_valid_i1
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_2 /axi_ad9361/dac_data_i1
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_3 /axi_ad9361/dac_enable_q1
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_3 /axi_ad9361/dac_valid_q1
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_3 /axi_ad9361/dac_data_q1
    connect_bd_net /axi_ad9361_dac_fifo/dout_unf /axi_ad9361/dac_dunf
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_dac_upack/clk
    connect_bd_net /util_ad9361_divclk_reset/peripheral_reset /util_ad9361_dac_upack/reset
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_en /axi_ad9361_dac_fifo/din_valid_0
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_underflow /axi_ad9361_dac_fifo/din_unf
    connect_bd_net /util_ad9361_dac_upack/enable_0 /axi_ad9361_dac_fifo/din_enable_0
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_0
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_0 /axi_ad9361_dac_fifo/din_data_0
    connect_bd_net /util_ad9361_dac_upack/enable_1 /axi_ad9361_dac_fifo/din_enable_1
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_1
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_1 /axi_ad9361_dac_fifo/din_data_1
    connect_bd_net /util_ad9361_dac_upack/enable_2 /axi_ad9361_dac_fifo/din_enable_2
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_2
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_2 /axi_ad9361_dac_fifo/din_data_2
    connect_bd_net /util_ad9361_dac_upack/enable_3 /axi_ad9361_dac_fifo/din_enable_3
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_3
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_3 /axi_ad9361_dac_fifo/din_data_3
    connect_bd_net /util_ad9361_divclk/clk_out /axi_ad9361_dac_dma/m_axis_aclk
    connect_bd_intf_net /axi_ad9361_dac_dma/m_axis /util_ad9361_dac_upack/s_axis
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_dac_dma/m_src_axi_aresetn
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M02_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_ad9361/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M02_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M02_AXI /axi_ad9361/s_axi
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M03_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_adc_dma/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M03_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_adc_dma/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M03_AXI /axi_ad9361_adc_dma/s_axi
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M04_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_dac_dma/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M04_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_dac_dma/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M04_AXI /axi_ad9361_dac_dma/s_axi
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    connect_bd_net -net /sys_cpu_resetn /axi_hp1_interconnect/aresetn
    connect_bd_net -net /sys_cpu_clk /axi_hp1_interconnect/aclk
    connect_bd_intf_net /axi_hp1_interconnect/M00_AXI /sys_ps7/S_AXI_HP1
    connect_bd_net -net /sys_cpu_clk /sys_ps7/S_AXI_HP1_ACLK
    connect_bd_intf_net /axi_hp1_interconnect/S00_AXI /axi_ad9361_adc_dma/m_dest_axi
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_adc_dma/m_dest_axi_aclk
    WARNING: [BD 5-230] No cells matched 'get_bd_cells /sys_mb'
    WARNING: [BD 5-232] No interface pins matched 'get_bd_intf_pins -filter {NAME=~ *DLMB*} -of {}'
    Slave segment </sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM> is being mapped into address space </axi_ad9361_adc_dma/m_dest_axi> at <0x0000_0000 [ 1G ]>
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    connect_bd_net -net /sys_cpu_resetn /axi_hp2_interconnect/aresetn
    connect_bd_net -net /sys_cpu_clk /axi_hp2_interconnect/aclk
    connect_bd_intf_net /axi_hp2_interconnect/M00_AXI /sys_ps7/S_AXI_HP2
    connect_bd_net -net /sys_cpu_clk /sys_ps7/S_AXI_HP2_ACLK
    connect_bd_intf_net /axi_hp2_interconnect/S00_AXI /axi_ad9361_dac_dma/m_src_axi
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_dac_dma/m_src_axi_aclk
    WARNING: [BD 5-230] No cells matched 'get_bd_cells /sys_mb'
    WARNING: [BD 5-232] No interface pins matched 'get_bd_intf_pins -filter {NAME=~ *DLMB*} -of {}'
    Slave segment </sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM> is being mapped into address space </axi_ad9361_dac_dma/m_src_axi> at <0x0000_0000 [ 1G ]>
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In13
    connect_bd_net /sys_concat_intc/In13 /axi_ad9361_adc_dma/irq
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In12
    connect_bd_net /sys_concat_intc/In12 /axi_ad9361_dac_dma/irq
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In11
    connect_bd_net /sys_concat_intc/In11 /axi_ad9361/gps_pps_irq
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [BD 41-721] Attempt to set value '0' on disabled parameter 'SYNC_TRANSFER_START' of cell '/axi_hdmi_dma' is ignored
    connect_bd_net -net /sys_200m_clk /axi_hdmi_clkgen/clk
    connect_bd_intf_net /sys_ps7/MDIO_ETHERNET_1 /sys_rgmii/MDIO_GEM
    connect_bd_intf_net /sys_ps7/GMII_ETHERNET_1 /sys_rgmii/GMII
    connect_bd_intf_net /sys_rgmii/MDIO_PHY /eth1_mdio
    connect_bd_intf_net /sys_rgmii/RGMII /eth1_rgmii
    connect_bd_net /sys_ps7/ENET1_EXT_INTIN /eth1_intn
    connect_bd_net -net /sys_200m_clk /sys_rgmii_rstgen/slowest_sync_clk
    connect_bd_net -net /sys_200m_clk /sys_rgmii/clkin
    connect_bd_net /sys_rgmii_rstgen/ext_reset_in /sys_ps7/FCLK_RESET0_N
    connect_bd_net /sys_rgmii_rstgen/peripheral_reset /sys_rgmii/tx_reset
    connect_bd_net /sys_rgmii_rstgen/peripheral_reset /sys_rgmii/rx_reset
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_core/vdma_clk
    connect_bd_net /axi_hdmi_core/hdmi_clk /axi_hdmi_clkgen/clk_0
    connect_bd_net /axi_hdmi_core/hdmi_out_clk /hdmi_out_clk
    connect_bd_net /axi_hdmi_core/hdmi_16_hsync /hdmi_hsync
    connect_bd_net /axi_hdmi_core/hdmi_16_vsync /hdmi_vsync
    connect_bd_net /axi_hdmi_core/hdmi_16_data_e /hdmi_data_e
    connect_bd_net /axi_hdmi_core/hdmi_16_data /hdmi_data
    connect_bd_intf_net /axi_hdmi_dma/m_axis /axi_hdmi_core/s_axis
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_dma/s_axi_aresetn
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_dma/m_src_axi_aresetn
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_dma/s_axi_aclk
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_dma/m_src_axi_aclk
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_dma/m_axis_aclk
    connect_bd_net -net /sys_cpu_clk /axi_spdif_tx_core/dma_req_aclk
    connect_bd_net -net /sys_cpu_clk /sys_ps7/DMA0_ACLK
    connect_bd_net -net /sys_cpu_resetn /axi_spdif_tx_core/dma_req_rstn
    connect_bd_intf_net /sys_ps7/DMA0_REQ /axi_spdif_tx_core/dma_req
    connect_bd_intf_net /sys_ps7/DMA0_ACK /axi_spdif_tx_core/dma_ack
    connect_bd_net -net /sys_200m_clk /sys_audio_clkgen/clk_in1
    connect_bd_net -net /sys_cpu_resetn /sys_audio_clkgen/resetn
    connect_bd_net /sys_audio_clkgen/clk_out1 /axi_spdif_tx_core/spdif_data_clk
    connect_bd_net /spdif /axi_spdif_tx_core/spdif_tx_o
    connect_bd_net -net /sys_cpu_clk /axi_i2s_adi/dma_req_rx_aclk
    connect_bd_net -net /sys_cpu_clk /axi_i2s_adi/dma_req_tx_aclk
    connect_bd_net -net /sys_cpu_clk /sys_ps7/DMA1_ACLK
    connect_bd_net -net /sys_cpu_clk /sys_ps7/DMA2_ACLK
    connect_bd_net -net /sys_cpu_resetn /axi_i2s_adi/dma_req_rx_rstn
    connect_bd_net -net /sys_cpu_resetn /axi_i2s_adi/dma_req_tx_rstn
    connect_bd_intf_net /sys_ps7/DMA1_REQ /axi_i2s_adi/dma_req_tx
    connect_bd_intf_net /sys_ps7/DMA1_ACK /axi_i2s_adi/dma_ack_tx
    connect_bd_intf_net /sys_ps7/DMA2_REQ /axi_i2s_adi/dma_req_rx
    connect_bd_intf_net /sys_ps7/DMA2_ACK /axi_i2s_adi/dma_ack_rx
    connect_bd_net /sys_audio_clkgen/clk_out1 /i2s_mclk
    connect_bd_net /sys_audio_clkgen/clk_out1 /axi_i2s_adi/data_clk_i
    connect_bd_intf_net /i2s /axi_i2s_adi/i2s
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In15
    connect_bd_net /sys_concat_intc/In15 /axi_hdmi_dma/irq
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M05_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_clkgen/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M05_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_clkgen/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M05_AXI /axi_hdmi_clkgen/s_axi
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M06_ACLK
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M06_ARESETN
    connect_bd_intf_net /axi_cpu_interconnect/M06_AXI /axi_hdmi_dma/s_axi
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M07_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_core/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M07_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_core/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M07_AXI /axi_hdmi_core/s_axi
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M08_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_spdif_tx_core/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M08_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_spdif_tx_core/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M08_AXI /axi_spdif_tx_core/s_axi
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M09_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_i2s_adi/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M09_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_i2s_adi/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M09_AXI /axi_i2s_adi/s_axi
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    connect_bd_net -net /sys_cpu_resetn /axi_hp0_interconnect/aresetn
    connect_bd_net -net /sys_cpu_clk /axi_hp0_interconnect/aclk
    connect_bd_intf_net /axi_hp0_interconnect/M00_AXI /sys_ps7/S_AXI_HP0
    connect_bd_net -net /sys_cpu_clk /sys_ps7/S_AXI_HP0_ACLK
    connect_bd_intf_net /axi_hp0_interconnect/S00_AXI /axi_hdmi_dma/m_src_axi
    WARNING: [BD 5-230] No cells matched 'get_bd_cells /sys_mb'
    WARNING: [BD 5-232] No interface pins matched 'get_bd_intf_pins -filter {NAME=~ *DLMB*} -of {}'
    Slave segment </sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM> is being mapped into address space </axi_hdmi_dma/m_src_axi> at <0x0000_0000 [ 1G ]>
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M10_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_pz_xcvrlb/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M10_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_pz_xcvrlb/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M10_AXI /axi_pz_xcvrlb/s_axi
    connect_bd_net /axi_pz_xcvrlb/ref_clk /gt_ref_clk_0
    connect_bd_net /axi_pz_xcvrlb/rx_p /gt_rx_p
    connect_bd_net /axi_pz_xcvrlb/rx_n /gt_rx_n
    connect_bd_net /axi_pz_xcvrlb/tx_p /gt_tx_p
    connect_bd_net /axi_pz_xcvrlb/tx_n /gt_tx_n
    connect_bd_net /clk_0 /axi_gpreg/d_clk_0
    connect_bd_net /clk_1 /axi_gpreg/d_clk_1
    connect_bd_net /gt_ref_clk_1 /axi_gpreg/d_clk_2
    connect_bd_net /gp_in_0 /axi_gpreg/up_gp_in_0
    connect_bd_net /gp_in_1 /axi_gpreg/up_gp_in_1
    connect_bd_net /gp_out_0 /axi_gpreg/up_gp_out_0
    connect_bd_net /gp_out_1 /axi_gpreg/up_gp_out_1
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M11_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_gpreg/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M11_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_gpreg/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M11_AXI /axi_gpreg/s_axi
    WARNING: [BD 5-230] No cells matched 'get_bd_cells ila_adc'
    connect_bd_net /rx_clk_in_p /axi_ad9361/rx_clk_in_p
    connect_bd_net /rx_clk_in_n /axi_ad9361/rx_clk_in_n
    connect_bd_net /rx_frame_in_p /axi_ad9361/rx_frame_in_p
    connect_bd_net /rx_frame_in_n /axi_ad9361/rx_frame_in_n
    connect_bd_net /rx_data_in_p /axi_ad9361/rx_data_in_p
    connect_bd_net /rx_data_in_n /axi_ad9361/rx_data_in_n
    connect_bd_net /tx_clk_out_p /axi_ad9361/tx_clk_out_p
    connect_bd_net /tx_clk_out_n /axi_ad9361/tx_clk_out_n
    connect_bd_net /tx_frame_out_p /axi_ad9361/tx_frame_out_p
    connect_bd_net /tx_frame_out_n /axi_ad9361/tx_frame_out_n
    connect_bd_net /tx_data_out_p /axi_ad9361/tx_data_out_p
    connect_bd_net /tx_data_out_n /axi_ad9361/tx_data_out_n
    connect_bd_net -net /sys_cpu_clk /sys_cpu_clk_out
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd> 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [#UNDEF] When using EMIO pins for SPI_0 tie SSIN High in the PL bitstream
    WARNING: [#UNDEF] When using EMIO pins for SPI_1 tie SSIN High in the PL bitstream
    WARNING: [BD 41-927] Following properties on pin /axi_sysid_0/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /rom_sys_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/delay_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK1 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/l_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_tdd_sync/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk_out have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	POLARITY=ACTIVE_HIGH 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_pack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	POLARITY=ACTIVE_HIGH 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_dac_upack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_hdmi_clkgen_0_clk_0 
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_out_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_hdmi_core_0_hdmi_out_clk 
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/vdma_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/spdif_data_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1 
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/dma_req_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/data_clk_i have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1 
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_tx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_rx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_pz_xcvrlb/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_gpreg/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    validate_bd_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 792.254 ; gain = 87.219
    INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run.
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd> 
    VHDL Output written to : E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/synth/system.v
    VHDL Output written to : E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/sim/system.v
    VHDL Output written to : E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/hdl/system_wrapper.v
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_ps7 .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_iic_main .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_concat_intc .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_rstgen .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_logic_inv .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_sysid_0 .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block rom_sys_0 .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block GND_1 .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/xbar .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361 .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_tdd_sync .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk_sel_concat .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk_sel .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk_reset .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_adc_fifo .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_adc_pack .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361_adc_dma .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361_dac_fifo .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_dac_upack .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361_dac_dma .
    Exporting to file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/hw_handoff/system_axi_hp1_interconnect_0.hwh
    Generated Block Design Tcl file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/hw_handoff/system_axi_hp1_interconnect_0_bd.tcl
    Generated Hardware Definition File e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/synth/system_axi_hp1_interconnect_0.hwdef
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hp1_interconnect .
    Exporting to file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/hw_handoff/system_axi_hp2_interconnect_0.hwh
    Generated Block Design Tcl file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/hw_handoff/system_axi_hp2_interconnect_0_bd.tcl
    Generated Hardware Definition File e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/synth/system_axi_hp2_interconnect_0.hwdef
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hp2_interconnect .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_rgmii .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_rgmii_rstgen .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hdmi_clkgen .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hdmi_core .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hdmi_dma .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_audio_clkgen .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_spdif_tx_core .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_i2s_adi .
    Exporting to file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/hw_handoff/system_axi_hp0_interconnect_0.hwh
    Generated Block Design Tcl file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/hw_handoff/system_axi_hp0_interconnect_0_bd.tcl
    Generated Hardware Definition File e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/synth/system_axi_hp0_interconnect_0.hwdef
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hp0_interconnect .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_pz_xcvrlb .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpreg .
    WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_pc_0/system_auto_pc_0_ooc.xdc'
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/s00_couplers/auto_pc .
    Exporting to file E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/hw_handoff/system.hwh
    Generated Block Design Tcl file E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl
    Generated Hardware Definition File E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/synth/system.hwdef
    generate_target: Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1113.816 ; gain = 321.562
    Skipping synthesis
    Skipping
    Preprocessing adrv9361z7035 ccfmc_lvds rxtx
    WARNING: [BD 5-234] No nets matched 'get_bd_nets util_ad9361_dac_upack_dac_data_0'
    WARNING: [BD 5-234] No nets matched 'get_bd_nets util_ad9361_dac_upack_dac_data_1'
    WARNING: [BD 5-234] No nets matched 'get_bd_nets util_ad9361_dac_upack_dac_data_2'
    WARNING: [BD 5-234] No nets matched 'get_bd_nets util_ad9361_dac_upack_dac_data_3'
    WARNING: [BD 41-597] NET <Net> has no source
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd> 
    WARNING: [#UNDEF] When using EMIO pins for SPI_0 tie SSIN High in the PL bitstream
    WARNING: [#UNDEF] When using EMIO pins for SPI_1 tie SSIN High in the PL bitstream
    WARNING: [BD 41-927] Following properties on pin /axi_sysid_0/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /rom_sys_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/delay_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK1 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/l_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_tdd_sync/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk_out have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	POLARITY=ACTIVE_HIGH 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_pack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	POLARITY=ACTIVE_HIGH 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_dac_upack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_hdmi_clkgen_0_clk_0 
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_out_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_hdmi_core_0_hdmi_out_clk 
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/vdma_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/spdif_data_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1 
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/dma_req_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/data_clk_i have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1 
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_tx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_rx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_pz_xcvrlb/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_gpreg/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
    Please check your design and connect them as needed: 
    /axi_ad9361_dac_fifo/din_valid_in_0
    /axi_ad9361_dac_fifo/din_valid_in_1
    /axi_ad9361_dac_fifo/din_valid_in_2
    /axi_ad9361_dac_fifo/din_valid_in_3
    
    validate_bd_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1125.434 ; gain = 11.617
    WARNING: [BD 41-597] NET <Net> has no source
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd> 
    INFO: [Common 17-206] Exiting Vivado at Thu Mar 17 17:55:35 2022...
    
    Elapsed time is 303.2003 seconds.
    
    ****** Vivado v2019.1 (64-bit)
      **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
      **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
        ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
    
    source vivado_insert_ip.tcl -notrace
    Scanning sources...
    Finished scanning sources
    WARNING: [filemgmt 56-3] IP Repository Path: Could not find the directory 'E:/hdl_prj/ghdl/library'.
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/ipcore'.
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'.
    WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/hdl_prj/ghdl/library'; Can't find the specified path.
    If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2019.1/data/ip'.
    INFO: [IP_Flow 19-949] Unzipped './ipcore/HDL_DUT_ip_v1_0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/ipcore'.
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/ipcore'
    INFO: [IP_Flow 19-1839] IP Catalog is up to date.
    Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - sys_ps7
    Adding component instance block -- xilinx.com:ip:axi_iic:2.0 - axi_iic_main
    Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - sys_concat_intc
    Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - sys_rstgen
    Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - sys_logic_inv
    Adding component instance block -- analog.com:user:axi_sysid:1.0 - axi_sysid_0
    Adding component instance block -- analog.com:user:sysid_rom:1.0 - rom_sys_0
    Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - GND_1
    Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_cpu_interconnect
    Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
    Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
    Adding component instance block -- analog.com:user:axi_ad9361:1.0 - axi_ad9361
    Adding component instance block -- analog.com:user:util_tdd_sync:1.0 - util_ad9361_tdd_sync
    Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - util_ad9361_divclk_sel_concat
    Adding component instance block -- xilinx.com:ip:util_reduced_logic:2.0 - util_ad9361_divclk_sel
    Adding component instance block -- analog.com:user:util_clkdiv:1.0 - util_ad9361_divclk
    Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - util_ad9361_divclk_reset
    Adding component instance block -- analog.com:user:util_wfifo:1.0 - util_ad9361_adc_fifo
    Adding component instance block -- analog.com:user:util_cpack2:1.0 - util_ad9361_adc_pack
    Adding component instance block -- analog.com:user:axi_dmac:1.0 - axi_ad9361_adc_dma
    Adding component instance block -- analog.com:user:util_rfifo:1.0 - axi_ad9361_dac_fifo
    Adding component instance block -- analog.com:user:util_upack2:1.0 - util_ad9361_dac_upack
    Adding component instance block -- analog.com:user:axi_dmac:1.0 - axi_ad9361_dac_dma
    Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_hp1_interconnect
    Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_hp2_interconnect
    Adding component instance block -- xilinx.com:ip:gmii_to_rgmii:4.0 - sys_rgmii
    Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - sys_rgmii_rstgen
    Adding component instance block -- analog.com:user:axi_clkgen:1.0 - axi_hdmi_clkgen
    Adding component instance block -- analog.com:user:axi_hdmi_tx:1.0 - axi_hdmi_core
    Adding component instance block -- analog.com:user:axi_dmac:1.0 - axi_hdmi_dma
    Adding component instance block -- xilinx.com:ip:clk_wiz:6.0 - sys_audio_clkgen
    Adding component instance block -- analog.com:user:axi_spdif_tx:1.0 - axi_spdif_tx_core
    Adding component instance block -- analog.com:user:axi_i2s_adi:1.0 - axi_i2s_adi
    Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_hp0_interconnect
    Adding component instance block -- analog.com:user:axi_xcvrlb:1.0 - axi_pz_xcvrlb
    Adding component instance block -- analog.com:user:axi_gpreg:1.0 - axi_gpreg
    Successfully read diagram <system> from BD file <E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/system.bd>
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /gpio_status'
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /gpio_ctl'
    WARNING: [BD 5-235] No pins matched 'get_bd_pins axi_ad9361_adc_dma/s_axis_ready'
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects {}'
    WARNING: [BD 5-235] No pins matched 'get_bd_pins axi_ad9361_adc_dma/s_axis_ready'
    ERROR: [BD 41-701] connect_bd_net requires at least two pins/ports, or one pin/port and a net
    ERROR: [BD 5-4] Error: running connect_bd_net.
    ERROR: [Common 17-39] 'connect_bd_net' failed due to earlier errors.
    
        while executing
    "connect_bd_net -net [get_bd_nets -of_objects [get_bd_pins axi_ad9361_adc_dma/s_axis_ready]] [get_bd_pins $HDLCODERIPINST/dma_rdy] [get_bd_pins axi_ad9..."
        (file "vivado_insert_ip.tcl" line 24)
    INFO: [Common 17-206] Exiting Vivado at Thu Mar 17 17:55:44 2022...
    
    Elapsed time is 8.1278 seconds.




    I don't know what should I do or what the reason for this error , I need help to go through  or workaround this issue, second issue pls. explain thoroughly  since this is my first project with this stuff

    thank you

    Regards

  • Can you make sure your hdl_prj folder is clean before building? It looks like the system.bd is getting overwritten.

    -Travis

  • Hello

    I repeated HDL workflow with a NEW destination folder to make sure there is no any influence from previous attempts. but still i got the same previous errors  

    ERROR: [BD 41-701] connect_bd_net requires at least two pins/ports, or one pin/port and a net
    ERROR: [BD 5-4] Error: running connect_bd_net.
    ERROR: [Common 17-39] 'connect_bd_net' failed due to earlier errors.

    with the same previous log.

    I tried to run "frequency-hopping/hdlworkflow.m"  i got this log file

    >> hdlworkflow
    ### Workflow begin.
    ### Loading settings from model.
    ### Model compilation and PIR creation begin.
    ### Generating HDL for 'frequency_hopping/HDL_DUT'.
    ### Using the config set for model frequency_hopping for HDL code generation parameters.
    ### Running HDL checks on the model 'frequency_hopping'.
    ### Begin compilation of the model 'frequency_hopping'...
    ### Failure to initialize the model frequency_hopping.
    ### Creating HDL Code Generation Check Report HDL_DUT_ip_src_HDL_DUT_report.html
    ### HDL check for 'frequency_hopping' complete with 1 errors, 0 warnings, and 0 messages.
    ### HDL check for 'frequency_hopping' complete with 1 errors, 0 warnings, and 0 messages.
    >> hdlworkflow
    ### Workflow begin.
    ### Loading settings from model.
    ### Model compilation and PIR creation begin.
    ### Generating HDL for 'frequency_hopping/HDL_DUT'.
    ### Using the config set for model frequency_hopping for HDL code generation parameters.
    ### Running HDL checks on the model 'frequency_hopping'.
    ### Begin compilation of the model 'frequency_hopping'...
    ### Model compilation and PIR creation complete.
    Warning: Interface is not assigned to model port 'TxDMAEnable'. 
    > In downstream.tool.displayValidateCell
    In downstream.DownstreamIntegrationDriver/validateTargetInterface
    In hwcli.runWorkflow
    In hdlcoder.runWorkflow (line 27)
    In hdlworkflow (line 172) 
    ### ++++++++++++++ Task Generate RTL Code and IP Core ++++++++++++++
    ### Generate RTL Code and IP Core
    ### Applying HDL optimizations on the model 'frequency_hopping'...
    ### 'LUTMapToRAM' is set to 'On' for the model. This option is used to map lookup tables to a block RAM in hardware.  To disable pipeline insertion for mapping lookup tables to RAM, set the option to 'Off'.
    ### Begin model generation.
    ### Model generation complete.
    ### Begin Verilog Code Generation for 'frequency_hopping'.
    ### Working on frequency_hopping/HDL_DUT/DEBUG as hdl_prj\hdlsrc\frequency_hopping\HDL_DUT_ip_src_DEBUG.v.
    ### Working on frequency_hopping/HDL_DUT/Enable Control as hdl_prj\hdlsrc\frequency_hopping\HDL_DUT_ip_src_Enable_Control.v.
    ### Working on frequency_hopping/HDL_DUT as hdl_prj\hdlsrc\frequency_hopping\HDL_DUT_ip_src_HDL_DUT.v.
    ### Code Generation for 'frequency_hopping' completed.
    ### Generating HTML files for code generation report at frequency_hopping_codegen_rpt.html
    ### Creating HDL Code Generation Check Report HDL_DUT_ip_src_HDL_DUT_report.html
    ### HDL check for 'frequency_hopping' complete with 0 errors, 0 warnings, and 1 messages.
    ### HDL code generation complete.
    ### Begin IP core top level wrapper code generation.
    ### Begin Verilog Code Generation for 'frequency_hopping'.
    ### Working on HDL_DUT_ip/HDL_DUT_ip_reset_sync as hdl_prj\hdlsrc\frequency_hopping\HDL_DUT_ip_reset_sync.v.
    ### Working on HDL_DUT_ip/HDL_DUT_ip_dut as hdl_prj\hdlsrc\frequency_hopping\HDL_DUT_ip_dut.v.
    ### Working on HDL_DUT_ip/HDL_DUT_ip_axi_lite/HDL_DUT_ip_addr_decoder as hdl_prj\hdlsrc\frequency_hopping\HDL_DUT_ip_addr_decoder.v.
    ### Working on HDL_DUT_ip/HDL_DUT_ip_axi_lite/HDL_DUT_ip_axi_lite_module as hdl_prj\hdlsrc\frequency_hopping\HDL_DUT_ip_axi_lite_module.v.
    ### Working on HDL_DUT_ip/HDL_DUT_ip_axi_lite as hdl_prj\hdlsrc\frequency_hopping\HDL_DUT_ip_axi_lite.v.
    ### Working on HDL_DUT_ip as hdl_prj\hdlsrc\frequency_hopping\HDL_DUT_ip.v.
    ### Code Generation for 'frequency_hopping' completed.
    ### HDL code generation complete.
    ### Begin IP core packaging.
    ### Generating IP core report frequency_hopping_ip_core_report.html
     
    ****** Vivado v2019.1 (64-bit) 
      **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 
      **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 
        ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
     
    source vivado_ip_package.tcl -notrace 
    INFO: [IP_Flow 19-234] Refreshing IP repositories 
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/ipcore'. 
    WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'e:/hdl_prj/ipcore' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'e:/hdl_prj/ipcore/HDL_DUT_ip_v1_0/prj_ip'.) 
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2019.1/data/ip'. 
    INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). 
    INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite_ARESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). 
    INFO: [IP_Flow 19-5107] Inferred bus interface 'IPCORE_RESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). 
    INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite_ACLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). 
    INFO: [IP_Flow 19-5107] Inferred bus interface 'IPCORE_CLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). 
    INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ARESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. 
    INFO: [IP_Flow 19-4728] Bus Interface 'IPCORE_RESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. 
    INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ACLK': Added interface parameter 'ASSOCIATED_BUSIF' with value 'AXI4_Lite'. 
    INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'AXI4_Lite_ARESETN'. 
    INFO: [IP_Flow 19-4728] Bus Interface 'IPCORE_CLK': Added interface parameter 'ASSOCIATED_RESET' with value 'IPCORE_RESETN'. 
    WARNING: [IP_Flow 19-3153] Bus Interface 'IPCORE_CLK': ASSOCIATED_BUSIF bus parameter is missing. 
    INFO: [IP_Flow 19-2181] Payment Required is not set for this core. 
    INFO: [IP_Flow 19-2187] The Product Guide file is missing. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_DEBUG.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_DEBUG.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_Enable_Control.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_Enable_Control.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_HDL_DUT.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_HDL_DUT.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_reset_sync.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_reset_sync.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_dut.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_dut.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_addr_decoder.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_addr_decoder.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_axi_lite_module.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_axi_lite_module.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_axi_lite.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_axi_lite.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again. 
    INFO: [Common 17-206] Exiting Vivado at Sun Mar 20 11:38:09 2022... 
    ### Generated logfile: hdl_prj\hdlsrc\frequency_hopping\workflow_task_VivadoIPPackager.log
    ### Task "Vivado IP Packager" successful.
    ### 
    ****** Vivado v2019.1 (64-bit)
      **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
      **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
        ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
    
    source vivado_ip_package.tcl -notrace
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/ipcore'.
    WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'e:/hdl_prj/ipcore' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'e:/hdl_prj/ipcore/HDL_DUT_ip_v1_0/prj_ip'.)
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2019.1/data/ip'.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
    INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite_ARESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
    INFO: [IP_Flow 19-5107] Inferred bus interface 'IPCORE_RESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
    INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite_ACLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
    INFO: [IP_Flow 19-5107] Inferred bus interface 'IPCORE_CLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
    INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ARESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
    INFO: [IP_Flow 19-4728] Bus Interface 'IPCORE_RESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
    INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ACLK': Added interface parameter 'ASSOCIATED_BUSIF' with value 'AXI4_Lite'.
    INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'AXI4_Lite_ARESETN'.
    INFO: [IP_Flow 19-4728] Bus Interface 'IPCORE_CLK': Added interface parameter 'ASSOCIATED_RESET' with value 'IPCORE_RESETN'.
    WARNING: [IP_Flow 19-3153] Bus Interface 'IPCORE_CLK': ASSOCIATED_BUSIF bus parameter is missing.
    INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
    INFO: [IP_Flow 19-2187] The Product Guide file is missing.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_DEBUG.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_DEBUG.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_Enable_Control.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_Enable_Control.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_HDL_DUT.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_HDL_DUT.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_reset_sync.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_reset_sync.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_dut.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_dut.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_addr_decoder.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_addr_decoder.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_axi_lite_module.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_axi_lite_module.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_axi_lite.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_axi_lite.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
    INFO: [Common 17-206] Exiting Vivado at Sun Mar 20 11:38:09 2022...
    
    Elapsed time is 9.4813 seconds.
    
    ### ++++++++++++++ Task Create Project ++++++++++++++
    ### Create Project
     
    ****** Vivado v2019.1 (64-bit) 
      **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 
      **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 
        ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
     
    source vivado_create_prj.tcl -notrace 
    INFO: [IP_Flow 19-234] Refreshing IP repositories 
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/ipcore'. 
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2019.1/data/ip'. 
    INFO: [IP_Flow 19-1839] IP Catalog is up to date. 
    Starting Transceiver Toolbox HDL build 
    Building: 
    - axi_ad9361 
    - axi_clkgen 
    - axi_dmac 
    - axi_gpreg 
    - axi_hdmi_tx 
    - axi_i2s_adi 
    - axi_spdif_tx 
    - axi_sysid 
    - sysid_rom 
    - util_pack/util_cpack2 
    - util_pack/util_upack2 
    - util_rfifo 
    - util_tdd_sync 
    - util_wfifo 
    - xilinx/axi_xcvrlb 
    - xilinx/util_clkdiv 
    Please wait, this might take a few minutes 
    - Done building axi_ad9361 
    - Done building axi_clkgen 
    - Done building util_cdc 
    - Done building util_axis_fifo 
    - Done building axi_dmac 
    - Done building axi_gpreg 
    - Done building axi_hdmi_tx 
    - Done building axi_i2s_adi 
    - Done building axi_spdif_tx 
    - Done building axi_sysid 
    - Done building sysid_rom 
    - Done building util_pack/util_cpack2 
    - Done building util_pack/util_upack2 
    - Done building util_rfifo 
    - Done building util_tdd_sync 
    - Done building util_wfifo 
    - Done building xilinx/axi_xcvrlb 
    - Done building xilinx/util_clkdiv 
    INFO: [IP_Flow 19-234] Refreshing IP repositories 
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/ipcore'. 
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'. 
    WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/hdl_prj/ghdl/library'; Can't find the specified path. 
    If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. 
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd>  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    create_bd_net sys_cpu_clk 
    connect_bd_net -net /sys_cpu_clk /sys_ps7/FCLK_CLK0 
    create_bd_net sys_200m_clk 
    connect_bd_net -net /sys_200m_clk /sys_ps7/FCLK_CLK1 
    create_bd_net sys_cpu_reset 
    connect_bd_net -net /sys_cpu_reset /sys_rstgen/peripheral_reset 
    create_bd_net sys_cpu_resetn 
    connect_bd_net -net /sys_cpu_resetn /sys_rstgen/peripheral_aresetn 
    connect_bd_net -net /sys_cpu_clk /sys_rstgen/slowest_sync_clk 
    connect_bd_net /sys_rstgen/ext_reset_in /sys_ps7/FCLK_RESET0_N 
    connect_bd_intf_net /ddr /sys_ps7/DDR 
    connect_bd_net /gpio_i /sys_ps7/GPIO_I 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/GPIO_I is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0 
    connect_bd_net /gpio_o /sys_ps7/GPIO_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/GPIO_O is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0 
    connect_bd_net /gpio_t /sys_ps7/GPIO_T 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/GPIO_T is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0 
    connect_bd_intf_net /fixed_io /sys_ps7/FIXED_IO 
    connect_bd_intf_net /iic_main /axi_iic_main/IIC 
    connect_bd_net /sys_logic_inv/Res /sys_ps7/USB0_VBUS_PWRFAULT 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/USB0_VBUS_PWRFAULT is being overridden by the user. This pin will not be connected as a part of interface connection USBIND_0 
    connect_bd_net /sys_logic_inv/Op1 /otg_vbusoc 
    connect_bd_net /spi0_csn_2_o /sys_ps7/SPI0_SS2_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS2_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0 
    connect_bd_net /spi0_csn_1_o /sys_ps7/SPI0_SS1_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS1_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0 
    connect_bd_net /spi0_csn_0_o /sys_ps7/SPI0_SS_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0 
    connect_bd_net /spi0_csn_i /sys_ps7/SPI0_SS_I 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0 
    connect_bd_net /spi0_clk_i /sys_ps7/SPI0_SCLK_I 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SCLK_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0 
    connect_bd_net /spi0_clk_o /sys_ps7/SPI0_SCLK_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SCLK_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0 
    connect_bd_net /spi0_sdo_i /sys_ps7/SPI0_MOSI_I 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_MOSI_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0 
    connect_bd_net /spi0_sdo_o /sys_ps7/SPI0_MOSI_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_MOSI_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0 
    connect_bd_net /spi0_sdi_i /sys_ps7/SPI0_MISO_I 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_MISO_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0 
    connect_bd_net /spi1_csn_2_o /sys_ps7/SPI1_SS2_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS2_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1 
    connect_bd_net /spi1_csn_1_o /sys_ps7/SPI1_SS1_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS1_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1 
    connect_bd_net /spi1_csn_0_o /sys_ps7/SPI1_SS_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1 
    connect_bd_net /spi1_csn_i /sys_ps7/SPI1_SS_I 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1 
    connect_bd_net /spi1_clk_i /sys_ps7/SPI1_SCLK_I 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SCLK_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1 
    connect_bd_net /spi1_clk_o /sys_ps7/SPI1_SCLK_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SCLK_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1 
    connect_bd_net /spi1_sdo_i /sys_ps7/SPI1_MOSI_I 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_MOSI_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1 
    connect_bd_net /spi1_sdo_o /sys_ps7/SPI1_MOSI_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_MOSI_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1 
    connect_bd_net /spi1_sdi_i /sys_ps7/SPI1_MISO_I 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_MISO_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1 
    connect_bd_net /axi_sysid_0/rom_addr /rom_sys_0/rom_addr 
    connect_bd_net /axi_sysid_0/sys_rom_data /rom_sys_0/rom_data 
    connect_bd_net -net /sys_cpu_clk /rom_sys_0/clk 
    connect_bd_net /sys_concat_intc/dout /sys_ps7/IRQ_F2P 
    connect_bd_net GND_1/dout sys_concat_intc/In15 
    connect_bd_net /sys_concat_intc/In14 /axi_iic_main/iic2intc_irpt 
    connect_bd_net GND_1/dout sys_concat_intc/In13 
    connect_bd_net GND_1/dout sys_concat_intc/In12 
    connect_bd_net GND_1/dout sys_concat_intc/In11 
    connect_bd_net GND_1/dout sys_concat_intc/In10 
    connect_bd_net GND_1/dout sys_concat_intc/In9 
    connect_bd_net GND_1/dout sys_concat_intc/In8 
    connect_bd_net GND_1/dout sys_concat_intc/In7 
    connect_bd_net GND_1/dout sys_concat_intc/In6 
    connect_bd_net GND_1/dout sys_concat_intc/In5 
    connect_bd_net GND_1/dout sys_concat_intc/In4 
    connect_bd_net GND_1/dout sys_concat_intc/In3 
    connect_bd_net GND_1/dout sys_concat_intc/In2 
    connect_bd_net GND_1/dout sys_concat_intc/In1 
    connect_bd_net GND_1/dout sys_concat_intc/In0 
    connect_bd_net -net /sys_cpu_clk /sys_ps7/M_AXI_GP0_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/S00_ACLK 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/S00_ARESETN 
    connect_bd_intf_net /axi_cpu_interconnect/S00_AXI /sys_ps7/M_AXI_GP0 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M00_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_sysid_0/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M00_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_sysid_0/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M00_AXI /axi_sysid_0/s_axi 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M01_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_iic_main/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M01_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_iic_main/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M01_AXI /axi_iic_main/S_AXI 
    connect_bd_net -net /sys_200m_clk /axi_ad9361/delay_clk 
    connect_bd_net /axi_ad9361/l_clk /axi_ad9361/clk 
    connect_bd_net /enable /axi_ad9361/enable 
    connect_bd_net /txnrx /axi_ad9361/txnrx 
    connect_bd_net /up_enable /axi_ad9361/up_enable 
    connect_bd_net /up_txnrx /axi_ad9361/up_txnrx 
    connect_bd_net -net /sys_cpu_clk /util_ad9361_tdd_sync/clk 
    connect_bd_net -net /sys_cpu_resetn /util_ad9361_tdd_sync/rstn 
    connect_bd_net /util_ad9361_tdd_sync/sync_out /axi_ad9361/tdd_sync 
    connect_bd_net /util_ad9361_tdd_sync/sync_mode /axi_ad9361/tdd_sync_cntr 
    connect_bd_net /tdd_sync_t /axi_ad9361/tdd_sync_cntr 
    connect_bd_net /tdd_sync_o /util_ad9361_tdd_sync/sync_out 
    connect_bd_net /tdd_sync_i /util_ad9361_tdd_sync/sync_in 
    connect_bd_net /gps_pps /axi_ad9361/gps_pps 
    WARNING: [BD 41-1753] The name 'util_ad9361_divclk_sel_concat' you have specified is long. The Windows OS has path length limitations. It is recommended you use shorter names(less than 25 characters) to reduce the likelihood of issues when/if running on windows OS. 
    connect_bd_net /axi_ad9361/adc_r1_mode /util_ad9361_divclk_sel_concat/In0 
    connect_bd_net /axi_ad9361/dac_r1_mode /util_ad9361_divclk_sel_concat/In1 
    connect_bd_net /util_ad9361_divclk_sel_concat/dout /util_ad9361_divclk_sel/Op1 
    connect_bd_net /util_ad9361_divclk_sel/Res /util_ad9361_divclk/clk_sel 
    connect_bd_net /axi_ad9361/l_clk /util_ad9361_divclk/clk 
    connect_bd_net /sys_rstgen/peripheral_aresetn /util_ad9361_divclk_reset/ext_reset_in 
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_divclk_reset/slowest_sync_clk 
    connect_bd_net /axi_ad9361/l_clk /util_ad9361_adc_fifo/din_clk 
    connect_bd_net /axi_ad9361/rst /util_ad9361_adc_fifo/din_rst 
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_adc_fifo/dout_clk 
    connect_bd_net /util_ad9361_divclk_reset/peripheral_aresetn /util_ad9361_adc_fifo/dout_rstn 
    connect_bd_net /axi_ad9361/adc_enable_i0 /util_ad9361_adc_fifo/din_enable_0 
    connect_bd_net /axi_ad9361/adc_valid_i0 /util_ad9361_adc_fifo/din_valid_0 
    connect_bd_net /axi_ad9361/adc_data_i0 /util_ad9361_adc_fifo/din_data_0 
    connect_bd_net /axi_ad9361/adc_enable_q0 /util_ad9361_adc_fifo/din_enable_1 
    connect_bd_net /axi_ad9361/adc_valid_q0 /util_ad9361_adc_fifo/din_valid_1 
    connect_bd_net /axi_ad9361/adc_data_q0 /util_ad9361_adc_fifo/din_data_1 
    connect_bd_net /axi_ad9361/adc_enable_i1 /util_ad9361_adc_fifo/din_enable_2 
    connect_bd_net /axi_ad9361/adc_valid_i1 /util_ad9361_adc_fifo/din_valid_2 
    connect_bd_net /axi_ad9361/adc_data_i1 /util_ad9361_adc_fifo/din_data_2 
    connect_bd_net /axi_ad9361/adc_enable_q1 /util_ad9361_adc_fifo/din_enable_3 
    connect_bd_net /axi_ad9361/adc_valid_q1 /util_ad9361_adc_fifo/din_valid_3 
    connect_bd_net /axi_ad9361/adc_data_q1 /util_ad9361_adc_fifo/din_data_3 
    connect_bd_net /util_ad9361_adc_fifo/din_ovf /axi_ad9361/adc_dovf 
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_adc_pack/clk 
    connect_bd_net /util_ad9361_divclk_reset/peripheral_reset /util_ad9361_adc_pack/reset 
    connect_bd_net /util_ad9361_adc_fifo/dout_valid_0 /util_ad9361_adc_pack/fifo_wr_en 
    connect_bd_net /util_ad9361_adc_pack/fifo_wr_overflow /util_ad9361_adc_fifo/dout_ovf 
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_0 /util_ad9361_adc_pack/enable_0 
    connect_bd_net /util_ad9361_adc_fifo/dout_data_0 /util_ad9361_adc_pack/fifo_wr_data_0 
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_1 /util_ad9361_adc_pack/enable_1 
    connect_bd_net /util_ad9361_adc_fifo/dout_data_1 /util_ad9361_adc_pack/fifo_wr_data_1 
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_2 /util_ad9361_adc_pack/enable_2 
    connect_bd_net /util_ad9361_adc_fifo/dout_data_2 /util_ad9361_adc_pack/fifo_wr_data_2 
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_3 /util_ad9361_adc_pack/enable_3 
    connect_bd_net /util_ad9361_adc_fifo/dout_data_3 /util_ad9361_adc_pack/fifo_wr_data_3 
    connect_bd_net /util_ad9361_divclk/clk_out /axi_ad9361_adc_dma/fifo_wr_clk 
    connect_bd_intf_net /util_ad9361_adc_pack/packed_fifo_wr /axi_ad9361_adc_dma/fifo_wr 
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_adc_dma/m_dest_axi_aresetn 
    connect_bd_net /axi_ad9361/l_clk /axi_ad9361_dac_fifo/dout_clk 
    connect_bd_net /axi_ad9361/rst /axi_ad9361_dac_fifo/dout_rst 
    connect_bd_net /util_ad9361_divclk/clk_out /axi_ad9361_dac_fifo/din_clk 
    connect_bd_net /util_ad9361_divclk_reset/peripheral_aresetn /axi_ad9361_dac_fifo/din_rstn 
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_0 /axi_ad9361/dac_enable_i0 
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_0 /axi_ad9361/dac_valid_i0 
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_0 /axi_ad9361/dac_data_i0 
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_1 /axi_ad9361/dac_enable_q0 
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_1 /axi_ad9361/dac_valid_q0 
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_1 /axi_ad9361/dac_data_q0 
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_2 /axi_ad9361/dac_enable_i1 
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_2 /axi_ad9361/dac_valid_i1 
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_2 /axi_ad9361/dac_data_i1 
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_3 /axi_ad9361/dac_enable_q1 
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_3 /axi_ad9361/dac_valid_q1 
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_3 /axi_ad9361/dac_data_q1 
    connect_bd_net /axi_ad9361_dac_fifo/dout_unf /axi_ad9361/dac_dunf 
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_dac_upack/clk 
    connect_bd_net /util_ad9361_divclk_reset/peripheral_reset /util_ad9361_dac_upack/reset 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_en /axi_ad9361_dac_fifo/din_valid_0 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_underflow /axi_ad9361_dac_fifo/din_unf 
    connect_bd_net /util_ad9361_dac_upack/enable_0 /axi_ad9361_dac_fifo/din_enable_0 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_0 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_0 /axi_ad9361_dac_fifo/din_data_0 
    connect_bd_net /util_ad9361_dac_upack/enable_1 /axi_ad9361_dac_fifo/din_enable_1 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_1 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_1 /axi_ad9361_dac_fifo/din_data_1 
    connect_bd_net /util_ad9361_dac_upack/enable_2 /axi_ad9361_dac_fifo/din_enable_2 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_2 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_2 /axi_ad9361_dac_fifo/din_data_2 
    connect_bd_net /util_ad9361_dac_upack/enable_3 /axi_ad9361_dac_fifo/din_enable_3 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_3 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_3 /axi_ad9361_dac_fifo/din_data_3 
    connect_bd_net /util_ad9361_divclk/clk_out /axi_ad9361_dac_dma/m_axis_aclk 
    connect_bd_intf_net /axi_ad9361_dac_dma/m_axis /util_ad9361_dac_upack/s_axis 
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_dac_dma/m_src_axi_aresetn 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M02_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_ad9361/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M02_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M02_AXI /axi_ad9361/s_axi 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M03_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_adc_dma/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M03_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_adc_dma/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M03_AXI /axi_ad9361_adc_dma/s_axi 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M04_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_dac_dma/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M04_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_dac_dma/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M04_AXI /axi_ad9361_dac_dma/s_axi 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    connect_bd_net -net /sys_cpu_resetn /axi_hp1_interconnect/aresetn 
    connect_bd_net -net /sys_cpu_clk /axi_hp1_interconnect/aclk 
    connect_bd_intf_net /axi_hp1_interconnect/M00_AXI /sys_ps7/S_AXI_HP1 
    connect_bd_net -net /sys_cpu_clk /sys_ps7/S_AXI_HP1_ACLK 
    connect_bd_intf_net /axi_hp1_interconnect/S00_AXI /axi_ad9361_adc_dma/m_dest_axi 
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_adc_dma/m_dest_axi_aclk 
    WARNING: [BD 5-230] No cells matched 'get_bd_cells /sys_mb' 
    WARNING: [BD 5-232] No interface pins matched 'get_bd_intf_pins -filter {NAME=~ *DLMB*} -of {}' 
    Slave segment </sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM> is being mapped into address space </axi_ad9361_adc_dma/m_dest_axi> at <0x0000_0000 [ 1G ]> 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    connect_bd_net -net /sys_cpu_resetn /axi_hp2_interconnect/aresetn 
    connect_bd_net -net /sys_cpu_clk /axi_hp2_interconnect/aclk 
    connect_bd_intf_net /axi_hp2_interconnect/M00_AXI /sys_ps7/S_AXI_HP2 
    connect_bd_net -net /sys_cpu_clk /sys_ps7/S_AXI_HP2_ACLK 
    connect_bd_intf_net /axi_hp2_interconnect/S00_AXI /axi_ad9361_dac_dma/m_src_axi 
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_dac_dma/m_src_axi_aclk 
    WARNING: [BD 5-230] No cells matched 'get_bd_cells /sys_mb' 
    WARNING: [BD 5-232] No interface pins matched 'get_bd_intf_pins -filter {NAME=~ *DLMB*} -of {}' 
    Slave segment </sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM> is being mapped into address space </axi_ad9361_dac_dma/m_src_axi> at <0x0000_0000 [ 1G ]> 
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In13 
    connect_bd_net /sys_concat_intc/In13 /axi_ad9361_adc_dma/irq 
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In12 
    connect_bd_net /sys_concat_intc/In12 /axi_ad9361_dac_dma/irq 
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In11 
    connect_bd_net /sys_concat_intc/In11 /axi_ad9361/gps_pps_irq 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [BD 41-721] Attempt to set value '0' on disabled parameter 'SYNC_TRANSFER_START' of cell '/axi_hdmi_dma' is ignored 
    connect_bd_net -net /sys_200m_clk /axi_hdmi_clkgen/clk 
    connect_bd_intf_net /sys_ps7/MDIO_ETHERNET_1 /sys_rgmii/MDIO_GEM 
    connect_bd_intf_net /sys_ps7/GMII_ETHERNET_1 /sys_rgmii/GMII 
    connect_bd_intf_net /sys_rgmii/MDIO_PHY /eth1_mdio 
    connect_bd_intf_net /sys_rgmii/RGMII /eth1_rgmii 
    connect_bd_net /sys_ps7/ENET1_EXT_INTIN /eth1_intn 
    connect_bd_net -net /sys_200m_clk /sys_rgmii_rstgen/slowest_sync_clk 
    connect_bd_net -net /sys_200m_clk /sys_rgmii/clkin 
    connect_bd_net /sys_rgmii_rstgen/ext_reset_in /sys_ps7/FCLK_RESET0_N 
    connect_bd_net /sys_rgmii_rstgen/peripheral_reset /sys_rgmii/tx_reset 
    connect_bd_net /sys_rgmii_rstgen/peripheral_reset /sys_rgmii/rx_reset 
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_core/vdma_clk 
    connect_bd_net /axi_hdmi_core/hdmi_clk /axi_hdmi_clkgen/clk_0 
    connect_bd_net /axi_hdmi_core/hdmi_out_clk /hdmi_out_clk 
    connect_bd_net /axi_hdmi_core/hdmi_16_hsync /hdmi_hsync 
    connect_bd_net /axi_hdmi_core/hdmi_16_vsync /hdmi_vsync 
    connect_bd_net /axi_hdmi_core/hdmi_16_data_e /hdmi_data_e 
    connect_bd_net /axi_hdmi_core/hdmi_16_data /hdmi_data 
    connect_bd_intf_net /axi_hdmi_dma/m_axis /axi_hdmi_core/s_axis 
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_dma/s_axi_aresetn 
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_dma/m_src_axi_aresetn 
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_dma/s_axi_aclk 
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_dma/m_src_axi_aclk 
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_dma/m_axis_aclk 
    connect_bd_net -net /sys_cpu_clk /axi_spdif_tx_core/dma_req_aclk 
    connect_bd_net -net /sys_cpu_clk /sys_ps7/DMA0_ACLK 
    connect_bd_net -net /sys_cpu_resetn /axi_spdif_tx_core/dma_req_rstn 
    connect_bd_intf_net /sys_ps7/DMA0_REQ /axi_spdif_tx_core/dma_req 
    connect_bd_intf_net /sys_ps7/DMA0_ACK /axi_spdif_tx_core/dma_ack 
    connect_bd_net -net /sys_200m_clk /sys_audio_clkgen/clk_in1 
    connect_bd_net -net /sys_cpu_resetn /sys_audio_clkgen/resetn 
    connect_bd_net /sys_audio_clkgen/clk_out1 /axi_spdif_tx_core/spdif_data_clk 
    connect_bd_net /spdif /axi_spdif_tx_core/spdif_tx_o 
    connect_bd_net -net /sys_cpu_clk /axi_i2s_adi/dma_req_rx_aclk 
    connect_bd_net -net /sys_cpu_clk /axi_i2s_adi/dma_req_tx_aclk 
    connect_bd_net -net /sys_cpu_clk /sys_ps7/DMA1_ACLK 
    connect_bd_net -net /sys_cpu_clk /sys_ps7/DMA2_ACLK 
    connect_bd_net -net /sys_cpu_resetn /axi_i2s_adi/dma_req_rx_rstn 
    connect_bd_net -net /sys_cpu_resetn /axi_i2s_adi/dma_req_tx_rstn 
    connect_bd_intf_net /sys_ps7/DMA1_REQ /axi_i2s_adi/dma_req_tx 
    connect_bd_intf_net /sys_ps7/DMA1_ACK /axi_i2s_adi/dma_ack_tx 
    connect_bd_intf_net /sys_ps7/DMA2_REQ /axi_i2s_adi/dma_req_rx 
    connect_bd_intf_net /sys_ps7/DMA2_ACK /axi_i2s_adi/dma_ack_rx 
    connect_bd_net /sys_audio_clkgen/clk_out1 /i2s_mclk 
    connect_bd_net /sys_audio_clkgen/clk_out1 /axi_i2s_adi/data_clk_i 
    connect_bd_intf_net /i2s /axi_i2s_adi/i2s 
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In15 
    connect_bd_net /sys_concat_intc/In15 /axi_hdmi_dma/irq 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M05_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_clkgen/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M05_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_clkgen/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M05_AXI /axi_hdmi_clkgen/s_axi 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M06_ACLK 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M06_ARESETN 
    connect_bd_intf_net /axi_cpu_interconnect/M06_AXI /axi_hdmi_dma/s_axi 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M07_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_core/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M07_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_core/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M07_AXI /axi_hdmi_core/s_axi 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M08_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_spdif_tx_core/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M08_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_spdif_tx_core/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M08_AXI /axi_spdif_tx_core/s_axi 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M09_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_i2s_adi/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M09_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_i2s_adi/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M09_AXI /axi_i2s_adi/s_axi 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    connect_bd_net -net /sys_cpu_resetn /axi_hp0_interconnect/aresetn 
    connect_bd_net -net /sys_cpu_clk /axi_hp0_interconnect/aclk 
    connect_bd_intf_net /axi_hp0_interconnect/M00_AXI /sys_ps7/S_AXI_HP0 
    connect_bd_net -net /sys_cpu_clk /sys_ps7/S_AXI_HP0_ACLK 
    connect_bd_intf_net /axi_hp0_interconnect/S00_AXI /axi_hdmi_dma/m_src_axi 
    WARNING: [BD 5-230] No cells matched 'get_bd_cells /sys_mb' 
    WARNING: [BD 5-232] No interface pins matched 'get_bd_intf_pins -filter {NAME=~ *DLMB*} -of {}' 
    Slave segment </sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM> is being mapped into address space </axi_hdmi_dma/m_src_axi> at <0x0000_0000 [ 1G ]> 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M10_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_pz_xcvrlb/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M10_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_pz_xcvrlb/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M10_AXI /axi_pz_xcvrlb/s_axi 
    connect_bd_net /axi_pz_xcvrlb/ref_clk /gt_ref_clk_0 
    connect_bd_net /axi_pz_xcvrlb/rx_p /gt_rx_p 
    connect_bd_net /axi_pz_xcvrlb/rx_n /gt_rx_n 
    connect_bd_net /axi_pz_xcvrlb/tx_p /gt_tx_p 
    connect_bd_net /axi_pz_xcvrlb/tx_n /gt_tx_n 
    connect_bd_net /clk_0 /axi_gpreg/d_clk_0 
    connect_bd_net /clk_1 /axi_gpreg/d_clk_1 
    connect_bd_net /gt_ref_clk_1 /axi_gpreg/d_clk_2 
    connect_bd_net /gp_in_0 /axi_gpreg/up_gp_in_0 
    connect_bd_net /gp_in_1 /axi_gpreg/up_gp_in_1 
    connect_bd_net /gp_out_0 /axi_gpreg/up_gp_out_0 
    connect_bd_net /gp_out_1 /axi_gpreg/up_gp_out_1 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M11_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_gpreg/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M11_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_gpreg/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M11_AXI /axi_gpreg/s_axi 
    WARNING: [BD 5-230] No cells matched 'get_bd_cells ila_adc' 
    connect_bd_net /rx_clk_in_p /axi_ad9361/rx_clk_in_p 
    connect_bd_net /rx_clk_in_n /axi_ad9361/rx_clk_in_n 
    connect_bd_net /rx_frame_in_p /axi_ad9361/rx_frame_in_p 
    connect_bd_net /rx_frame_in_n /axi_ad9361/rx_frame_in_n 
    connect_bd_net /rx_data_in_p /axi_ad9361/rx_data_in_p 
    connect_bd_net /rx_data_in_n /axi_ad9361/rx_data_in_n 
    connect_bd_net /tx_clk_out_p /axi_ad9361/tx_clk_out_p 
    connect_bd_net /tx_clk_out_n /axi_ad9361/tx_clk_out_n 
    connect_bd_net /tx_frame_out_p /axi_ad9361/tx_frame_out_p 
    connect_bd_net /tx_frame_out_n /axi_ad9361/tx_frame_out_n 
    connect_bd_net /tx_data_out_p /axi_ad9361/tx_data_out_p 
    connect_bd_net /tx_data_out_n /axi_ad9361/tx_data_out_n 
    connect_bd_net -net /sys_cpu_clk /sys_cpu_clk_out 
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd>  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [#UNDEF] When using EMIO pins for SPI_0 tie SSIN High in the PL bitstream 
    WARNING: [#UNDEF] When using EMIO pins for SPI_1 tie SSIN High in the PL bitstream 
    WARNING: [BD 41-927] Following properties on pin /axi_sysid_0/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /rom_sys_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/delay_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK1  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/l_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_tdd_sync/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk_out have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	POLARITY=ACTIVE_HIGH  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_pack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	POLARITY=ACTIVE_HIGH  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_dac_upack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_hdmi_clkgen_0_clk_0  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_out_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_hdmi_core_0_hdmi_out_clk  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/vdma_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/spdif_data_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1  
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/dma_req_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/data_clk_i have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_tx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_rx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_pz_xcvrlb/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_gpreg/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    validate_bd_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 794.555 ; gain = 86.355 
    INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run. 
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd>  
    VHDL Output written to : E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/synth/system.v 
    VHDL Output written to : E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/sim/system.v 
    VHDL Output written to : E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/hdl/system_wrapper.v 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_ps7 . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_iic_main . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_concat_intc . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_rstgen . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_logic_inv . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_sysid_0 . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block rom_sys_0 . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block GND_1 . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/xbar . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361 . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_tdd_sync . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk_sel_concat . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk_sel . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk_reset . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_adc_fifo . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_adc_pack . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361_adc_dma . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361_dac_fifo . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_dac_upack . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361_dac_dma . 
    Exporting to file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/hw_handoff/system_axi_hp1_interconnect_0.hwh 
    Generated Block Design Tcl file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/hw_handoff/system_axi_hp1_interconnect_0_bd.tcl 
    Generated Hardware Definition File e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/synth/system_axi_hp1_interconnect_0.hwdef 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hp1_interconnect . 
    Exporting to file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/hw_handoff/system_axi_hp2_interconnect_0.hwh 
    Generated Block Design Tcl file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/hw_handoff/system_axi_hp2_interconnect_0_bd.tcl 
    Generated Hardware Definition File e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/synth/system_axi_hp2_interconnect_0.hwdef 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hp2_interconnect . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_rgmii . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_rgmii_rstgen . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hdmi_clkgen . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hdmi_core . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hdmi_dma . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_audio_clkgen . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_spdif_tx_core . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_i2s_adi . 
    Exporting to file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/hw_handoff/system_axi_hp0_interconnect_0.hwh 
    Generated Block Design Tcl file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/hw_handoff/system_axi_hp0_interconnect_0_bd.tcl 
    Generated Hardware Definition File e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/synth/system_axi_hp0_interconnect_0.hwdef 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hp0_interconnect . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_pz_xcvrlb . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpreg . 
    WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_pc_0/system_auto_pc_0_ooc.xdc' 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/s00_couplers/auto_pc . 
    Exporting to file E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/hw_handoff/system.hwh 
    Generated Block Design Tcl file E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl 
    Generated Hardware Definition File E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/synth/system.hwdef 
    generate_target: Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 1118.031 ; gain = 323.477 
    Skipping synthesis 
    Skipping 
    Preprocessing adrv9361z7035 ccfmc_lvds rxtx 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets util_ad9361_dac_upack_dac_data_0' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets util_ad9361_dac_upack_dac_data_1' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets util_ad9361_dac_upack_dac_data_2' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets util_ad9361_dac_upack_dac_data_3' 
    WARNING: [BD 41-597] NET <Net> has no source 
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd>  
    WARNING: [#UNDEF] When using EMIO pins for SPI_0 tie SSIN High in the PL bitstream 
    WARNING: [#UNDEF] When using EMIO pins for SPI_1 tie SSIN High in the PL bitstream 
    WARNING: [BD 41-927] Following properties on pin /axi_sysid_0/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /rom_sys_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/delay_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK1  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/l_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_tdd_sync/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk_out have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	POLARITY=ACTIVE_HIGH  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_pack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	POLARITY=ACTIVE_HIGH  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_dac_upack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_hdmi_clkgen_0_clk_0  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_out_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_hdmi_core_0_hdmi_out_clk  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/vdma_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/spdif_data_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1  
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/dma_req_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/data_clk_i have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_tx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_rx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_pz_xcvrlb/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_gpreg/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow. 
    Please check your design and connect them as needed:  
    /axi_ad9361_dac_fifo/din_valid_in_0 
    /axi_ad9361_dac_fifo/din_valid_in_1 
    /axi_ad9361_dac_fifo/din_valid_in_2 
    /axi_ad9361_dac_fifo/din_valid_in_3 
     
    validate_bd_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1127.777 ; gain = 9.746 
    WARNING: [BD 41-597] NET <Net> has no source 
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd>  
    INFO: [Common 17-206] Exiting Vivado at Sun Mar 20 11:43:36 2022... 
     
    ****** Vivado v2019.1 (64-bit) 
      **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 
      **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 
        ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
     
    source vivado_insert_ip.tcl -notrace 
    Scanning sources... 
    Finished scanning sources 
    WARNING: [filemgmt 56-3] IP Repository Path: Could not find the directory 'E:/hdl_prj/ghdl/library'. 
    INFO: [IP_Flow 19-234] Refreshing IP repositories 
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/ipcore'. 
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'. 
    WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/hdl_prj/ghdl/library'; Can't find the specified path. 
    If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. 
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2019.1/data/ip'. 
    open_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 334.457 ; gain = 30.418 
    INFO: [IP_Flow 19-949] Unzipped './ipcore/HDL_DUT_ip_v1_0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/ipcore'. 
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/ipcore' 
    INFO: [IP_Flow 19-1839] IP Catalog is up to date. 
    Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - sys_ps7 
    Adding component instance block -- xilinx.com:ip:axi_iic:2.0 - axi_iic_main 
    Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - sys_concat_intc 
    Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - sys_rstgen 
    Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - sys_logic_inv 
    Adding component instance block -- analog.com:user:axi_sysid:1.0 - axi_sysid_0 
    Adding component instance block -- analog.com:user:sysid_rom:1.0 - rom_sys_0 
    Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - GND_1 
    Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_cpu_interconnect 
    Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar 
    Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc 
    Adding component instance block -- analog.com:user:axi_ad9361:1.0 - axi_ad9361 
    Adding component instance block -- analog.com:user:util_tdd_sync:1.0 - util_ad9361_tdd_sync 
    Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - util_ad9361_divclk_sel_concat 
    Adding component instance block -- xilinx.com:ip:util_reduced_logic:2.0 - util_ad9361_divclk_sel 
    Adding component instance block -- analog.com:user:util_clkdiv:1.0 - util_ad9361_divclk 
    Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - util_ad9361_divclk_reset 
    Adding component instance block -- analog.com:user:util_wfifo:1.0 - util_ad9361_adc_fifo 
    Adding component instance block -- analog.com:user:util_cpack2:1.0 - util_ad9361_adc_pack 
    Adding component instance block -- analog.com:user:axi_dmac:1.0 - axi_ad9361_adc_dma 
    Adding component instance block -- analog.com:user:util_rfifo:1.0 - axi_ad9361_dac_fifo 
    Adding component instance block -- analog.com:user:util_upack2:1.0 - util_ad9361_dac_upack 
    Adding component instance block -- analog.com:user:axi_dmac:1.0 - axi_ad9361_dac_dma 
    Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_hp1_interconnect 
    Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_hp2_interconnect 
    Adding component instance block -- xilinx.com:ip:gmii_to_rgmii:4.0 - sys_rgmii 
    Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - sys_rgmii_rstgen 
    Adding component instance block -- analog.com:user:axi_clkgen:1.0 - axi_hdmi_clkgen 
    Adding component instance block -- analog.com:user:axi_hdmi_tx:1.0 - axi_hdmi_core 
    Adding component instance block -- analog.com:user:axi_dmac:1.0 - axi_hdmi_dma 
    Adding component instance block -- xilinx.com:ip:clk_wiz:6.0 - sys_audio_clkgen 
    Adding component instance block -- analog.com:user:axi_spdif_tx:1.0 - axi_spdif_tx_core 
    Adding component instance block -- analog.com:user:axi_i2s_adi:1.0 - axi_i2s_adi 
    Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_hp0_interconnect 
    Adding component instance block -- analog.com:user:axi_xcvrlb:1.0 - axi_pz_xcvrlb 
    Adding component instance block -- analog.com:user:axi_gpreg:1.0 - axi_gpreg 
    Successfully read diagram <system> from BD file <E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/system.bd> 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /gpio_status' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /gpio_ctl' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /util_ad9361_adc_pack/fifo_wr_en' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /util_ad9361_adc_pack/fifo_wr_data_0' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /util_ad9361_adc_pack/fifo_wr_data_1' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /util_ad9361_adc_fifo/dout_data_0' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /util_ad9361_adc_fifo/dout_data_1' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /axi_ad9361_dac_fifo/din_data_0' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /axi_ad9361_dac_fifo/din_data_1' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /util_ad9361_dac_upack/fifo_rd_data_0' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /util_ad9361_dac_upack/fifo_rd_data_1' 
    WARNING: [#UNDEF] When using EMIO pins for SPI_0 tie SSIN High in the PL bitstream 
    WARNING: [#UNDEF] When using EMIO pins for SPI_1 tie SSIN High in the PL bitstream 
    WARNING: [BD 41-927] Following properties on pin /axi_sysid_0/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /rom_sys_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/delay_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK1  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/l_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_tdd_sync/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk_out have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	POLARITY=ACTIVE_HIGH  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_pack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	POLARITY=ACTIVE_HIGH  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_dac_upack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_hdmi_clkgen_0_clk_0  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_out_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_hdmi_core_0_hdmi_out_clk  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/vdma_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/spdif_data_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1  
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/dma_req_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/data_clk_i have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_tx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_rx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_pz_xcvrlb/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_gpreg/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /HDL_DUT_ip_0/IPCORE_CLK have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /HDL_DUT_ip_0/AXI4_Lite_ACLK have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow. 
    Please check your design and connect them as needed:  
    /axi_ad9361_dac_fifo/din_valid_in_0 
    /axi_ad9361_dac_fifo/din_valid_in_1 
    /axi_ad9361_dac_fifo/din_valid_in_2 
    /axi_ad9361_dac_fifo/din_valid_in_3 
     
    validate_bd_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 515.043 ; gain = 106.250 
    WARNING: [BD 41-597] NET <Net> has no source 
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd>  
    INFO: [Common 17-206] Exiting Vivado at Sun Mar 20 11:43:58 2022... 
    ### Generating Xilinx Vivado with IP Integrator project: hdl_prj\vivado_ip_prj\vivado_prj.xpr
    ### Generated logfile: hdl_prj\hdlsrc\frequency_hopping\workflow_task_CreateProject.log
    ### Task "Create Project" successful.
    ### ++++++++++++++ Task Build FPGA Bitstream ++++++++++++++
    ### Build FPGA Bitstream
    >> hdlworkflow

    which says "Task Create Project successful." and started to Build FPGA Bitstream and then stopped without generate bitstream

    1- do this means the project has been built correctly ? if yes ? why still get error when     using HDL workflow?

    I tried to use Vivado to Synthesis and Implementation the project which was build by Matlab and finally get bitstream file with these warnings

    [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow. Please check your design and connect them as needed: /axi_ad9361_dac_fifo/din_valid_in_0 /axi_ad9361_dac_fifo/din_valid_in_1 /axi_ad9361_dac_fifo/din_valid_in_2 /axi_ad9361_dac_fifo/din_valid_in_3

    and the "Implementation log"

    *** Running vivado
        with args -log system_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source system_top.tcl -notrace
    
    
    ****** Vivado v2019.1 (64-bit)
      **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
      **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
        ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
    
    source system_top.tcl -notrace
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/ipcore'.
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'.
    WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/hdl_prj/ghdl/library'; Can't find the specified path.
    If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2019.1/data/ip'.
    Command: link_design -top system_top -part xc7z035ifbg676-2L
    Design is defaulting to srcset: sources_1
    Design is defaulting to constrset: constrs_1
    INFO: [Device 21-403] Loading part xc7z035ifbg676-2L
    INFO: [Netlist 29-17] Analyzing 2207 Unisim elements for replacement
    INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
    INFO: [Project 1-479] Netlist was created with Vivado 2019.1
    INFO: [Project 1-570] Preparing netlist for logic optimization
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_ps7_0/system_sys_ps7_0.xdc] for cell 'i_system_wrapper/system_i/sys_ps7/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_ps7_0/system_sys_ps7_0.xdc] for cell 'i_system_wrapper/system_i/sys_ps7/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_iic_main_0/system_axi_iic_main_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_iic_main/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_iic_main_0/system_axi_iic_main_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_iic_main/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/system_sys_rstgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_rstgen/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/system_sys_rstgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_rstgen/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/system_sys_rstgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_rstgen/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/system_sys_rstgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_rstgen/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/axi_ad9361_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/axi_ad9361_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_tdd_sync_0/util_tdd_sync_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_tdd_sync/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_tdd_sync_0/util_tdd_sync_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_tdd_sync/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_reset_0/system_util_ad9361_divclk_reset_0_board.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_divclk_reset/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_reset_0/system_util_ad9361_divclk_reset_0_board.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_divclk_reset/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_reset_0/system_util_ad9361_divclk_reset_0.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_divclk_reset/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_reset_0/system_util_ad9361_divclk_reset_0.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_divclk_reset/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_adc_fifo/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_adc_fifo/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_fifo_0/util_rfifo_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_fifo_0/util_rfifo_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_1/bd_31bd_psr_aclk_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/clk_map/psr_aclk/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_1/bd_31bd_psr_aclk_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/clk_map/psr_aclk/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_1/bd_31bd_psr_aclk_0.xdc] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/clk_map/psr_aclk/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_1/bd_31bd_psr_aclk_0.xdc] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/clk_map/psr_aclk/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_1/bd_c0fd_psr_aclk_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/clk_map/psr_aclk/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_1/bd_c0fd_psr_aclk_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/clk_map/psr_aclk/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_1/bd_c0fd_psr_aclk_0.xdc] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/clk_map/psr_aclk/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_1/bd_c0fd_psr_aclk_0.xdc] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/clk_map/psr_aclk/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_rstgen_0/system_sys_rgmii_rstgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii_rstgen/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_rstgen_0/system_sys_rgmii_rstgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii_rstgen/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_rstgen_0/system_sys_rgmii_rstgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii_rstgen/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_rstgen_0/system_sys_rgmii_rstgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii_rstgen/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hdmi_core_0/axi_hdmi_tx_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hdmi_core_0/axi_hdmi_tx_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_spdif_tx_core_0/axi_spdif_tx_constr.xdc] for cell 'i_system_wrapper/system_i/axi_spdif_tx_core/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_spdif_tx_core_0/axi_spdif_tx_constr.xdc] for cell 'i_system_wrapper/system_i/axi_spdif_tx_core/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_1/bd_a17c_psr_aclk_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/clk_map/psr_aclk/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_1/bd_a17c_psr_aclk_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/clk_map/psr_aclk/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_1/bd_a17c_psr_aclk_0.xdc] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/clk_map/psr_aclk/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_1/bd_a17c_psr_aclk_0.xdc] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/clk_map/psr_aclk/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_pz_xcvrlb_0/axi_xcvrlb_constr.xdc] for cell 'i_system_wrapper/system_i/axi_pz_xcvrlb/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_pz_xcvrlb_0/axi_xcvrlb_constr.xdc] for cell 'i_system_wrapper/system_i/axi_pz_xcvrlb/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc] for cell 'i_system_wrapper/system_i/axi_gpreg/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc] for cell 'i_system_wrapper/system_i/axi_gpreg/inst'
    Parsing XDC File [E:/hdl_prj/vivado_ip_prj/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc]
    Finished Parsing XDC File [E:/hdl_prj/vivado_ip_prj/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc]
    Parsing XDC File [E:/hdl_prj/vivado_ip_prj/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc]
    Finished Parsing XDC File [E:/hdl_prj/vivado_ip_prj/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc]
    Parsing XDC File [E:/hdl_prj/vivado_ip_prj/projects/adrv9361z7035/common/ccfmc_constr.xdc]
    Finished Parsing XDC File [E:/hdl_prj/vivado_ip_prj/projects/adrv9361z7035/common/ccfmc_constr.xdc]
    Parsing XDC File [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/ccfmc_constr.xdc]
    WARNING: [Constraints 18-619] A clock with name 'eth1_rgmii_rxclk' already exists, overwriting the previous clock with the same name. [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/ccfmc_constr.xdc:80]
    WARNING: [Constraints 18-619] A clock with name 'ref_clk_0' already exists, overwriting the previous clock with the same name. [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/ccfmc_constr.xdc:147]
    WARNING: [Constraints 18-619] A clock with name 'ref_clk_1' already exists, overwriting the previous clock with the same name. [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/ccfmc_constr.xdc:148]
    WARNING: [Constraints 18-619] A clock with name 'clk0' already exists, overwriting the previous clock with the same name. [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/ccfmc_constr.xdc:149]
    WARNING: [Constraints 18-619] A clock with name 'clk1' already exists, overwriting the previous clock with the same name. [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/ccfmc_constr.xdc:150]
    WARNING: [Constraints 18-619] A clock with name 'xcvr_clk_0' already exists, overwriting the previous clock with the same name. [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/ccfmc_constr.xdc:151]
    WARNING: [Constraints 18-619] A clock with name 'xcvr_clk_1' already exists, overwriting the previous clock with the same name. [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/ccfmc_constr.xdc:152]
    Finished Parsing XDC File [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/ccfmc_constr.xdc]
    Parsing XDC File [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc]
    Finished Parsing XDC File [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc]
    Parsing XDC File [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc]
    WARNING: [Constraints 18-619] A clock with name 'rx_clk' already exists, overwriting the previous clock with the same name. [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc:40]
    Finished Parsing XDC File [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc]
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/system_axi_ad9361_0_pps_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/system_axi_ad9361_0_pps_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_0/util_clkdiv_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_divclk/inst'
    INFO: [Timing 38-35] Done setting XDC timing constraints. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_0/util_clkdiv_constr.xdc:1]
    INFO: [Timing 38-2] Deriving generated clocks [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_0/util_clkdiv_constr.xdc:1]
    get_clocks: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1480.062 ; gain = 432.090
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_0/util_clkdiv_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_divclk/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_adc_dma_0/system_axi_ad9361_adc_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_adc_dma/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_adc_dma_0/system_axi_ad9361_adc_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_adc_dma/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_dma_0/system_axi_ad9361_dac_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_dac_dma/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_dma_0/system_axi_ad9361_dac_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_dac_dma/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii/U0'
    INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'system_sys_rgmii_0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:7]
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hdmi_dma_0/system_axi_hdmi_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_dma/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hdmi_dma_0/system_axi_hdmi_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_dma/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0_late.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0_late.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_i2s_adi_0/axi_i2s_adi_constr.xdc] for cell 'i_system_wrapper/system_i/axi_i2s_adi/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_i2s_adi_0/axi_i2s_adi_constr.xdc] for cell 'i_system_wrapper/system_i/axi_i2s_adi/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_gpreg_0/system_axi_gpreg_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_gpreg/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_gpreg_0/system_axi_gpreg_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_gpreg/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_cc_0/system_auto_cc_0_clocks.xdc] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst'
    WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_cc_0/system_auto_cc_0_clocks.xdc:7]
    WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-11' -to list should not be empty. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_cc_0/system_auto_cc_0_clocks.xdc:10]
    WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-15' -to list should not be empty. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_cc_0/system_auto_cc_0_clocks.xdc:13]
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_cc_0/system_auto_cc_0_clocks.xdc] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
    Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1480.062 ; gain = 0.000
    INFO: [Project 1-111] Unisim Transformation Summary:
      A total of 211 instances were transformed.
      IOBUF => IOBUF (IBUF, OBUFT): 34 instances
      OBUFDS => OBUFDS: 8 instances
      RAM16X1D => RAM32X1D (RAMD32, RAMD32): 9 instances
      RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 160 instances
    
    14 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered.
    link_design completed successfully
    link_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 1480.062 ; gain = 1118.965
    Command: opt_design
    Attempting to get a license for feature 'Implementation' and/or device 'xc7z035i'
    INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035i'
    Running DRC as a precondition to command opt_design
    
    Starting DRC Task
    INFO: [DRC 23-27] Running DRC with 2 threads
    INFO: [Project 1-461] DRC finished with 0 Errors
    INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
    
    Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.976 . Memory (MB): peak = 1480.062 ; gain = 0.000
    
    Starting Cache Timing Information Task
    INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'system_sys_rgmii_0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:7]
    INFO: [Timing 38-35] Done setting XDC timing constraints.
    Ending Cache Timing Information Task | Checksum: 204cd4a3f
    
    Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1480.062 ; gain = 0.000
    
    Starting Logic Optimization Task
    
    Phase 1 Retarget
    INFO: [Opt 31-138] Pushed 18 inverter(s) to 88 load pin(s).
    INFO: [Opt 31-49] Retargeted 0 cell(s).
    Phase 1 Retarget | Checksum: 17e959d1f
    
    Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1585.012 ; gain = 2.066
    INFO: [Opt 31-389] Phase Retarget created 399 cells and removed 1920 cells
    INFO: [Opt 31-1021] In phase Retarget, 25 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
    
    Phase 2 Constant propagation
    INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
    Phase 2 Constant propagation | Checksum: 1758217bf
    
    Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1585.012 ; gain = 2.066
    INFO: [Opt 31-389] Phase Constant propagation created 1192 cells and removed 1627 cells
    INFO: [Opt 31-1021] In phase Constant propagation, 38 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
    
    Phase 3 Sweep
    Phase 3 Sweep | Checksum: 23a54313e
    
    Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1585.012 ; gain = 2.066
    INFO: [Opt 31-389] Phase Sweep created 54 cells and removed 2587 cells
    INFO: [Opt 31-1021] In phase Sweep, 36 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
    
    Phase 4 BUFG optimization
    INFO: [Opt 31-274] Optimized connectivity to 1 cascaded buffer cells
    Phase 4 BUFG optimization | Checksum: 207f00a20
    
    Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1585.012 ; gain = 2.066
    INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 1 cells.
    
    Phase 5 Shift Register Optimization
    INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
    Phase 5 Shift Register Optimization | Checksum: 207f00a20
    
    Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1585.012 ; gain = 2.066
    INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
    
    Phase 6 Post Processing Netlist
    Phase 6 Post Processing Netlist | Checksum: 1839d5ee7
    
    Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1585.012 ; gain = 2.066
    INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
    INFO: [Opt 31-1021] In phase Post Processing Netlist, 21 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
    Opt_design Change Summary
    =========================
    
    
    -------------------------------------------------------------------------------------------------------------------------
    |  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
    -------------------------------------------------------------------------------------------------------------------------
    |  Retarget                     |             399  |            1920  |                                             25  |
    |  Constant propagation         |            1192  |            1627  |                                             38  |
    |  Sweep                        |              54  |            2587  |                                             36  |
    |  BUFG optimization            |               0  |               1  |                                              0  |
    |  Shift Register Optimization  |               0  |               0  |                                              0  |
    |  Post Processing Netlist      |               0  |               0  |                                             21  |
    -------------------------------------------------------------------------------------------------------------------------
    
    
    
    Starting Connectivity Check Task
    
    Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.082 . Memory (MB): peak = 1585.012 ; gain = 0.000
    Ending Logic Optimization Task | Checksum: 2c3ef65a7
    
    Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1585.012 ; gain = 2.066
    
    Starting Power Optimization Task
    INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
    INFO: [Pwropt 34-9] Applying IDT optimizations ...
    INFO: [Pwropt 34-10] Applying ODC optimizations ...
    INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'system_sys_rgmii_0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:7]
    INFO: [Timing 38-35] Done setting XDC timing constraints.
    INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.252 | TNS=0.000 |
    Running Vector-less Activity Propagation...
    
    Finished Running Vector-less Activity Propagation
    
    
    Starting PowerOpt Patch Enables Task
    INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 5 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
    INFO: [Pwropt 34-201] Structural ODC has moved 1 WE to EN ports
    Number of BRAM Ports augmented: 3 newly gated: 9 Total Ports: 10
    Ending PowerOpt Patch Enables Task | Checksum: 28b8914d2
    
    Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.300 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Ending Power Optimization Task | Checksum: 28b8914d2
    
    Time (s): cpu = 00:00:39 ; elapsed = 00:00:23 . Memory (MB): peak = 1939.199 ; gain = 354.188
    
    Starting Final Cleanup Task
    
    Starting Logic Optimization Task
    INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'system_sys_rgmii_0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:7]
    INFO: [Timing 38-35] Done setting XDC timing constraints.
    Ending Logic Optimization Task | Checksum: 20bb0e620
    
    Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Ending Final Cleanup Task | Checksum: 20bb0e620
    
    Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Starting Netlist Obfuscation Task
    Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Ending Netlist Obfuscation Task | Checksum: 20bb0e620
    
    Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [Common 17-83] Releasing license: Implementation
    46 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered.
    opt_design completed successfully
    opt_design: Time (s): cpu = 00:01:14 ; elapsed = 00:00:52 . Memory (MB): peak = 1939.199 ; gain = 459.137
    Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [Timing 38-480] Writing timing data to binary archive.
    Writing placer database...
    Writing XDEF routing.
    Writing XDEF routing logical nets.
    Writing XDEF routing special nets.
    Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.154 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [Common 17-1381] The checkpoint 'E:/hdl_prj/impl_1/system_top_opt.dcp' has been generated.
    write_checkpoint: Time (s): cpu = 00:00:21 ; elapsed = 00:00:15 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [runtcl-4] Executing : report_drc -file system_top_drc_opted.rpt -pb system_top_drc_opted.pb -rpx system_top_drc_opted.rpx
    Command: report_drc -file system_top_drc_opted.rpt -pb system_top_drc_opted.pb -rpx system_top_drc_opted.rpx
    INFO: [IP_Flow 19-1839] IP Catalog is up to date.
    INFO: [DRC 23-27] Running DRC with 2 threads
    INFO: [Coretcl 2-168] The results of DRC are in file E:/hdl_prj/impl_1/system_top_drc_opted.rpt.
    report_drc completed successfully
    report_drc: Time (s): cpu = 00:00:20 ; elapsed = 00:00:11 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Command: place_design
    Attempting to get a license for feature 'Implementation' and/or device 'xc7z035i'
    INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035i'
    INFO: [DRC 23-27] Running DRC with 2 threads
    INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
    INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
    Running DRC as a precondition to command place_design
    INFO: [DRC 23-27] Running DRC with 2 threads
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[10] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[4]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[6] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[0]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[7] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[1]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[8] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[2]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[9] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[3]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ENARDEN (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_ENARDEN_cooolgate_en_sig_5) which is driven by a register (i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_control/d_data_cntrl_int_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ENARDEN (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_ENARDEN_cooolgate_en_sig_5) which is driven by a register (i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_control/d_data_cntrl_int_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ENARDEN (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_ENARDEN_cooolgate_en_sig_5) which is driven by a register (i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_cntrl/d_data_cntrl_int_reg[18]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg/ADDRARDADDR[6] (net: i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/Q[0]) which is driven by a register (i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_raddr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg/ADDRARDADDR[7] (net: i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/Q[1]) which is driven by a register (i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_raddr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg/ADDRARDADDR[8] (net: i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/Q[2]) which is driven by a register (i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_raddr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg/ADDRARDADDR[9] (net: i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/Q[3]) which is driven by a register (i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_raddr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 12 Warnings
    INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
    
    Starting Placer Task
    INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
    
    Phase 1 Placer Initialization
    
    Phase 1.1 Placer Initialization Netlist Sorting
    Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 13f1702b7
    
    Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
    INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'system_sys_rgmii_0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:7]
    INFO: [Timing 38-35] Done setting XDC timing constraints.
    Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12ed536df
    
    Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 1.3 Build Placer Netlist Model
    Phase 1.3 Build Placer Netlist Model | Checksum: 1a2f8e50e
    
    Time (s): cpu = 00:00:48 ; elapsed = 00:00:34 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 1.4 Constrain Clocks/Macros
    Phase 1.4 Constrain Clocks/Macros | Checksum: 1a2f8e50e
    
    Time (s): cpu = 00:00:48 ; elapsed = 00:00:35 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Phase 1 Placer Initialization | Checksum: 1a2f8e50e
    
    Time (s): cpu = 00:00:48 ; elapsed = 00:00:35 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 2 Global Placement
    
    Phase 2.1 Floorplanning
    Phase 2.1 Floorplanning | Checksum: 1b742d44a
    
    Time (s): cpu = 00:00:55 ; elapsed = 00:00:38 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 2.2 Global Placement Core
    
    Phase 2.2.1 Physical Synthesis In Placer
    INFO: [Physopt 32-65] No nets found for high-fanout optimization.
    INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
    INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
    INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
    INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
    INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
    INFO: [Physopt 32-949] No candidate nets found for HD net replication
    INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
    Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Summary of Physical Synthesis Optimizations
    ============================================
    
    
    ----------------------------------------------------------------------------------------------------------------------------------------
    |  Optimization                  |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
    ----------------------------------------------------------------------------------------------------------------------------------------
    |  Very High Fanout              |            0  |              0  |                     0  |           0  |           1  |  00:00:01  |
    |  DSP Register                  |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
    |  Shift Register                |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
    |  BRAM Register                 |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
    |  HD Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
    |  Total                         |            0  |              0  |                     0  |           0  |           2  |  00:00:01  |
    ----------------------------------------------------------------------------------------------------------------------------------------
    
    
    Phase 2.2.1 Physical Synthesis In Placer | Checksum: 22eba26e8
    
    Time (s): cpu = 00:02:00 ; elapsed = 00:01:18 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Phase 2.2 Global Placement Core | Checksum: 15738f48b
    
    Time (s): cpu = 00:02:03 ; elapsed = 00:01:20 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Phase 2 Global Placement | Checksum: 15738f48b
    
    Time (s): cpu = 00:02:03 ; elapsed = 00:01:20 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 3 Detail Placement
    
    Phase 3.1 Commit Multi Column Macros
    Phase 3.1 Commit Multi Column Macros | Checksum: 1563c516f
    
    Time (s): cpu = 00:02:10 ; elapsed = 00:01:25 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 3.2 Commit Most Macros & LUTRAMs
    Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1dd7f9334
    
    Time (s): cpu = 00:02:23 ; elapsed = 00:01:34 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 3.3 Area Swap Optimization
    Phase 3.3 Area Swap Optimization | Checksum: 1776367ab
    
    Time (s): cpu = 00:02:24 ; elapsed = 00:01:35 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 3.4 Pipeline Register Optimization
    Phase 3.4 Pipeline Register Optimization | Checksum: 23d73fb3e
    
    Time (s): cpu = 00:02:24 ; elapsed = 00:01:35 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 3.5 Small Shape Detail Placement
    Phase 3.5 Small Shape Detail Placement | Checksum: 211e28462
    
    Time (s): cpu = 00:02:37 ; elapsed = 00:01:47 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 3.6 Re-assign LUT pins
    Phase 3.6 Re-assign LUT pins | Checksum: 19ef796d3
    
    Time (s): cpu = 00:02:40 ; elapsed = 00:01:51 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 3.7 Pipeline Register Optimization
    Phase 3.7 Pipeline Register Optimization | Checksum: c0303eb0
    
    Time (s): cpu = 00:02:41 ; elapsed = 00:01:51 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Phase 3 Detail Placement | Checksum: c0303eb0
    
    Time (s): cpu = 00:02:41 ; elapsed = 00:01:52 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 4 Post Placement Optimization and Clean-Up
    
    Phase 4.1 Post Commit Optimization
    INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'system_sys_rgmii_0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:7]
    INFO: [Timing 38-35] Done setting XDC timing constraints.
    
    Phase 4.1.1 Post Placement Optimization
    Post Placement Optimization Initialization | Checksum: 111d59b6c
    
    Phase 4.1.1.1 BUFG Insertion
    INFO: [Place 46-33] Processed net i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_0/i_up_dac_channel/i_xfer_cntrl/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N, BUFG insertion was skipped due to placement/routing conflicts.
    INFO: [Place 46-33] Processed net i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_cntrl/d_data_cntrl_int_reg[0]_0[0], BUFG insertion was skipped due to placement/routing conflicts.
    INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
    Phase 4.1.1.1 BUFG Insertion | Checksum: 111d59b6c
    
    Time (s): cpu = 00:03:04 ; elapsed = 00:02:07 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [Place 30-746] Post Placement Timing Summary WNS=0.739. For the most accurate timing information please run report_timing.
    Phase 4.1.1 Post Placement Optimization | Checksum: 1ed4c3f65
    
    Time (s): cpu = 00:03:04 ; elapsed = 00:02:07 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Phase 4.1 Post Commit Optimization | Checksum: 1ed4c3f65
    
    Time (s): cpu = 00:03:05 ; elapsed = 00:02:08 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 4.2 Post Placement Cleanup
    Phase 4.2 Post Placement Cleanup | Checksum: 1ed4c3f65
    
    Time (s): cpu = 00:03:05 ; elapsed = 00:02:08 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 4.3 Placer Reporting
    Phase 4.3 Placer Reporting | Checksum: 1ed4c3f65
    
    Time (s): cpu = 00:03:06 ; elapsed = 00:02:09 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 4.4 Final Placement Cleanup
    Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Phase 4.4 Final Placement Cleanup | Checksum: 12e033fc6
    
    Time (s): cpu = 00:03:06 ; elapsed = 00:02:09 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Phase 4 Post Placement Optimization and Clean-Up | Checksum: 12e033fc6
    
    Time (s): cpu = 00:03:07 ; elapsed = 00:02:09 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Ending Placer Task | Checksum: 3c5a3892
    
    Time (s): cpu = 00:03:07 ; elapsed = 00:02:09 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [Common 17-83] Releasing license: Implementation
    77 Infos, 24 Warnings, 0 Critical Warnings and 0 Errors encountered.
    place_design completed successfully
    place_design: Time (s): cpu = 00:03:16 ; elapsed = 00:02:15 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [Timing 38-480] Writing timing data to binary archive.
    Writing placer database...
    Writing XDEF routing.
    Writing XDEF routing logical nets.
    Writing XDEF routing special nets.
    Write XDEF Complete: Time (s): cpu = 00:00:13 ; elapsed = 00:00:04 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [Common 17-1381] The checkpoint 'E:/hdl_prj/impl_1/system_top_placed.dcp' has been generated.
    write_checkpoint: Time (s): cpu = 00:00:26 ; elapsed = 00:00:17 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [runtcl-4] Executing : report_io -file system_top_io_placed.rpt
    report_io: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.336 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [runtcl-4] Executing : report_utilization -file system_top_utilization_placed.rpt -pb system_top_utilization_placed.pb
    INFO: [runtcl-4] Executing : report_control_sets -verbose -file system_top_control_sets_placed.rpt
    report_control_sets: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Command: route_design
    Attempting to get a license for feature 'Implementation' and/or device 'xc7z035i'
    INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035i'
    Running DRC as a precondition to command route_design
    INFO: [DRC 23-27] Running DRC with 2 threads
    INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
    INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
    
    
    Starting Routing Task
    INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
    Checksum: PlaceDB: 1363261c ConstDB: 0 ShapeSum: 28f71276 RouteDB: 0
    
    Phase 1 Build RT Design
    Phase 1 Build RT Design | Checksum: dc0f5857
    
    Time (s): cpu = 00:02:28 ; elapsed = 00:02:02 . Memory (MB): peak = 2082.473 ; gain = 143.273
    Post Restoration Checksum: NetGraph: 1b6ba7bf NumContArr: c0a3b098 Constraints: 0 Timing: 0
    
    Phase 2 Router Initialization
    
    Phase 2.1 Create Timer
    Phase 2.1 Create Timer | Checksum: dc0f5857
    
    Time (s): cpu = 00:02:29 ; elapsed = 00:02:03 . Memory (MB): peak = 2110.137 ; gain = 170.938
    
    Phase 2.2 Fix Topology Constraints
    Phase 2.2 Fix Topology Constraints | Checksum: dc0f5857
    
    Time (s): cpu = 00:02:30 ; elapsed = 00:02:04 . Memory (MB): peak = 2123.469 ; gain = 184.270
    
    Phase 2.3 Pre Route Cleanup
    Phase 2.3 Pre Route Cleanup | Checksum: dc0f5857
    
    Time (s): cpu = 00:02:30 ; elapsed = 00:02:04 . Memory (MB): peak = 2123.469 ; gain = 184.270
     Number of Nodes with overlaps = 0
    
    Phase 2.4 Update Timing
    Phase 2.4 Update Timing | Checksum: 1c4f965d0
    
    Time (s): cpu = 00:03:06 ; elapsed = 00:02:30 . Memory (MB): peak = 2267.762 ; gain = 328.562
    INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.547  | TNS=0.000  | WHS=-0.892 | THS=-2142.533|
    
    
    Phase 2.5 Update Timing for Bus Skew
    
    Phase 2.5.1 Update Timing
    Phase 2.5.1 Update Timing | Checksum: 1b71bcd37
    
    Time (s): cpu = 00:03:27 ; elapsed = 00:02:42 . Memory (MB): peak = 2323.766 ; gain = 384.566
    INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.547  | TNS=0.000  | WHS=N/A    | THS=N/A    |
    
    Phase 2.5 Update Timing for Bus Skew | Checksum: 11fb50c5a
    
    Time (s): cpu = 00:03:28 ; elapsed = 00:02:43 . Memory (MB): peak = 2323.766 ; gain = 384.566
    Phase 2 Router Initialization | Checksum: 15e9c07fc
    
    Time (s): cpu = 00:03:28 ; elapsed = 00:02:43 . Memory (MB): peak = 2323.766 ; gain = 384.566
    
    Router Utilization Summary
      Global Vertical Routing Utilization    = 0 %
      Global Horizontal Routing Utilization  = 0 %
      Routable Net Status*
      *Does not include unroutable nets such as driverless and loadless.
      Run report_route_status for detailed report.
      Number of Failed Nets               = 34036
        (Failed Nets is the sum of unrouted and partially routed nets)
      Number of Unrouted Nets             = 34035
      Number of Partially Routed Nets     = 1
      Number of Node Overlaps             = 0
    
    
    Phase 3 Initial Routing
    Phase 3 Initial Routing | Checksum: fe396d7b
    
    Time (s): cpu = 00:03:42 ; elapsed = 00:02:51 . Memory (MB): peak = 2328.023 ; gain = 388.824
    
    Phase 4 Rip-up And Reroute
    
    Phase 4.1 Global Iteration 0
     Number of Nodes with overlaps = 2001
     Number of Nodes with overlaps = 113
     Number of Nodes with overlaps = 0
    INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.547  | TNS=0.000  | WHS=N/A    | THS=N/A    |
    
    Phase 4.1 Global Iteration 0 | Checksum: 2718294a8
    
    Time (s): cpu = 00:04:07 ; elapsed = 00:03:07 . Memory (MB): peak = 2328.023 ; gain = 388.824
    Phase 4 Rip-up And Reroute | Checksum: 2718294a8
    
    Time (s): cpu = 00:04:07 ; elapsed = 00:03:07 . Memory (MB): peak = 2328.023 ; gain = 388.824
    
    Phase 5 Delay and Skew Optimization
    
    Phase 5.1 Delay CleanUp
    
    Phase 5.1.1 Update Timing
    Phase 5.1.1 Update Timing | Checksum: 1ddda4f83
    
    Time (s): cpu = 00:04:12 ; elapsed = 00:03:10 . Memory (MB): peak = 2328.023 ; gain = 388.824
    INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.724  | TNS=0.000  | WHS=N/A    | THS=N/A    |
    
    Phase 5.1 Delay CleanUp | Checksum: 287824a04
    
    Time (s): cpu = 00:04:12 ; elapsed = 00:03:10 . Memory (MB): peak = 2328.023 ; gain = 388.824
    
    Phase 5.2 Clock Skew Optimization
    Phase 5.2 Clock Skew Optimization | Checksum: 287824a04
    
    Time (s): cpu = 00:04:13 ; elapsed = 00:03:10 . Memory (MB): peak = 2328.023 ; gain = 388.824
    Phase 5 Delay and Skew Optimization | Checksum: 287824a04
    
    Time (s): cpu = 00:04:13 ; elapsed = 00:03:11 . Memory (MB): peak = 2328.023 ; gain = 388.824
    
    Phase 6 Post Hold Fix
    
    Phase 6.1 Hold Fix Iter
    
    Phase 6.1.1 Update Timing
    Phase 6.1.1 Update Timing | Checksum: 24538e98c
    
    Time (s): cpu = 00:04:19 ; elapsed = 00:03:14 . Memory (MB): peak = 2328.023 ; gain = 388.824
    INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.213  | TNS=0.000  | WHS=0.045  | THS=0.000  |
    
    Phase 6.1 Hold Fix Iter | Checksum: 27c91f1b9
    
    Time (s): cpu = 00:04:19 ; elapsed = 00:03:14 . Memory (MB): peak = 2328.023 ; gain = 388.824
    Phase 6 Post Hold Fix | Checksum: 27c91f1b9
    
    Time (s): cpu = 00:04:19 ; elapsed = 00:03:14 . Memory (MB): peak = 2328.023 ; gain = 388.824
    
    Phase 7 Route finalize
    
    Router Utilization Summary
      Global Vertical Routing Utilization    = 2.00144 %
      Global Horizontal Routing Utilization  = 2.43422 %
      Routable Net Status*
      *Does not include unroutable nets such as driverless and loadless.
      Run report_route_status for detailed report.
      Number of Failed Nets               = 0
        (Failed Nets is the sum of unrouted and partially routed nets)
      Number of Unrouted Nets             = 0
      Number of Partially Routed Nets     = 0
      Number of Node Overlaps             = 0
    
    Phase 7 Route finalize | Checksum: 2a51a3bf0
    
    Time (s): cpu = 00:04:20 ; elapsed = 00:03:15 . Memory (MB): peak = 2328.023 ; gain = 388.824
    
    Phase 8 Verifying routed nets
    
     Verification completed successfully
    Phase 8 Verifying routed nets | Checksum: 2a51a3bf0
    
    Time (s): cpu = 00:04:20 ; elapsed = 00:03:15 . Memory (MB): peak = 2328.023 ; gain = 388.824
    
    Phase 9 Depositing Routes
    INFO: [Route 35-467] Router swapped GT pin i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[1].i_xcvrlb_1/i_xch/i_gtxe2_channel/GTREFCLK0 to physical pin GTXE2_CHANNEL_X0Y9/GTSOUTHREFCLK1
    Phase 9 Depositing Routes | Checksum: 2b2d65d89
    
    Time (s): cpu = 00:04:25 ; elapsed = 00:03:20 . Memory (MB): peak = 2328.023 ; gain = 388.824
    
    Phase 10 Post Router Timing
    INFO: [Route 35-57] Estimated Timing Summary | WNS=0.213  | TNS=0.000  | WHS=0.045  | THS=0.000  |
    
    INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
    Phase 10 Post Router Timing | Checksum: 2b2d65d89
    
    Time (s): cpu = 00:04:25 ; elapsed = 00:03:21 . Memory (MB): peak = 2328.023 ; gain = 388.824
    INFO: [Route 35-16] Router Completed Successfully
    
    Time (s): cpu = 00:04:25 ; elapsed = 00:03:21 . Memory (MB): peak = 2328.023 ; gain = 388.824
    
    Routing Is Done.
    INFO: [Common 17-83] Releasing license: Implementation
    97 Infos, 24 Warnings, 0 Critical Warnings and 0 Errors encountered.
    route_design completed successfully
    route_design: Time (s): cpu = 00:04:36 ; elapsed = 00:03:27 . Memory (MB): peak = 2328.023 ; gain = 388.824
    Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 2328.023 ; gain = 0.000
    INFO: [Timing 38-480] Writing timing data to binary archive.
    Writing placer database...
    Writing XDEF routing.
    Writing XDEF routing logical nets.
    Writing XDEF routing special nets.
    Write XDEF Complete: Time (s): cpu = 00:00:17 ; elapsed = 00:00:06 . Memory (MB): peak = 2328.023 ; gain = 0.000
    INFO: [Common 17-1381] The checkpoint 'E:/hdl_prj/impl_1/system_top_routed.dcp' has been generated.
    write_checkpoint: Time (s): cpu = 00:00:29 ; elapsed = 00:00:18 . Memory (MB): peak = 2328.023 ; gain = 0.000
    INFO: [runtcl-4] Executing : report_drc -file system_top_drc_routed.rpt -pb system_top_drc_routed.pb -rpx system_top_drc_routed.rpx
    Command: report_drc -file system_top_drc_routed.rpt -pb system_top_drc_routed.pb -rpx system_top_drc_routed.rpx
    INFO: [IP_Flow 19-1839] IP Catalog is up to date.
    INFO: [DRC 23-27] Running DRC with 2 threads
    INFO: [Coretcl 2-168] The results of DRC are in file E:/hdl_prj/impl_1/system_top_drc_routed.rpt.
    report_drc completed successfully
    report_drc: Time (s): cpu = 00:00:27 ; elapsed = 00:00:16 . Memory (MB): peak = 2328.023 ; gain = 0.000
    INFO: [runtcl-4] Executing : report_methodology -file system_top_methodology_drc_routed.rpt -pb system_top_methodology_drc_routed.pb -rpx system_top_methodology_drc_routed.rpx
    Command: report_methodology -file system_top_methodology_drc_routed.rpt -pb system_top_methodology_drc_routed.pb -rpx system_top_methodology_drc_routed.rpx
    INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'system_sys_rgmii_0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:7]
    INFO: [Timing 38-35] Done setting XDC timing constraints.
    INFO: [DRC 23-133] Running Methodology with 2 threads
    INFO: [Coretcl 2-1520] The results of Report Methodology are in file E:/hdl_prj/impl_1/system_top_methodology_drc_routed.rpt.
    report_methodology completed successfully
    report_methodology: Time (s): cpu = 00:00:45 ; elapsed = 00:00:25 . Memory (MB): peak = 2412.891 ; gain = 84.867
    INFO: [runtcl-4] Executing : report_power -file system_top_power_routed.rpt -pb system_top_power_summary_routed.pb -rpx system_top_power_routed.rpx
    Command: report_power -file system_top_power_routed.rpt -pb system_top_power_summary_routed.pb -rpx system_top_power_routed.rpx
    INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'system_sys_rgmii_0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:7]
    INFO: [Timing 38-35] Done setting XDC timing constraints.
    Running Vector-less Activity Propagation...
    
    Finished Running Vector-less Activity Propagation
    WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
    Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
    111 Infos, 25 Warnings, 0 Critical Warnings and 0 Errors encountered.
    report_power completed successfully
    report_power: Time (s): cpu = 00:00:37 ; elapsed = 00:00:21 . Memory (MB): peak = 2415.055 ; gain = 2.164
    INFO: [runtcl-4] Executing : report_route_status -file system_top_route_status.rpt -pb system_top_route_status.pb
    INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file system_top_timing_summary_routed.rpt -pb system_top_timing_summary_routed.pb -rpx system_top_timing_summary_routed.rpx -warn_on_violation 
    INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
    INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
    WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
    INFO: [runtcl-4] Executing : report_incremental_reuse -file system_top_incremental_reuse_routed.rpt
    INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
    INFO: [runtcl-4] Executing : report_clock_utilization -file system_top_clock_utilization_routed.rpt
    INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file system_top_bus_skew_routed.rpt -pb system_top_bus_skew_routed.pb -rpx system_top_bus_skew_routed.rpx
    INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
    INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
    INFO: [Memdata 28-167] Found XPM memory block i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
    INFO: [Memdata 28-167] Found XPM memory block i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
    INFO: [Memdata 28-167] Found XPM memory block i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
    INFO: [Memdata 28-167] Found XPM memory block i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
    INFO: [Memdata 28-167] Found XPM memory block i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
    INFO: [Memdata 28-167] Found XPM memory block i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
    Command: write_bitstream -force system_top.bit
    Attempting to get a license for feature 'Implementation' and/or device 'xc7z035i'
    INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035i'
    Running DRC as a precondition to command write_bitstream
    INFO: [IP_Flow 19-1839] IP Catalog is up to date.
    INFO: [DRC 23-27] Running DRC with 2 threads
    WARNING: [DRC REQP-1577] Clock output buffering: MMCME2_ADV connectivity violation. The signal i_system_wrapper/system_i/sys_rgmii/U0/i_system_sys_rgmii_0_clocking/clk_10 on the i_system_wrapper/system_i/sys_rgmii/U0/i_system_sys_rgmii_0_clocking/mmcm_adv_inst/CLKOUT2 pin of i_system_wrapper/system_i/sys_rgmii/U0/i_system_sys_rgmii_0_clocking/mmcm_adv_inst does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[10] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[4]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[6] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[0]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[7] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[1]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[8] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[2]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[9] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[3]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ENARDEN (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_ENARDEN_cooolgate_en_sig_5) which is driven by a register (i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_control/d_data_cntrl_int_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ENARDEN (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_ENARDEN_cooolgate_en_sig_5) which is driven by a register (i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_control/d_data_cntrl_int_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ENARDEN (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_ENARDEN_cooolgate_en_sig_5) which is driven by a register (i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_cntrl/d_data_cntrl_int_reg[18]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg/ADDRARDADDR[6] (net: i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/Q[0]) which is driven by a register (i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_raddr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg/ADDRARDADDR[7] (net: i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/Q[1]) which is driven by a register (i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_raddr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg/ADDRARDADDR[8] (net: i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/Q[2]) which is driven by a register (i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_raddr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg/ADDRARDADDR[9] (net: i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/Q[3]) which is driven by a register (i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_raddr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_ad_iqcor/g_loop[0].i_mul_i/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_ad_iqcor/g_loop[0].i_mul_q/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_ad_iqcor/g_loop[0].i_mul_i/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_ad_iqcor/g_loop[0].i_mul_q/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_ad_iqcor/g_loop[0].i_mul_i/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_ad_iqcor/g_loop[0].i_mul_q/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_ad_iqcor/g_loop[0].i_mul_i/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_ad_iqcor/g_loop[0].i_mul_q/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_0/i_ad_iqcor/g_loop[0].i_mul_i/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_0/i_ad_iqcor/g_loop[0].i_mul_q/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_0/i_dds/dds_phase[1].i_dds_2/i_dds_1_0/i_dds_scale/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_0/i_dds/dds_phase[1].i_dds_2/i_dds_1_1/i_dds_scale/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_1/i_ad_iqcor/g_loop[0].i_mul_i/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_1/i_ad_iqcor/g_loop[0].i_mul_q/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_1/i_dds/dds_phase[1].i_dds_2/i_dds_1_0/i_dds_scale/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_1/i_dds/dds_phase[1].i_dds_2/i_dds_1_1/i_dds_scale/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_2/i_ad_iqcor/g_loop[0].i_mul_i/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_2/i_ad_iqcor/g_loop[0].i_mul_q/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_2/i_dds/dds_phase[1].i_dds_2/i_dds_1_0/i_dds_scale/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_2/i_dds/dds_phase[1].i_dds_2/i_dds_1_1/i_dds_scale/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_3/i_ad_iqcor/g_loop[0].i_mul_i/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_3/i_ad_iqcor/g_loop[0].i_mul_q/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_3/i_dds/dds_phase[1].i_dds_2/i_dds_1_0/i_dds_scale/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_3/i_dds/dds_phase[1].i_dds_2/i_dds_1_1/i_dds_scale/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (i_system_wrapper/system_i/axi_hdmi_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_mem/m_ram_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
    INFO: [Vivado 12-3199] DRC finished with 0 Errors, 13 Warnings, 25 Advisories
    INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
    INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
    Loading data files...
    Loading site data...
    Loading route data...
    Processing options...
    Creating bitmap...
    Creating bitstream...
    Writing bitstream ./system_top.bit...
    INFO: [Vivado 12-1842] Bitgen Completed Successfully.
    INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.).
    INFO: [Common 17-186] 'E:/hdl_prj/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Sun Mar 20 12:05:07 2022. For additional details about this file, please refer to the WebTalk help file at E:/Xilinx/Vivado/2019.1/doc/webtalk_introduction.html.
    INFO: [Common 17-83] Releasing license: Implementation
    162 Infos, 39 Warnings, 0 Critical Warnings and 0 Errors encountered.
    write_bitstream completed successfully
    write_bitstream: Time (s): cpu = 00:01:38 ; elapsed = 00:01:19 . Memory (MB): peak = 2848.449 ; gain = 429.000
    INFO: [Common 17-206] Exiting Vivado at Sun Mar 20 12:05:07 2022...
    

    2- Is the generated File"/system_top.bit" the right one?

    3- Could I use it  to build BOOT.BIN using Vivado BOOTGEN tool

    thank you for you patient

    and sorry for prolongation

    Regards

Reply
  • Hello

    I repeated HDL workflow with a NEW destination folder to make sure there is no any influence from previous attempts. but still i got the same previous errors  

    ERROR: [BD 41-701] connect_bd_net requires at least two pins/ports, or one pin/port and a net
    ERROR: [BD 5-4] Error: running connect_bd_net.
    ERROR: [Common 17-39] 'connect_bd_net' failed due to earlier errors.

    with the same previous log.

    I tried to run "frequency-hopping/hdlworkflow.m"  i got this log file

    >> hdlworkflow
    ### Workflow begin.
    ### Loading settings from model.
    ### Model compilation and PIR creation begin.
    ### Generating HDL for 'frequency_hopping/HDL_DUT'.
    ### Using the config set for model frequency_hopping for HDL code generation parameters.
    ### Running HDL checks on the model 'frequency_hopping'.
    ### Begin compilation of the model 'frequency_hopping'...
    ### Failure to initialize the model frequency_hopping.
    ### Creating HDL Code Generation Check Report HDL_DUT_ip_src_HDL_DUT_report.html
    ### HDL check for 'frequency_hopping' complete with 1 errors, 0 warnings, and 0 messages.
    ### HDL check for 'frequency_hopping' complete with 1 errors, 0 warnings, and 0 messages.
    >> hdlworkflow
    ### Workflow begin.
    ### Loading settings from model.
    ### Model compilation and PIR creation begin.
    ### Generating HDL for 'frequency_hopping/HDL_DUT'.
    ### Using the config set for model frequency_hopping for HDL code generation parameters.
    ### Running HDL checks on the model 'frequency_hopping'.
    ### Begin compilation of the model 'frequency_hopping'...
    ### Model compilation and PIR creation complete.
    Warning: Interface is not assigned to model port 'TxDMAEnable'. 
    > In downstream.tool.displayValidateCell
    In downstream.DownstreamIntegrationDriver/validateTargetInterface
    In hwcli.runWorkflow
    In hdlcoder.runWorkflow (line 27)
    In hdlworkflow (line 172) 
    ### ++++++++++++++ Task Generate RTL Code and IP Core ++++++++++++++
    ### Generate RTL Code and IP Core
    ### Applying HDL optimizations on the model 'frequency_hopping'...
    ### 'LUTMapToRAM' is set to 'On' for the model. This option is used to map lookup tables to a block RAM in hardware.  To disable pipeline insertion for mapping lookup tables to RAM, set the option to 'Off'.
    ### Begin model generation.
    ### Model generation complete.
    ### Begin Verilog Code Generation for 'frequency_hopping'.
    ### Working on frequency_hopping/HDL_DUT/DEBUG as hdl_prj\hdlsrc\frequency_hopping\HDL_DUT_ip_src_DEBUG.v.
    ### Working on frequency_hopping/HDL_DUT/Enable Control as hdl_prj\hdlsrc\frequency_hopping\HDL_DUT_ip_src_Enable_Control.v.
    ### Working on frequency_hopping/HDL_DUT as hdl_prj\hdlsrc\frequency_hopping\HDL_DUT_ip_src_HDL_DUT.v.
    ### Code Generation for 'frequency_hopping' completed.
    ### Generating HTML files for code generation report at frequency_hopping_codegen_rpt.html
    ### Creating HDL Code Generation Check Report HDL_DUT_ip_src_HDL_DUT_report.html
    ### HDL check for 'frequency_hopping' complete with 0 errors, 0 warnings, and 1 messages.
    ### HDL code generation complete.
    ### Begin IP core top level wrapper code generation.
    ### Begin Verilog Code Generation for 'frequency_hopping'.
    ### Working on HDL_DUT_ip/HDL_DUT_ip_reset_sync as hdl_prj\hdlsrc\frequency_hopping\HDL_DUT_ip_reset_sync.v.
    ### Working on HDL_DUT_ip/HDL_DUT_ip_dut as hdl_prj\hdlsrc\frequency_hopping\HDL_DUT_ip_dut.v.
    ### Working on HDL_DUT_ip/HDL_DUT_ip_axi_lite/HDL_DUT_ip_addr_decoder as hdl_prj\hdlsrc\frequency_hopping\HDL_DUT_ip_addr_decoder.v.
    ### Working on HDL_DUT_ip/HDL_DUT_ip_axi_lite/HDL_DUT_ip_axi_lite_module as hdl_prj\hdlsrc\frequency_hopping\HDL_DUT_ip_axi_lite_module.v.
    ### Working on HDL_DUT_ip/HDL_DUT_ip_axi_lite as hdl_prj\hdlsrc\frequency_hopping\HDL_DUT_ip_axi_lite.v.
    ### Working on HDL_DUT_ip as hdl_prj\hdlsrc\frequency_hopping\HDL_DUT_ip.v.
    ### Code Generation for 'frequency_hopping' completed.
    ### HDL code generation complete.
    ### Begin IP core packaging.
    ### Generating IP core report frequency_hopping_ip_core_report.html
     
    ****** Vivado v2019.1 (64-bit) 
      **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 
      **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 
        ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
     
    source vivado_ip_package.tcl -notrace 
    INFO: [IP_Flow 19-234] Refreshing IP repositories 
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/ipcore'. 
    WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'e:/hdl_prj/ipcore' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'e:/hdl_prj/ipcore/HDL_DUT_ip_v1_0/prj_ip'.) 
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2019.1/data/ip'. 
    INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). 
    INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite_ARESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). 
    INFO: [IP_Flow 19-5107] Inferred bus interface 'IPCORE_RESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). 
    INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite_ACLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). 
    INFO: [IP_Flow 19-5107] Inferred bus interface 'IPCORE_CLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). 
    INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ARESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. 
    INFO: [IP_Flow 19-4728] Bus Interface 'IPCORE_RESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. 
    INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ACLK': Added interface parameter 'ASSOCIATED_BUSIF' with value 'AXI4_Lite'. 
    INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'AXI4_Lite_ARESETN'. 
    INFO: [IP_Flow 19-4728] Bus Interface 'IPCORE_CLK': Added interface parameter 'ASSOCIATED_RESET' with value 'IPCORE_RESETN'. 
    WARNING: [IP_Flow 19-3153] Bus Interface 'IPCORE_CLK': ASSOCIATED_BUSIF bus parameter is missing. 
    INFO: [IP_Flow 19-2181] Payment Required is not set for this core. 
    INFO: [IP_Flow 19-2187] The Product Guide file is missing. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_DEBUG.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_DEBUG.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_Enable_Control.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_Enable_Control.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_HDL_DUT.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_HDL_DUT.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_reset_sync.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_reset_sync.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_dut.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_dut.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_addr_decoder.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_addr_decoder.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_axi_lite_module.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_axi_lite_module.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_axi_lite.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_axi_lite.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again. 
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again. 
    INFO: [Common 17-206] Exiting Vivado at Sun Mar 20 11:38:09 2022... 
    ### Generated logfile: hdl_prj\hdlsrc\frequency_hopping\workflow_task_VivadoIPPackager.log
    ### Task "Vivado IP Packager" successful.
    ### 
    ****** Vivado v2019.1 (64-bit)
      **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
      **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
        ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
    
    source vivado_ip_package.tcl -notrace
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/ipcore'.
    WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'e:/hdl_prj/ipcore' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'e:/hdl_prj/ipcore/HDL_DUT_ip_v1_0/prj_ip'.)
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2019.1/data/ip'.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
    INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite_ARESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
    INFO: [IP_Flow 19-5107] Inferred bus interface 'IPCORE_RESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
    INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite_ACLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
    INFO: [IP_Flow 19-5107] Inferred bus interface 'IPCORE_CLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
    INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ARESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
    INFO: [IP_Flow 19-4728] Bus Interface 'IPCORE_RESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
    INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ACLK': Added interface parameter 'ASSOCIATED_BUSIF' with value 'AXI4_Lite'.
    INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'AXI4_Lite_ARESETN'.
    INFO: [IP_Flow 19-4728] Bus Interface 'IPCORE_CLK': Added interface parameter 'ASSOCIATED_RESET' with value 'IPCORE_RESETN'.
    WARNING: [IP_Flow 19-3153] Bus Interface 'IPCORE_CLK': ASSOCIATED_BUSIF bus parameter is missing.
    INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
    INFO: [IP_Flow 19-2187] The Product Guide file is missing.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_DEBUG.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_DEBUG.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_Enable_Control.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_Enable_Control.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_HDL_DUT.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_src_HDL_DUT.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_reset_sync.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_reset_sync.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_dut.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_dut.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_addr_decoder.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_addr_decoder.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_axi_lite_module.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_axi_lite_module.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_axi_lite.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip_axi_lite.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    WARNING: [IP_Flow 19-1971] File named "hdl/verilog/HDL_DUT_ip.v" already exists in file group "xilinx_anylanguagebehavioralsimulation", cannot add it again.
    INFO: [Common 17-206] Exiting Vivado at Sun Mar 20 11:38:09 2022...
    
    Elapsed time is 9.4813 seconds.
    
    ### ++++++++++++++ Task Create Project ++++++++++++++
    ### Create Project
     
    ****** Vivado v2019.1 (64-bit) 
      **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 
      **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 
        ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
     
    source vivado_create_prj.tcl -notrace 
    INFO: [IP_Flow 19-234] Refreshing IP repositories 
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/ipcore'. 
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2019.1/data/ip'. 
    INFO: [IP_Flow 19-1839] IP Catalog is up to date. 
    Starting Transceiver Toolbox HDL build 
    Building: 
    - axi_ad9361 
    - axi_clkgen 
    - axi_dmac 
    - axi_gpreg 
    - axi_hdmi_tx 
    - axi_i2s_adi 
    - axi_spdif_tx 
    - axi_sysid 
    - sysid_rom 
    - util_pack/util_cpack2 
    - util_pack/util_upack2 
    - util_rfifo 
    - util_tdd_sync 
    - util_wfifo 
    - xilinx/axi_xcvrlb 
    - xilinx/util_clkdiv 
    Please wait, this might take a few minutes 
    - Done building axi_ad9361 
    - Done building axi_clkgen 
    - Done building util_cdc 
    - Done building util_axis_fifo 
    - Done building axi_dmac 
    - Done building axi_gpreg 
    - Done building axi_hdmi_tx 
    - Done building axi_i2s_adi 
    - Done building axi_spdif_tx 
    - Done building axi_sysid 
    - Done building sysid_rom 
    - Done building util_pack/util_cpack2 
    - Done building util_pack/util_upack2 
    - Done building util_rfifo 
    - Done building util_tdd_sync 
    - Done building util_wfifo 
    - Done building xilinx/axi_xcvrlb 
    - Done building xilinx/util_clkdiv 
    INFO: [IP_Flow 19-234] Refreshing IP repositories 
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/ipcore'. 
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'. 
    WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/hdl_prj/ghdl/library'; Can't find the specified path. 
    If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. 
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd>  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    create_bd_net sys_cpu_clk 
    connect_bd_net -net /sys_cpu_clk /sys_ps7/FCLK_CLK0 
    create_bd_net sys_200m_clk 
    connect_bd_net -net /sys_200m_clk /sys_ps7/FCLK_CLK1 
    create_bd_net sys_cpu_reset 
    connect_bd_net -net /sys_cpu_reset /sys_rstgen/peripheral_reset 
    create_bd_net sys_cpu_resetn 
    connect_bd_net -net /sys_cpu_resetn /sys_rstgen/peripheral_aresetn 
    connect_bd_net -net /sys_cpu_clk /sys_rstgen/slowest_sync_clk 
    connect_bd_net /sys_rstgen/ext_reset_in /sys_ps7/FCLK_RESET0_N 
    connect_bd_intf_net /ddr /sys_ps7/DDR 
    connect_bd_net /gpio_i /sys_ps7/GPIO_I 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/GPIO_I is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0 
    connect_bd_net /gpio_o /sys_ps7/GPIO_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/GPIO_O is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0 
    connect_bd_net /gpio_t /sys_ps7/GPIO_T 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/GPIO_T is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0 
    connect_bd_intf_net /fixed_io /sys_ps7/FIXED_IO 
    connect_bd_intf_net /iic_main /axi_iic_main/IIC 
    connect_bd_net /sys_logic_inv/Res /sys_ps7/USB0_VBUS_PWRFAULT 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/USB0_VBUS_PWRFAULT is being overridden by the user. This pin will not be connected as a part of interface connection USBIND_0 
    connect_bd_net /sys_logic_inv/Op1 /otg_vbusoc 
    connect_bd_net /spi0_csn_2_o /sys_ps7/SPI0_SS2_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS2_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0 
    connect_bd_net /spi0_csn_1_o /sys_ps7/SPI0_SS1_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS1_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0 
    connect_bd_net /spi0_csn_0_o /sys_ps7/SPI0_SS_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0 
    connect_bd_net /spi0_csn_i /sys_ps7/SPI0_SS_I 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0 
    connect_bd_net /spi0_clk_i /sys_ps7/SPI0_SCLK_I 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SCLK_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0 
    connect_bd_net /spi0_clk_o /sys_ps7/SPI0_SCLK_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SCLK_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0 
    connect_bd_net /spi0_sdo_i /sys_ps7/SPI0_MOSI_I 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_MOSI_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0 
    connect_bd_net /spi0_sdo_o /sys_ps7/SPI0_MOSI_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_MOSI_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0 
    connect_bd_net /spi0_sdi_i /sys_ps7/SPI0_MISO_I 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_MISO_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0 
    connect_bd_net /spi1_csn_2_o /sys_ps7/SPI1_SS2_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS2_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1 
    connect_bd_net /spi1_csn_1_o /sys_ps7/SPI1_SS1_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS1_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1 
    connect_bd_net /spi1_csn_0_o /sys_ps7/SPI1_SS_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1 
    connect_bd_net /spi1_csn_i /sys_ps7/SPI1_SS_I 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1 
    connect_bd_net /spi1_clk_i /sys_ps7/SPI1_SCLK_I 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SCLK_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1 
    connect_bd_net /spi1_clk_o /sys_ps7/SPI1_SCLK_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SCLK_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1 
    connect_bd_net /spi1_sdo_i /sys_ps7/SPI1_MOSI_I 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_MOSI_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1 
    connect_bd_net /spi1_sdo_o /sys_ps7/SPI1_MOSI_O 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_MOSI_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1 
    connect_bd_net /spi1_sdi_i /sys_ps7/SPI1_MISO_I 
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_MISO_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1 
    connect_bd_net /axi_sysid_0/rom_addr /rom_sys_0/rom_addr 
    connect_bd_net /axi_sysid_0/sys_rom_data /rom_sys_0/rom_data 
    connect_bd_net -net /sys_cpu_clk /rom_sys_0/clk 
    connect_bd_net /sys_concat_intc/dout /sys_ps7/IRQ_F2P 
    connect_bd_net GND_1/dout sys_concat_intc/In15 
    connect_bd_net /sys_concat_intc/In14 /axi_iic_main/iic2intc_irpt 
    connect_bd_net GND_1/dout sys_concat_intc/In13 
    connect_bd_net GND_1/dout sys_concat_intc/In12 
    connect_bd_net GND_1/dout sys_concat_intc/In11 
    connect_bd_net GND_1/dout sys_concat_intc/In10 
    connect_bd_net GND_1/dout sys_concat_intc/In9 
    connect_bd_net GND_1/dout sys_concat_intc/In8 
    connect_bd_net GND_1/dout sys_concat_intc/In7 
    connect_bd_net GND_1/dout sys_concat_intc/In6 
    connect_bd_net GND_1/dout sys_concat_intc/In5 
    connect_bd_net GND_1/dout sys_concat_intc/In4 
    connect_bd_net GND_1/dout sys_concat_intc/In3 
    connect_bd_net GND_1/dout sys_concat_intc/In2 
    connect_bd_net GND_1/dout sys_concat_intc/In1 
    connect_bd_net GND_1/dout sys_concat_intc/In0 
    connect_bd_net -net /sys_cpu_clk /sys_ps7/M_AXI_GP0_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/S00_ACLK 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/S00_ARESETN 
    connect_bd_intf_net /axi_cpu_interconnect/S00_AXI /sys_ps7/M_AXI_GP0 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M00_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_sysid_0/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M00_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_sysid_0/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M00_AXI /axi_sysid_0/s_axi 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M01_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_iic_main/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M01_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_iic_main/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M01_AXI /axi_iic_main/S_AXI 
    connect_bd_net -net /sys_200m_clk /axi_ad9361/delay_clk 
    connect_bd_net /axi_ad9361/l_clk /axi_ad9361/clk 
    connect_bd_net /enable /axi_ad9361/enable 
    connect_bd_net /txnrx /axi_ad9361/txnrx 
    connect_bd_net /up_enable /axi_ad9361/up_enable 
    connect_bd_net /up_txnrx /axi_ad9361/up_txnrx 
    connect_bd_net -net /sys_cpu_clk /util_ad9361_tdd_sync/clk 
    connect_bd_net -net /sys_cpu_resetn /util_ad9361_tdd_sync/rstn 
    connect_bd_net /util_ad9361_tdd_sync/sync_out /axi_ad9361/tdd_sync 
    connect_bd_net /util_ad9361_tdd_sync/sync_mode /axi_ad9361/tdd_sync_cntr 
    connect_bd_net /tdd_sync_t /axi_ad9361/tdd_sync_cntr 
    connect_bd_net /tdd_sync_o /util_ad9361_tdd_sync/sync_out 
    connect_bd_net /tdd_sync_i /util_ad9361_tdd_sync/sync_in 
    connect_bd_net /gps_pps /axi_ad9361/gps_pps 
    WARNING: [BD 41-1753] The name 'util_ad9361_divclk_sel_concat' you have specified is long. The Windows OS has path length limitations. It is recommended you use shorter names(less than 25 characters) to reduce the likelihood of issues when/if running on windows OS. 
    connect_bd_net /axi_ad9361/adc_r1_mode /util_ad9361_divclk_sel_concat/In0 
    connect_bd_net /axi_ad9361/dac_r1_mode /util_ad9361_divclk_sel_concat/In1 
    connect_bd_net /util_ad9361_divclk_sel_concat/dout /util_ad9361_divclk_sel/Op1 
    connect_bd_net /util_ad9361_divclk_sel/Res /util_ad9361_divclk/clk_sel 
    connect_bd_net /axi_ad9361/l_clk /util_ad9361_divclk/clk 
    connect_bd_net /sys_rstgen/peripheral_aresetn /util_ad9361_divclk_reset/ext_reset_in 
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_divclk_reset/slowest_sync_clk 
    connect_bd_net /axi_ad9361/l_clk /util_ad9361_adc_fifo/din_clk 
    connect_bd_net /axi_ad9361/rst /util_ad9361_adc_fifo/din_rst 
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_adc_fifo/dout_clk 
    connect_bd_net /util_ad9361_divclk_reset/peripheral_aresetn /util_ad9361_adc_fifo/dout_rstn 
    connect_bd_net /axi_ad9361/adc_enable_i0 /util_ad9361_adc_fifo/din_enable_0 
    connect_bd_net /axi_ad9361/adc_valid_i0 /util_ad9361_adc_fifo/din_valid_0 
    connect_bd_net /axi_ad9361/adc_data_i0 /util_ad9361_adc_fifo/din_data_0 
    connect_bd_net /axi_ad9361/adc_enable_q0 /util_ad9361_adc_fifo/din_enable_1 
    connect_bd_net /axi_ad9361/adc_valid_q0 /util_ad9361_adc_fifo/din_valid_1 
    connect_bd_net /axi_ad9361/adc_data_q0 /util_ad9361_adc_fifo/din_data_1 
    connect_bd_net /axi_ad9361/adc_enable_i1 /util_ad9361_adc_fifo/din_enable_2 
    connect_bd_net /axi_ad9361/adc_valid_i1 /util_ad9361_adc_fifo/din_valid_2 
    connect_bd_net /axi_ad9361/adc_data_i1 /util_ad9361_adc_fifo/din_data_2 
    connect_bd_net /axi_ad9361/adc_enable_q1 /util_ad9361_adc_fifo/din_enable_3 
    connect_bd_net /axi_ad9361/adc_valid_q1 /util_ad9361_adc_fifo/din_valid_3 
    connect_bd_net /axi_ad9361/adc_data_q1 /util_ad9361_adc_fifo/din_data_3 
    connect_bd_net /util_ad9361_adc_fifo/din_ovf /axi_ad9361/adc_dovf 
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_adc_pack/clk 
    connect_bd_net /util_ad9361_divclk_reset/peripheral_reset /util_ad9361_adc_pack/reset 
    connect_bd_net /util_ad9361_adc_fifo/dout_valid_0 /util_ad9361_adc_pack/fifo_wr_en 
    connect_bd_net /util_ad9361_adc_pack/fifo_wr_overflow /util_ad9361_adc_fifo/dout_ovf 
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_0 /util_ad9361_adc_pack/enable_0 
    connect_bd_net /util_ad9361_adc_fifo/dout_data_0 /util_ad9361_adc_pack/fifo_wr_data_0 
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_1 /util_ad9361_adc_pack/enable_1 
    connect_bd_net /util_ad9361_adc_fifo/dout_data_1 /util_ad9361_adc_pack/fifo_wr_data_1 
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_2 /util_ad9361_adc_pack/enable_2 
    connect_bd_net /util_ad9361_adc_fifo/dout_data_2 /util_ad9361_adc_pack/fifo_wr_data_2 
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_3 /util_ad9361_adc_pack/enable_3 
    connect_bd_net /util_ad9361_adc_fifo/dout_data_3 /util_ad9361_adc_pack/fifo_wr_data_3 
    connect_bd_net /util_ad9361_divclk/clk_out /axi_ad9361_adc_dma/fifo_wr_clk 
    connect_bd_intf_net /util_ad9361_adc_pack/packed_fifo_wr /axi_ad9361_adc_dma/fifo_wr 
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_adc_dma/m_dest_axi_aresetn 
    connect_bd_net /axi_ad9361/l_clk /axi_ad9361_dac_fifo/dout_clk 
    connect_bd_net /axi_ad9361/rst /axi_ad9361_dac_fifo/dout_rst 
    connect_bd_net /util_ad9361_divclk/clk_out /axi_ad9361_dac_fifo/din_clk 
    connect_bd_net /util_ad9361_divclk_reset/peripheral_aresetn /axi_ad9361_dac_fifo/din_rstn 
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_0 /axi_ad9361/dac_enable_i0 
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_0 /axi_ad9361/dac_valid_i0 
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_0 /axi_ad9361/dac_data_i0 
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_1 /axi_ad9361/dac_enable_q0 
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_1 /axi_ad9361/dac_valid_q0 
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_1 /axi_ad9361/dac_data_q0 
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_2 /axi_ad9361/dac_enable_i1 
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_2 /axi_ad9361/dac_valid_i1 
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_2 /axi_ad9361/dac_data_i1 
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_3 /axi_ad9361/dac_enable_q1 
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_3 /axi_ad9361/dac_valid_q1 
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_3 /axi_ad9361/dac_data_q1 
    connect_bd_net /axi_ad9361_dac_fifo/dout_unf /axi_ad9361/dac_dunf 
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_dac_upack/clk 
    connect_bd_net /util_ad9361_divclk_reset/peripheral_reset /util_ad9361_dac_upack/reset 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_en /axi_ad9361_dac_fifo/din_valid_0 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_underflow /axi_ad9361_dac_fifo/din_unf 
    connect_bd_net /util_ad9361_dac_upack/enable_0 /axi_ad9361_dac_fifo/din_enable_0 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_0 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_0 /axi_ad9361_dac_fifo/din_data_0 
    connect_bd_net /util_ad9361_dac_upack/enable_1 /axi_ad9361_dac_fifo/din_enable_1 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_1 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_1 /axi_ad9361_dac_fifo/din_data_1 
    connect_bd_net /util_ad9361_dac_upack/enable_2 /axi_ad9361_dac_fifo/din_enable_2 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_2 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_2 /axi_ad9361_dac_fifo/din_data_2 
    connect_bd_net /util_ad9361_dac_upack/enable_3 /axi_ad9361_dac_fifo/din_enable_3 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_3 
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_3 /axi_ad9361_dac_fifo/din_data_3 
    connect_bd_net /util_ad9361_divclk/clk_out /axi_ad9361_dac_dma/m_axis_aclk 
    connect_bd_intf_net /axi_ad9361_dac_dma/m_axis /util_ad9361_dac_upack/s_axis 
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_dac_dma/m_src_axi_aresetn 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M02_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_ad9361/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M02_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M02_AXI /axi_ad9361/s_axi 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M03_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_adc_dma/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M03_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_adc_dma/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M03_AXI /axi_ad9361_adc_dma/s_axi 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M04_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_dac_dma/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M04_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_dac_dma/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M04_AXI /axi_ad9361_dac_dma/s_axi 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    connect_bd_net -net /sys_cpu_resetn /axi_hp1_interconnect/aresetn 
    connect_bd_net -net /sys_cpu_clk /axi_hp1_interconnect/aclk 
    connect_bd_intf_net /axi_hp1_interconnect/M00_AXI /sys_ps7/S_AXI_HP1 
    connect_bd_net -net /sys_cpu_clk /sys_ps7/S_AXI_HP1_ACLK 
    connect_bd_intf_net /axi_hp1_interconnect/S00_AXI /axi_ad9361_adc_dma/m_dest_axi 
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_adc_dma/m_dest_axi_aclk 
    WARNING: [BD 5-230] No cells matched 'get_bd_cells /sys_mb' 
    WARNING: [BD 5-232] No interface pins matched 'get_bd_intf_pins -filter {NAME=~ *DLMB*} -of {}' 
    Slave segment </sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM> is being mapped into address space </axi_ad9361_adc_dma/m_dest_axi> at <0x0000_0000 [ 1G ]> 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    connect_bd_net -net /sys_cpu_resetn /axi_hp2_interconnect/aresetn 
    connect_bd_net -net /sys_cpu_clk /axi_hp2_interconnect/aclk 
    connect_bd_intf_net /axi_hp2_interconnect/M00_AXI /sys_ps7/S_AXI_HP2 
    connect_bd_net -net /sys_cpu_clk /sys_ps7/S_AXI_HP2_ACLK 
    connect_bd_intf_net /axi_hp2_interconnect/S00_AXI /axi_ad9361_dac_dma/m_src_axi 
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_dac_dma/m_src_axi_aclk 
    WARNING: [BD 5-230] No cells matched 'get_bd_cells /sys_mb' 
    WARNING: [BD 5-232] No interface pins matched 'get_bd_intf_pins -filter {NAME=~ *DLMB*} -of {}' 
    Slave segment </sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM> is being mapped into address space </axi_ad9361_dac_dma/m_src_axi> at <0x0000_0000 [ 1G ]> 
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In13 
    connect_bd_net /sys_concat_intc/In13 /axi_ad9361_adc_dma/irq 
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In12 
    connect_bd_net /sys_concat_intc/In12 /axi_ad9361_dac_dma/irq 
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In11 
    connect_bd_net /sys_concat_intc/In11 /axi_ad9361/gps_pps_irq 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [BD 41-721] Attempt to set value '0' on disabled parameter 'SYNC_TRANSFER_START' of cell '/axi_hdmi_dma' is ignored 
    connect_bd_net -net /sys_200m_clk /axi_hdmi_clkgen/clk 
    connect_bd_intf_net /sys_ps7/MDIO_ETHERNET_1 /sys_rgmii/MDIO_GEM 
    connect_bd_intf_net /sys_ps7/GMII_ETHERNET_1 /sys_rgmii/GMII 
    connect_bd_intf_net /sys_rgmii/MDIO_PHY /eth1_mdio 
    connect_bd_intf_net /sys_rgmii/RGMII /eth1_rgmii 
    connect_bd_net /sys_ps7/ENET1_EXT_INTIN /eth1_intn 
    connect_bd_net -net /sys_200m_clk /sys_rgmii_rstgen/slowest_sync_clk 
    connect_bd_net -net /sys_200m_clk /sys_rgmii/clkin 
    connect_bd_net /sys_rgmii_rstgen/ext_reset_in /sys_ps7/FCLK_RESET0_N 
    connect_bd_net /sys_rgmii_rstgen/peripheral_reset /sys_rgmii/tx_reset 
    connect_bd_net /sys_rgmii_rstgen/peripheral_reset /sys_rgmii/rx_reset 
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_core/vdma_clk 
    connect_bd_net /axi_hdmi_core/hdmi_clk /axi_hdmi_clkgen/clk_0 
    connect_bd_net /axi_hdmi_core/hdmi_out_clk /hdmi_out_clk 
    connect_bd_net /axi_hdmi_core/hdmi_16_hsync /hdmi_hsync 
    connect_bd_net /axi_hdmi_core/hdmi_16_vsync /hdmi_vsync 
    connect_bd_net /axi_hdmi_core/hdmi_16_data_e /hdmi_data_e 
    connect_bd_net /axi_hdmi_core/hdmi_16_data /hdmi_data 
    connect_bd_intf_net /axi_hdmi_dma/m_axis /axi_hdmi_core/s_axis 
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_dma/s_axi_aresetn 
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_dma/m_src_axi_aresetn 
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_dma/s_axi_aclk 
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_dma/m_src_axi_aclk 
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_dma/m_axis_aclk 
    connect_bd_net -net /sys_cpu_clk /axi_spdif_tx_core/dma_req_aclk 
    connect_bd_net -net /sys_cpu_clk /sys_ps7/DMA0_ACLK 
    connect_bd_net -net /sys_cpu_resetn /axi_spdif_tx_core/dma_req_rstn 
    connect_bd_intf_net /sys_ps7/DMA0_REQ /axi_spdif_tx_core/dma_req 
    connect_bd_intf_net /sys_ps7/DMA0_ACK /axi_spdif_tx_core/dma_ack 
    connect_bd_net -net /sys_200m_clk /sys_audio_clkgen/clk_in1 
    connect_bd_net -net /sys_cpu_resetn /sys_audio_clkgen/resetn 
    connect_bd_net /sys_audio_clkgen/clk_out1 /axi_spdif_tx_core/spdif_data_clk 
    connect_bd_net /spdif /axi_spdif_tx_core/spdif_tx_o 
    connect_bd_net -net /sys_cpu_clk /axi_i2s_adi/dma_req_rx_aclk 
    connect_bd_net -net /sys_cpu_clk /axi_i2s_adi/dma_req_tx_aclk 
    connect_bd_net -net /sys_cpu_clk /sys_ps7/DMA1_ACLK 
    connect_bd_net -net /sys_cpu_clk /sys_ps7/DMA2_ACLK 
    connect_bd_net -net /sys_cpu_resetn /axi_i2s_adi/dma_req_rx_rstn 
    connect_bd_net -net /sys_cpu_resetn /axi_i2s_adi/dma_req_tx_rstn 
    connect_bd_intf_net /sys_ps7/DMA1_REQ /axi_i2s_adi/dma_req_tx 
    connect_bd_intf_net /sys_ps7/DMA1_ACK /axi_i2s_adi/dma_ack_tx 
    connect_bd_intf_net /sys_ps7/DMA2_REQ /axi_i2s_adi/dma_req_rx 
    connect_bd_intf_net /sys_ps7/DMA2_ACK /axi_i2s_adi/dma_ack_rx 
    connect_bd_net /sys_audio_clkgen/clk_out1 /i2s_mclk 
    connect_bd_net /sys_audio_clkgen/clk_out1 /axi_i2s_adi/data_clk_i 
    connect_bd_intf_net /i2s /axi_i2s_adi/i2s 
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In15 
    connect_bd_net /sys_concat_intc/In15 /axi_hdmi_dma/irq 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M05_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_clkgen/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M05_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_clkgen/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M05_AXI /axi_hdmi_clkgen/s_axi 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M06_ACLK 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M06_ARESETN 
    connect_bd_intf_net /axi_cpu_interconnect/M06_AXI /axi_hdmi_dma/s_axi 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M07_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_core/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M07_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_core/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M07_AXI /axi_hdmi_core/s_axi 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M08_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_spdif_tx_core/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M08_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_spdif_tx_core/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M08_AXI /axi_spdif_tx_core/s_axi 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M09_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_i2s_adi/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M09_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_i2s_adi/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M09_AXI /axi_i2s_adi/s_axi 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    connect_bd_net -net /sys_cpu_resetn /axi_hp0_interconnect/aresetn 
    connect_bd_net -net /sys_cpu_clk /axi_hp0_interconnect/aclk 
    connect_bd_intf_net /axi_hp0_interconnect/M00_AXI /sys_ps7/S_AXI_HP0 
    connect_bd_net -net /sys_cpu_clk /sys_ps7/S_AXI_HP0_ACLK 
    connect_bd_intf_net /axi_hp0_interconnect/S00_AXI /axi_hdmi_dma/m_src_axi 
    WARNING: [BD 5-230] No cells matched 'get_bd_cells /sys_mb' 
    WARNING: [BD 5-232] No interface pins matched 'get_bd_intf_pins -filter {NAME=~ *DLMB*} -of {}' 
    Slave segment </sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM> is being mapped into address space </axi_hdmi_dma/m_src_axi> at <0x0000_0000 [ 1G ]> 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M10_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_pz_xcvrlb/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M10_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_pz_xcvrlb/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M10_AXI /axi_pz_xcvrlb/s_axi 
    connect_bd_net /axi_pz_xcvrlb/ref_clk /gt_ref_clk_0 
    connect_bd_net /axi_pz_xcvrlb/rx_p /gt_rx_p 
    connect_bd_net /axi_pz_xcvrlb/rx_n /gt_rx_n 
    connect_bd_net /axi_pz_xcvrlb/tx_p /gt_tx_p 
    connect_bd_net /axi_pz_xcvrlb/tx_n /gt_tx_n 
    connect_bd_net /clk_0 /axi_gpreg/d_clk_0 
    connect_bd_net /clk_1 /axi_gpreg/d_clk_1 
    connect_bd_net /gt_ref_clk_1 /axi_gpreg/d_clk_2 
    connect_bd_net /gp_in_0 /axi_gpreg/up_gp_in_0 
    connect_bd_net /gp_in_1 /axi_gpreg/up_gp_in_1 
    connect_bd_net /gp_out_0 /axi_gpreg/up_gp_out_0 
    connect_bd_net /gp_out_1 /axi_gpreg/up_gp_out_1 
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M11_ACLK 
    connect_bd_net -net /sys_cpu_clk /axi_gpreg/s_axi_aclk 
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M11_ARESETN 
    connect_bd_net -net /sys_cpu_resetn /axi_gpreg/s_axi_aresetn 
    connect_bd_intf_net /axi_cpu_interconnect/M11_AXI /axi_gpreg/s_axi 
    WARNING: [BD 5-230] No cells matched 'get_bd_cells ila_adc' 
    connect_bd_net /rx_clk_in_p /axi_ad9361/rx_clk_in_p 
    connect_bd_net /rx_clk_in_n /axi_ad9361/rx_clk_in_n 
    connect_bd_net /rx_frame_in_p /axi_ad9361/rx_frame_in_p 
    connect_bd_net /rx_frame_in_n /axi_ad9361/rx_frame_in_n 
    connect_bd_net /rx_data_in_p /axi_ad9361/rx_data_in_p 
    connect_bd_net /rx_data_in_n /axi_ad9361/rx_data_in_n 
    connect_bd_net /tx_clk_out_p /axi_ad9361/tx_clk_out_p 
    connect_bd_net /tx_clk_out_n /axi_ad9361/tx_clk_out_n 
    connect_bd_net /tx_frame_out_p /axi_ad9361/tx_frame_out_p 
    connect_bd_net /tx_frame_out_n /axi_ad9361/tx_frame_out_n 
    connect_bd_net /tx_data_out_p /axi_ad9361/tx_data_out_p 
    connect_bd_net /tx_data_out_n /axi_ad9361/tx_data_out_n 
    connect_bd_net -net /sys_cpu_clk /sys_cpu_clk_out 
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd>  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values.  
    WARNING: [#UNDEF] When using EMIO pins for SPI_0 tie SSIN High in the PL bitstream 
    WARNING: [#UNDEF] When using EMIO pins for SPI_1 tie SSIN High in the PL bitstream 
    WARNING: [BD 41-927] Following properties on pin /axi_sysid_0/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /rom_sys_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/delay_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK1  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/l_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_tdd_sync/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk_out have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	POLARITY=ACTIVE_HIGH  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_pack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	POLARITY=ACTIVE_HIGH  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_dac_upack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_hdmi_clkgen_0_clk_0  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_out_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_hdmi_core_0_hdmi_out_clk  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/vdma_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/spdif_data_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1  
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/dma_req_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/data_clk_i have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_tx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_rx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_pz_xcvrlb/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_gpreg/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    validate_bd_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 794.555 ; gain = 86.355 
    INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run. 
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd>  
    VHDL Output written to : E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/synth/system.v 
    VHDL Output written to : E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/sim/system.v 
    VHDL Output written to : E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/hdl/system_wrapper.v 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_ps7 . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_iic_main . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_concat_intc . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_rstgen . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_logic_inv . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_sysid_0 . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block rom_sys_0 . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block GND_1 . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/xbar . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361 . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_tdd_sync . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk_sel_concat . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk_sel . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk_reset . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_adc_fifo . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_adc_pack . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361_adc_dma . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361_dac_fifo . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_dac_upack . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361_dac_dma . 
    Exporting to file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/hw_handoff/system_axi_hp1_interconnect_0.hwh 
    Generated Block Design Tcl file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/hw_handoff/system_axi_hp1_interconnect_0_bd.tcl 
    Generated Hardware Definition File e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/synth/system_axi_hp1_interconnect_0.hwdef 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hp1_interconnect . 
    Exporting to file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/hw_handoff/system_axi_hp2_interconnect_0.hwh 
    Generated Block Design Tcl file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/hw_handoff/system_axi_hp2_interconnect_0_bd.tcl 
    Generated Hardware Definition File e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/synth/system_axi_hp2_interconnect_0.hwdef 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hp2_interconnect . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_rgmii . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_rgmii_rstgen . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hdmi_clkgen . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hdmi_core . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hdmi_dma . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_audio_clkgen . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_spdif_tx_core . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_i2s_adi . 
    Exporting to file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/hw_handoff/system_axi_hp0_interconnect_0.hwh 
    Generated Block Design Tcl file e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/hw_handoff/system_axi_hp0_interconnect_0_bd.tcl 
    Generated Hardware Definition File e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/synth/system_axi_hp0_interconnect_0.hwdef 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hp0_interconnect . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_pz_xcvrlb . 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpreg . 
    WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_pc_0/system_auto_pc_0_ooc.xdc' 
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/s00_couplers/auto_pc . 
    Exporting to file E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/hw_handoff/system.hwh 
    Generated Block Design Tcl file E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl 
    Generated Hardware Definition File E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/synth/system.hwdef 
    generate_target: Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 1118.031 ; gain = 323.477 
    Skipping synthesis 
    Skipping 
    Preprocessing adrv9361z7035 ccfmc_lvds rxtx 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets util_ad9361_dac_upack_dac_data_0' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets util_ad9361_dac_upack_dac_data_1' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets util_ad9361_dac_upack_dac_data_2' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets util_ad9361_dac_upack_dac_data_3' 
    WARNING: [BD 41-597] NET <Net> has no source 
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd>  
    WARNING: [#UNDEF] When using EMIO pins for SPI_0 tie SSIN High in the PL bitstream 
    WARNING: [#UNDEF] When using EMIO pins for SPI_1 tie SSIN High in the PL bitstream 
    WARNING: [BD 41-927] Following properties on pin /axi_sysid_0/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /rom_sys_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/delay_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK1  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/l_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_tdd_sync/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk_out have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	POLARITY=ACTIVE_HIGH  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_pack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	POLARITY=ACTIVE_HIGH  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_dac_upack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_hdmi_clkgen_0_clk_0  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_out_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_hdmi_core_0_hdmi_out_clk  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/vdma_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/spdif_data_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1  
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/dma_req_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/data_clk_i have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_tx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_rx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_pz_xcvrlb/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_gpreg/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow. 
    Please check your design and connect them as needed:  
    /axi_ad9361_dac_fifo/din_valid_in_0 
    /axi_ad9361_dac_fifo/din_valid_in_1 
    /axi_ad9361_dac_fifo/din_valid_in_2 
    /axi_ad9361_dac_fifo/din_valid_in_3 
     
    validate_bd_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1127.777 ; gain = 9.746 
    WARNING: [BD 41-597] NET <Net> has no source 
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd>  
    INFO: [Common 17-206] Exiting Vivado at Sun Mar 20 11:43:36 2022... 
     
    ****** Vivado v2019.1 (64-bit) 
      **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 
      **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 
        ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
     
    source vivado_insert_ip.tcl -notrace 
    Scanning sources... 
    Finished scanning sources 
    WARNING: [filemgmt 56-3] IP Repository Path: Could not find the directory 'E:/hdl_prj/ghdl/library'. 
    INFO: [IP_Flow 19-234] Refreshing IP repositories 
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/ipcore'. 
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'. 
    WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/hdl_prj/ghdl/library'; Can't find the specified path. 
    If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. 
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2019.1/data/ip'. 
    open_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 334.457 ; gain = 30.418 
    INFO: [IP_Flow 19-949] Unzipped './ipcore/HDL_DUT_ip_v1_0.zip' into repository 'e:/hdl_prj/vivado_ip_prj/ipcore'. 
    INFO: [IP_Flow 19-725] Reloaded user IP repository 'e:/hdl_prj/vivado_ip_prj/ipcore' 
    INFO: [IP_Flow 19-1839] IP Catalog is up to date. 
    Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - sys_ps7 
    Adding component instance block -- xilinx.com:ip:axi_iic:2.0 - axi_iic_main 
    Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - sys_concat_intc 
    Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - sys_rstgen 
    Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - sys_logic_inv 
    Adding component instance block -- analog.com:user:axi_sysid:1.0 - axi_sysid_0 
    Adding component instance block -- analog.com:user:sysid_rom:1.0 - rom_sys_0 
    Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - GND_1 
    Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_cpu_interconnect 
    Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar 
    Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc 
    Adding component instance block -- analog.com:user:axi_ad9361:1.0 - axi_ad9361 
    Adding component instance block -- analog.com:user:util_tdd_sync:1.0 - util_ad9361_tdd_sync 
    Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - util_ad9361_divclk_sel_concat 
    Adding component instance block -- xilinx.com:ip:util_reduced_logic:2.0 - util_ad9361_divclk_sel 
    Adding component instance block -- analog.com:user:util_clkdiv:1.0 - util_ad9361_divclk 
    Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - util_ad9361_divclk_reset 
    Adding component instance block -- analog.com:user:util_wfifo:1.0 - util_ad9361_adc_fifo 
    Adding component instance block -- analog.com:user:util_cpack2:1.0 - util_ad9361_adc_pack 
    Adding component instance block -- analog.com:user:axi_dmac:1.0 - axi_ad9361_adc_dma 
    Adding component instance block -- analog.com:user:util_rfifo:1.0 - axi_ad9361_dac_fifo 
    Adding component instance block -- analog.com:user:util_upack2:1.0 - util_ad9361_dac_upack 
    Adding component instance block -- analog.com:user:axi_dmac:1.0 - axi_ad9361_dac_dma 
    Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_hp1_interconnect 
    Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_hp2_interconnect 
    Adding component instance block -- xilinx.com:ip:gmii_to_rgmii:4.0 - sys_rgmii 
    Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - sys_rgmii_rstgen 
    Adding component instance block -- analog.com:user:axi_clkgen:1.0 - axi_hdmi_clkgen 
    Adding component instance block -- analog.com:user:axi_hdmi_tx:1.0 - axi_hdmi_core 
    Adding component instance block -- analog.com:user:axi_dmac:1.0 - axi_hdmi_dma 
    Adding component instance block -- xilinx.com:ip:clk_wiz:6.0 - sys_audio_clkgen 
    Adding component instance block -- analog.com:user:axi_spdif_tx:1.0 - axi_spdif_tx_core 
    Adding component instance block -- analog.com:user:axi_i2s_adi:1.0 - axi_i2s_adi 
    Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_hp0_interconnect 
    Adding component instance block -- analog.com:user:axi_xcvrlb:1.0 - axi_pz_xcvrlb 
    Adding component instance block -- analog.com:user:axi_gpreg:1.0 - axi_gpreg 
    Successfully read diagram <system> from BD file <E:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/system.bd> 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /gpio_status' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /gpio_ctl' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /util_ad9361_adc_pack/fifo_wr_en' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /util_ad9361_adc_pack/fifo_wr_data_0' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /util_ad9361_adc_pack/fifo_wr_data_1' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /util_ad9361_adc_fifo/dout_data_0' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /util_ad9361_adc_fifo/dout_data_1' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /axi_ad9361_dac_fifo/din_data_0' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /axi_ad9361_dac_fifo/din_data_1' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /util_ad9361_dac_upack/fifo_rd_data_0' 
    WARNING: [BD 5-234] No nets matched 'get_bd_nets -of_objects /util_ad9361_dac_upack/fifo_rd_data_1' 
    WARNING: [#UNDEF] When using EMIO pins for SPI_0 tie SSIN High in the PL bitstream 
    WARNING: [#UNDEF] When using EMIO pins for SPI_1 tie SSIN High in the PL bitstream 
    WARNING: [BD 41-927] Following properties on pin /axi_sysid_0/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /rom_sys_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/delay_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK1  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/l_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_tdd_sync/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk_out have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	POLARITY=ACTIVE_HIGH  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_pack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	POLARITY=ACTIVE_HIGH  
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk  
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_dac_upack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_hdmi_clkgen_0_clk_0  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_out_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_axi_hdmi_core_0_hdmi_out_clk  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/vdma_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/spdif_data_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1  
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/dma_req_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/data_clk_i have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_tx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_rx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_pz_xcvrlb/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /axi_gpreg/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0  
    WARNING: [BD 41-927] Following properties on pin /HDL_DUT_ip_0/IPCORE_CLK have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    WARNING: [BD 41-927] Following properties on pin /HDL_DUT_ip_0/AXI4_Lite_ACLK have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. 
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out  
    CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow. 
    Please check your design and connect them as needed:  
    /axi_ad9361_dac_fifo/din_valid_in_0 
    /axi_ad9361_dac_fifo/din_valid_in_1 
    /axi_ad9361_dac_fifo/din_valid_in_2 
    /axi_ad9361_dac_fifo/din_valid_in_3 
     
    validate_bd_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 515.043 ; gain = 106.250 
    WARNING: [BD 41-597] NET <Net> has no source 
    Wrote  : <E:\hdl_prj\vivado_ip_prj\vivado_prj.srcs\sources_1\bd\system\system.bd>  
    INFO: [Common 17-206] Exiting Vivado at Sun Mar 20 11:43:58 2022... 
    ### Generating Xilinx Vivado with IP Integrator project: hdl_prj\vivado_ip_prj\vivado_prj.xpr
    ### Generated logfile: hdl_prj\hdlsrc\frequency_hopping\workflow_task_CreateProject.log
    ### Task "Create Project" successful.
    ### ++++++++++++++ Task Build FPGA Bitstream ++++++++++++++
    ### Build FPGA Bitstream
    >> hdlworkflow

    which says "Task Create Project successful." and started to Build FPGA Bitstream and then stopped without generate bitstream

    1- do this means the project has been built correctly ? if yes ? why still get error when     using HDL workflow?

    I tried to use Vivado to Synthesis and Implementation the project which was build by Matlab and finally get bitstream file with these warnings

    [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow. Please check your design and connect them as needed: /axi_ad9361_dac_fifo/din_valid_in_0 /axi_ad9361_dac_fifo/din_valid_in_1 /axi_ad9361_dac_fifo/din_valid_in_2 /axi_ad9361_dac_fifo/din_valid_in_3

    and the "Implementation log"

    *** Running vivado
        with args -log system_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source system_top.tcl -notrace
    
    
    ****** Vivado v2019.1 (64-bit)
      **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
      **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
        ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
    
    source system_top.tcl -notrace
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/ipcore'.
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/hdl_prj/vivado_ip_prj/library'.
    WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/hdl_prj/ghdl/library'; Can't find the specified path.
    If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2019.1/data/ip'.
    Command: link_design -top system_top -part xc7z035ifbg676-2L
    Design is defaulting to srcset: sources_1
    Design is defaulting to constrset: constrs_1
    INFO: [Device 21-403] Loading part xc7z035ifbg676-2L
    INFO: [Netlist 29-17] Analyzing 2207 Unisim elements for replacement
    INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
    INFO: [Project 1-479] Netlist was created with Vivado 2019.1
    INFO: [Project 1-570] Preparing netlist for logic optimization
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_ps7_0/system_sys_ps7_0.xdc] for cell 'i_system_wrapper/system_i/sys_ps7/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_ps7_0/system_sys_ps7_0.xdc] for cell 'i_system_wrapper/system_i/sys_ps7/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_iic_main_0/system_axi_iic_main_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_iic_main/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_iic_main_0/system_axi_iic_main_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_iic_main/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/system_sys_rstgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_rstgen/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/system_sys_rstgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_rstgen/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/system_sys_rstgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_rstgen/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/system_sys_rstgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_rstgen/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/axi_ad9361_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/axi_ad9361_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_tdd_sync_0/util_tdd_sync_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_tdd_sync/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_tdd_sync_0/util_tdd_sync_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_tdd_sync/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_reset_0/system_util_ad9361_divclk_reset_0_board.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_divclk_reset/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_reset_0/system_util_ad9361_divclk_reset_0_board.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_divclk_reset/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_reset_0/system_util_ad9361_divclk_reset_0.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_divclk_reset/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_reset_0/system_util_ad9361_divclk_reset_0.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_divclk_reset/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_adc_fifo/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_adc_fifo/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_fifo_0/util_rfifo_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_fifo_0/util_rfifo_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_1/bd_31bd_psr_aclk_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/clk_map/psr_aclk/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_1/bd_31bd_psr_aclk_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/clk_map/psr_aclk/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_1/bd_31bd_psr_aclk_0.xdc] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/clk_map/psr_aclk/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_1/bd_31bd_psr_aclk_0.xdc] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/clk_map/psr_aclk/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_1/bd_c0fd_psr_aclk_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/clk_map/psr_aclk/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_1/bd_c0fd_psr_aclk_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/clk_map/psr_aclk/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_1/bd_c0fd_psr_aclk_0.xdc] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/clk_map/psr_aclk/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_1/bd_c0fd_psr_aclk_0.xdc] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/clk_map/psr_aclk/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_rstgen_0/system_sys_rgmii_rstgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii_rstgen/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_rstgen_0/system_sys_rgmii_rstgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii_rstgen/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_rstgen_0/system_sys_rgmii_rstgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii_rstgen/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_rstgen_0/system_sys_rgmii_rstgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii_rstgen/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hdmi_core_0/axi_hdmi_tx_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hdmi_core_0/axi_hdmi_tx_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_spdif_tx_core_0/axi_spdif_tx_constr.xdc] for cell 'i_system_wrapper/system_i/axi_spdif_tx_core/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_spdif_tx_core_0/axi_spdif_tx_constr.xdc] for cell 'i_system_wrapper/system_i/axi_spdif_tx_core/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_1/bd_a17c_psr_aclk_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/clk_map/psr_aclk/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_1/bd_a17c_psr_aclk_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/clk_map/psr_aclk/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_1/bd_a17c_psr_aclk_0.xdc] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/clk_map/psr_aclk/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_1/bd_a17c_psr_aclk_0.xdc] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/clk_map/psr_aclk/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_pz_xcvrlb_0/axi_xcvrlb_constr.xdc] for cell 'i_system_wrapper/system_i/axi_pz_xcvrlb/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_pz_xcvrlb_0/axi_xcvrlb_constr.xdc] for cell 'i_system_wrapper/system_i/axi_pz_xcvrlb/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc] for cell 'i_system_wrapper/system_i/axi_gpreg/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc] for cell 'i_system_wrapper/system_i/axi_gpreg/inst'
    Parsing XDC File [E:/hdl_prj/vivado_ip_prj/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc]
    Finished Parsing XDC File [E:/hdl_prj/vivado_ip_prj/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc]
    Parsing XDC File [E:/hdl_prj/vivado_ip_prj/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc]
    Finished Parsing XDC File [E:/hdl_prj/vivado_ip_prj/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc]
    Parsing XDC File [E:/hdl_prj/vivado_ip_prj/projects/adrv9361z7035/common/ccfmc_constr.xdc]
    Finished Parsing XDC File [E:/hdl_prj/vivado_ip_prj/projects/adrv9361z7035/common/ccfmc_constr.xdc]
    Parsing XDC File [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/ccfmc_constr.xdc]
    WARNING: [Constraints 18-619] A clock with name 'eth1_rgmii_rxclk' already exists, overwriting the previous clock with the same name. [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/ccfmc_constr.xdc:80]
    WARNING: [Constraints 18-619] A clock with name 'ref_clk_0' already exists, overwriting the previous clock with the same name. [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/ccfmc_constr.xdc:147]
    WARNING: [Constraints 18-619] A clock with name 'ref_clk_1' already exists, overwriting the previous clock with the same name. [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/ccfmc_constr.xdc:148]
    WARNING: [Constraints 18-619] A clock with name 'clk0' already exists, overwriting the previous clock with the same name. [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/ccfmc_constr.xdc:149]
    WARNING: [Constraints 18-619] A clock with name 'clk1' already exists, overwriting the previous clock with the same name. [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/ccfmc_constr.xdc:150]
    WARNING: [Constraints 18-619] A clock with name 'xcvr_clk_0' already exists, overwriting the previous clock with the same name. [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/ccfmc_constr.xdc:151]
    WARNING: [Constraints 18-619] A clock with name 'xcvr_clk_1' already exists, overwriting the previous clock with the same name. [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/ccfmc_constr.xdc:152]
    Finished Parsing XDC File [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/ccfmc_constr.xdc]
    Parsing XDC File [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc]
    Finished Parsing XDC File [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc]
    Parsing XDC File [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc]
    WARNING: [Constraints 18-619] A clock with name 'rx_clk' already exists, overwriting the previous clock with the same name. [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc:40]
    Finished Parsing XDC File [E:/hdl_prj/vivado_ip_prj/hdl/vendor/AnalogDevices/vivado/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc]
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/system_axi_ad9361_0_pps_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/system_axi_ad9361_0_pps_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_0/util_clkdiv_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_divclk/inst'
    INFO: [Timing 38-35] Done setting XDC timing constraints. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_0/util_clkdiv_constr.xdc:1]
    INFO: [Timing 38-2] Deriving generated clocks [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_0/util_clkdiv_constr.xdc:1]
    get_clocks: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1480.062 ; gain = 432.090
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_0/util_clkdiv_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_divclk/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_adc_dma_0/system_axi_ad9361_adc_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_adc_dma/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_adc_dma_0/system_axi_ad9361_adc_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_adc_dma/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_dma_0/system_axi_ad9361_dac_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_dac_dma/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_dma_0/system_axi_ad9361_dac_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_dac_dma/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii/U0'
    INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'system_sys_rgmii_0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:7]
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hdmi_dma_0/system_axi_hdmi_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_dma/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_hdmi_dma_0/system_axi_hdmi_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_dma/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0_late.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0_late.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_i2s_adi_0/axi_i2s_adi_constr.xdc] for cell 'i_system_wrapper/system_i/axi_i2s_adi/U0'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_i2s_adi_0/axi_i2s_adi_constr.xdc] for cell 'i_system_wrapper/system_i/axi_i2s_adi/U0'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_gpreg_0/system_axi_gpreg_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_gpreg/inst'
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_axi_gpreg_0/system_axi_gpreg_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_gpreg/inst'
    Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_cc_0/system_auto_cc_0_clocks.xdc] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst'
    WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_cc_0/system_auto_cc_0_clocks.xdc:7]
    WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-11' -to list should not be empty. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_cc_0/system_auto_cc_0_clocks.xdc:10]
    WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-15' -to list should not be empty. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_cc_0/system_auto_cc_0_clocks.xdc:13]
    Finished Parsing XDC File [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_auto_cc_0/system_auto_cc_0_clocks.xdc] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_system_wrapper/system_i/axi_cpu_interconnect/m12_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Finished Sourcing Tcl File [E:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
    Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1480.062 ; gain = 0.000
    INFO: [Project 1-111] Unisim Transformation Summary:
      A total of 211 instances were transformed.
      IOBUF => IOBUF (IBUF, OBUFT): 34 instances
      OBUFDS => OBUFDS: 8 instances
      RAM16X1D => RAM32X1D (RAMD32, RAMD32): 9 instances
      RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 160 instances
    
    14 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered.
    link_design completed successfully
    link_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 1480.062 ; gain = 1118.965
    Command: opt_design
    Attempting to get a license for feature 'Implementation' and/or device 'xc7z035i'
    INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035i'
    Running DRC as a precondition to command opt_design
    
    Starting DRC Task
    INFO: [DRC 23-27] Running DRC with 2 threads
    INFO: [Project 1-461] DRC finished with 0 Errors
    INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
    
    Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.976 . Memory (MB): peak = 1480.062 ; gain = 0.000
    
    Starting Cache Timing Information Task
    INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'system_sys_rgmii_0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:7]
    INFO: [Timing 38-35] Done setting XDC timing constraints.
    Ending Cache Timing Information Task | Checksum: 204cd4a3f
    
    Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1480.062 ; gain = 0.000
    
    Starting Logic Optimization Task
    
    Phase 1 Retarget
    INFO: [Opt 31-138] Pushed 18 inverter(s) to 88 load pin(s).
    INFO: [Opt 31-49] Retargeted 0 cell(s).
    Phase 1 Retarget | Checksum: 17e959d1f
    
    Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1585.012 ; gain = 2.066
    INFO: [Opt 31-389] Phase Retarget created 399 cells and removed 1920 cells
    INFO: [Opt 31-1021] In phase Retarget, 25 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
    
    Phase 2 Constant propagation
    INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
    Phase 2 Constant propagation | Checksum: 1758217bf
    
    Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1585.012 ; gain = 2.066
    INFO: [Opt 31-389] Phase Constant propagation created 1192 cells and removed 1627 cells
    INFO: [Opt 31-1021] In phase Constant propagation, 38 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
    
    Phase 3 Sweep
    Phase 3 Sweep | Checksum: 23a54313e
    
    Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1585.012 ; gain = 2.066
    INFO: [Opt 31-389] Phase Sweep created 54 cells and removed 2587 cells
    INFO: [Opt 31-1021] In phase Sweep, 36 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
    
    Phase 4 BUFG optimization
    INFO: [Opt 31-274] Optimized connectivity to 1 cascaded buffer cells
    Phase 4 BUFG optimization | Checksum: 207f00a20
    
    Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1585.012 ; gain = 2.066
    INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 1 cells.
    
    Phase 5 Shift Register Optimization
    INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
    Phase 5 Shift Register Optimization | Checksum: 207f00a20
    
    Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1585.012 ; gain = 2.066
    INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
    
    Phase 6 Post Processing Netlist
    Phase 6 Post Processing Netlist | Checksum: 1839d5ee7
    
    Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1585.012 ; gain = 2.066
    INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
    INFO: [Opt 31-1021] In phase Post Processing Netlist, 21 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
    Opt_design Change Summary
    =========================
    
    
    -------------------------------------------------------------------------------------------------------------------------
    |  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
    -------------------------------------------------------------------------------------------------------------------------
    |  Retarget                     |             399  |            1920  |                                             25  |
    |  Constant propagation         |            1192  |            1627  |                                             38  |
    |  Sweep                        |              54  |            2587  |                                             36  |
    |  BUFG optimization            |               0  |               1  |                                              0  |
    |  Shift Register Optimization  |               0  |               0  |                                              0  |
    |  Post Processing Netlist      |               0  |               0  |                                             21  |
    -------------------------------------------------------------------------------------------------------------------------
    
    
    
    Starting Connectivity Check Task
    
    Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.082 . Memory (MB): peak = 1585.012 ; gain = 0.000
    Ending Logic Optimization Task | Checksum: 2c3ef65a7
    
    Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1585.012 ; gain = 2.066
    
    Starting Power Optimization Task
    INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
    INFO: [Pwropt 34-9] Applying IDT optimizations ...
    INFO: [Pwropt 34-10] Applying ODC optimizations ...
    INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'system_sys_rgmii_0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:7]
    INFO: [Timing 38-35] Done setting XDC timing constraints.
    INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.252 | TNS=0.000 |
    Running Vector-less Activity Propagation...
    
    Finished Running Vector-less Activity Propagation
    
    
    Starting PowerOpt Patch Enables Task
    INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 5 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
    INFO: [Pwropt 34-201] Structural ODC has moved 1 WE to EN ports
    Number of BRAM Ports augmented: 3 newly gated: 9 Total Ports: 10
    Ending PowerOpt Patch Enables Task | Checksum: 28b8914d2
    
    Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.300 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Ending Power Optimization Task | Checksum: 28b8914d2
    
    Time (s): cpu = 00:00:39 ; elapsed = 00:00:23 . Memory (MB): peak = 1939.199 ; gain = 354.188
    
    Starting Final Cleanup Task
    
    Starting Logic Optimization Task
    INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'system_sys_rgmii_0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:7]
    INFO: [Timing 38-35] Done setting XDC timing constraints.
    Ending Logic Optimization Task | Checksum: 20bb0e620
    
    Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Ending Final Cleanup Task | Checksum: 20bb0e620
    
    Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Starting Netlist Obfuscation Task
    Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Ending Netlist Obfuscation Task | Checksum: 20bb0e620
    
    Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [Common 17-83] Releasing license: Implementation
    46 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered.
    opt_design completed successfully
    opt_design: Time (s): cpu = 00:01:14 ; elapsed = 00:00:52 . Memory (MB): peak = 1939.199 ; gain = 459.137
    Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [Timing 38-480] Writing timing data to binary archive.
    Writing placer database...
    Writing XDEF routing.
    Writing XDEF routing logical nets.
    Writing XDEF routing special nets.
    Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.154 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [Common 17-1381] The checkpoint 'E:/hdl_prj/impl_1/system_top_opt.dcp' has been generated.
    write_checkpoint: Time (s): cpu = 00:00:21 ; elapsed = 00:00:15 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [runtcl-4] Executing : report_drc -file system_top_drc_opted.rpt -pb system_top_drc_opted.pb -rpx system_top_drc_opted.rpx
    Command: report_drc -file system_top_drc_opted.rpt -pb system_top_drc_opted.pb -rpx system_top_drc_opted.rpx
    INFO: [IP_Flow 19-1839] IP Catalog is up to date.
    INFO: [DRC 23-27] Running DRC with 2 threads
    INFO: [Coretcl 2-168] The results of DRC are in file E:/hdl_prj/impl_1/system_top_drc_opted.rpt.
    report_drc completed successfully
    report_drc: Time (s): cpu = 00:00:20 ; elapsed = 00:00:11 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Command: place_design
    Attempting to get a license for feature 'Implementation' and/or device 'xc7z035i'
    INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035i'
    INFO: [DRC 23-27] Running DRC with 2 threads
    INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
    INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
    Running DRC as a precondition to command place_design
    INFO: [DRC 23-27] Running DRC with 2 threads
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[10] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[4]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[6] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[0]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[7] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[1]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[8] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[2]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[9] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[3]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ENARDEN (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_ENARDEN_cooolgate_en_sig_5) which is driven by a register (i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_control/d_data_cntrl_int_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ENARDEN (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_ENARDEN_cooolgate_en_sig_5) which is driven by a register (i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_control/d_data_cntrl_int_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ENARDEN (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_ENARDEN_cooolgate_en_sig_5) which is driven by a register (i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_cntrl/d_data_cntrl_int_reg[18]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg/ADDRARDADDR[6] (net: i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/Q[0]) which is driven by a register (i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_raddr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg/ADDRARDADDR[7] (net: i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/Q[1]) which is driven by a register (i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_raddr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg/ADDRARDADDR[8] (net: i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/Q[2]) which is driven by a register (i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_raddr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg/ADDRARDADDR[9] (net: i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/Q[3]) which is driven by a register (i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_raddr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 12 Warnings
    INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
    
    Starting Placer Task
    INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
    
    Phase 1 Placer Initialization
    
    Phase 1.1 Placer Initialization Netlist Sorting
    Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 13f1702b7
    
    Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
    INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'system_sys_rgmii_0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:7]
    INFO: [Timing 38-35] Done setting XDC timing constraints.
    Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12ed536df
    
    Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 1.3 Build Placer Netlist Model
    Phase 1.3 Build Placer Netlist Model | Checksum: 1a2f8e50e
    
    Time (s): cpu = 00:00:48 ; elapsed = 00:00:34 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 1.4 Constrain Clocks/Macros
    Phase 1.4 Constrain Clocks/Macros | Checksum: 1a2f8e50e
    
    Time (s): cpu = 00:00:48 ; elapsed = 00:00:35 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Phase 1 Placer Initialization | Checksum: 1a2f8e50e
    
    Time (s): cpu = 00:00:48 ; elapsed = 00:00:35 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 2 Global Placement
    
    Phase 2.1 Floorplanning
    Phase 2.1 Floorplanning | Checksum: 1b742d44a
    
    Time (s): cpu = 00:00:55 ; elapsed = 00:00:38 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 2.2 Global Placement Core
    
    Phase 2.2.1 Physical Synthesis In Placer
    INFO: [Physopt 32-65] No nets found for high-fanout optimization.
    INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
    INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
    INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
    INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
    INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
    INFO: [Physopt 32-949] No candidate nets found for HD net replication
    INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
    Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Summary of Physical Synthesis Optimizations
    ============================================
    
    
    ----------------------------------------------------------------------------------------------------------------------------------------
    |  Optimization                  |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
    ----------------------------------------------------------------------------------------------------------------------------------------
    |  Very High Fanout              |            0  |              0  |                     0  |           0  |           1  |  00:00:01  |
    |  DSP Register                  |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
    |  Shift Register                |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
    |  BRAM Register                 |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
    |  HD Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
    |  Total                         |            0  |              0  |                     0  |           0  |           2  |  00:00:01  |
    ----------------------------------------------------------------------------------------------------------------------------------------
    
    
    Phase 2.2.1 Physical Synthesis In Placer | Checksum: 22eba26e8
    
    Time (s): cpu = 00:02:00 ; elapsed = 00:01:18 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Phase 2.2 Global Placement Core | Checksum: 15738f48b
    
    Time (s): cpu = 00:02:03 ; elapsed = 00:01:20 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Phase 2 Global Placement | Checksum: 15738f48b
    
    Time (s): cpu = 00:02:03 ; elapsed = 00:01:20 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 3 Detail Placement
    
    Phase 3.1 Commit Multi Column Macros
    Phase 3.1 Commit Multi Column Macros | Checksum: 1563c516f
    
    Time (s): cpu = 00:02:10 ; elapsed = 00:01:25 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 3.2 Commit Most Macros & LUTRAMs
    Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1dd7f9334
    
    Time (s): cpu = 00:02:23 ; elapsed = 00:01:34 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 3.3 Area Swap Optimization
    Phase 3.3 Area Swap Optimization | Checksum: 1776367ab
    
    Time (s): cpu = 00:02:24 ; elapsed = 00:01:35 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 3.4 Pipeline Register Optimization
    Phase 3.4 Pipeline Register Optimization | Checksum: 23d73fb3e
    
    Time (s): cpu = 00:02:24 ; elapsed = 00:01:35 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 3.5 Small Shape Detail Placement
    Phase 3.5 Small Shape Detail Placement | Checksum: 211e28462
    
    Time (s): cpu = 00:02:37 ; elapsed = 00:01:47 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 3.6 Re-assign LUT pins
    Phase 3.6 Re-assign LUT pins | Checksum: 19ef796d3
    
    Time (s): cpu = 00:02:40 ; elapsed = 00:01:51 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 3.7 Pipeline Register Optimization
    Phase 3.7 Pipeline Register Optimization | Checksum: c0303eb0
    
    Time (s): cpu = 00:02:41 ; elapsed = 00:01:51 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Phase 3 Detail Placement | Checksum: c0303eb0
    
    Time (s): cpu = 00:02:41 ; elapsed = 00:01:52 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 4 Post Placement Optimization and Clean-Up
    
    Phase 4.1 Post Commit Optimization
    INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'system_sys_rgmii_0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:7]
    INFO: [Timing 38-35] Done setting XDC timing constraints.
    
    Phase 4.1.1 Post Placement Optimization
    Post Placement Optimization Initialization | Checksum: 111d59b6c
    
    Phase 4.1.1.1 BUFG Insertion
    INFO: [Place 46-33] Processed net i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_0/i_up_dac_channel/i_xfer_cntrl/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N, BUFG insertion was skipped due to placement/routing conflicts.
    INFO: [Place 46-33] Processed net i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_cntrl/d_data_cntrl_int_reg[0]_0[0], BUFG insertion was skipped due to placement/routing conflicts.
    INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
    Phase 4.1.1.1 BUFG Insertion | Checksum: 111d59b6c
    
    Time (s): cpu = 00:03:04 ; elapsed = 00:02:07 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [Place 30-746] Post Placement Timing Summary WNS=0.739. For the most accurate timing information please run report_timing.
    Phase 4.1.1 Post Placement Optimization | Checksum: 1ed4c3f65
    
    Time (s): cpu = 00:03:04 ; elapsed = 00:02:07 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Phase 4.1 Post Commit Optimization | Checksum: 1ed4c3f65
    
    Time (s): cpu = 00:03:05 ; elapsed = 00:02:08 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 4.2 Post Placement Cleanup
    Phase 4.2 Post Placement Cleanup | Checksum: 1ed4c3f65
    
    Time (s): cpu = 00:03:05 ; elapsed = 00:02:08 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 4.3 Placer Reporting
    Phase 4.3 Placer Reporting | Checksum: 1ed4c3f65
    
    Time (s): cpu = 00:03:06 ; elapsed = 00:02:09 . Memory (MB): peak = 1939.199 ; gain = 0.000
    
    Phase 4.4 Final Placement Cleanup
    Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Phase 4.4 Final Placement Cleanup | Checksum: 12e033fc6
    
    Time (s): cpu = 00:03:06 ; elapsed = 00:02:09 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Phase 4 Post Placement Optimization and Clean-Up | Checksum: 12e033fc6
    
    Time (s): cpu = 00:03:07 ; elapsed = 00:02:09 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Ending Placer Task | Checksum: 3c5a3892
    
    Time (s): cpu = 00:03:07 ; elapsed = 00:02:09 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [Common 17-83] Releasing license: Implementation
    77 Infos, 24 Warnings, 0 Critical Warnings and 0 Errors encountered.
    place_design completed successfully
    place_design: Time (s): cpu = 00:03:16 ; elapsed = 00:02:15 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [Timing 38-480] Writing timing data to binary archive.
    Writing placer database...
    Writing XDEF routing.
    Writing XDEF routing logical nets.
    Writing XDEF routing special nets.
    Write XDEF Complete: Time (s): cpu = 00:00:13 ; elapsed = 00:00:04 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [Common 17-1381] The checkpoint 'E:/hdl_prj/impl_1/system_top_placed.dcp' has been generated.
    write_checkpoint: Time (s): cpu = 00:00:26 ; elapsed = 00:00:17 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [runtcl-4] Executing : report_io -file system_top_io_placed.rpt
    report_io: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.336 . Memory (MB): peak = 1939.199 ; gain = 0.000
    INFO: [runtcl-4] Executing : report_utilization -file system_top_utilization_placed.rpt -pb system_top_utilization_placed.pb
    INFO: [runtcl-4] Executing : report_control_sets -verbose -file system_top_control_sets_placed.rpt
    report_control_sets: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1939.199 ; gain = 0.000
    Command: route_design
    Attempting to get a license for feature 'Implementation' and/or device 'xc7z035i'
    INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035i'
    Running DRC as a precondition to command route_design
    INFO: [DRC 23-27] Running DRC with 2 threads
    INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
    INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
    
    
    Starting Routing Task
    INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
    Checksum: PlaceDB: 1363261c ConstDB: 0 ShapeSum: 28f71276 RouteDB: 0
    
    Phase 1 Build RT Design
    Phase 1 Build RT Design | Checksum: dc0f5857
    
    Time (s): cpu = 00:02:28 ; elapsed = 00:02:02 . Memory (MB): peak = 2082.473 ; gain = 143.273
    Post Restoration Checksum: NetGraph: 1b6ba7bf NumContArr: c0a3b098 Constraints: 0 Timing: 0
    
    Phase 2 Router Initialization
    
    Phase 2.1 Create Timer
    Phase 2.1 Create Timer | Checksum: dc0f5857
    
    Time (s): cpu = 00:02:29 ; elapsed = 00:02:03 . Memory (MB): peak = 2110.137 ; gain = 170.938
    
    Phase 2.2 Fix Topology Constraints
    Phase 2.2 Fix Topology Constraints | Checksum: dc0f5857
    
    Time (s): cpu = 00:02:30 ; elapsed = 00:02:04 . Memory (MB): peak = 2123.469 ; gain = 184.270
    
    Phase 2.3 Pre Route Cleanup
    Phase 2.3 Pre Route Cleanup | Checksum: dc0f5857
    
    Time (s): cpu = 00:02:30 ; elapsed = 00:02:04 . Memory (MB): peak = 2123.469 ; gain = 184.270
     Number of Nodes with overlaps = 0
    
    Phase 2.4 Update Timing
    Phase 2.4 Update Timing | Checksum: 1c4f965d0
    
    Time (s): cpu = 00:03:06 ; elapsed = 00:02:30 . Memory (MB): peak = 2267.762 ; gain = 328.562
    INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.547  | TNS=0.000  | WHS=-0.892 | THS=-2142.533|
    
    
    Phase 2.5 Update Timing for Bus Skew
    
    Phase 2.5.1 Update Timing
    Phase 2.5.1 Update Timing | Checksum: 1b71bcd37
    
    Time (s): cpu = 00:03:27 ; elapsed = 00:02:42 . Memory (MB): peak = 2323.766 ; gain = 384.566
    INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.547  | TNS=0.000  | WHS=N/A    | THS=N/A    |
    
    Phase 2.5 Update Timing for Bus Skew | Checksum: 11fb50c5a
    
    Time (s): cpu = 00:03:28 ; elapsed = 00:02:43 . Memory (MB): peak = 2323.766 ; gain = 384.566
    Phase 2 Router Initialization | Checksum: 15e9c07fc
    
    Time (s): cpu = 00:03:28 ; elapsed = 00:02:43 . Memory (MB): peak = 2323.766 ; gain = 384.566
    
    Router Utilization Summary
      Global Vertical Routing Utilization    = 0 %
      Global Horizontal Routing Utilization  = 0 %
      Routable Net Status*
      *Does not include unroutable nets such as driverless and loadless.
      Run report_route_status for detailed report.
      Number of Failed Nets               = 34036
        (Failed Nets is the sum of unrouted and partially routed nets)
      Number of Unrouted Nets             = 34035
      Number of Partially Routed Nets     = 1
      Number of Node Overlaps             = 0
    
    
    Phase 3 Initial Routing
    Phase 3 Initial Routing | Checksum: fe396d7b
    
    Time (s): cpu = 00:03:42 ; elapsed = 00:02:51 . Memory (MB): peak = 2328.023 ; gain = 388.824
    
    Phase 4 Rip-up And Reroute
    
    Phase 4.1 Global Iteration 0
     Number of Nodes with overlaps = 2001
     Number of Nodes with overlaps = 113
     Number of Nodes with overlaps = 0
    INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.547  | TNS=0.000  | WHS=N/A    | THS=N/A    |
    
    Phase 4.1 Global Iteration 0 | Checksum: 2718294a8
    
    Time (s): cpu = 00:04:07 ; elapsed = 00:03:07 . Memory (MB): peak = 2328.023 ; gain = 388.824
    Phase 4 Rip-up And Reroute | Checksum: 2718294a8
    
    Time (s): cpu = 00:04:07 ; elapsed = 00:03:07 . Memory (MB): peak = 2328.023 ; gain = 388.824
    
    Phase 5 Delay and Skew Optimization
    
    Phase 5.1 Delay CleanUp
    
    Phase 5.1.1 Update Timing
    Phase 5.1.1 Update Timing | Checksum: 1ddda4f83
    
    Time (s): cpu = 00:04:12 ; elapsed = 00:03:10 . Memory (MB): peak = 2328.023 ; gain = 388.824
    INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.724  | TNS=0.000  | WHS=N/A    | THS=N/A    |
    
    Phase 5.1 Delay CleanUp | Checksum: 287824a04
    
    Time (s): cpu = 00:04:12 ; elapsed = 00:03:10 . Memory (MB): peak = 2328.023 ; gain = 388.824
    
    Phase 5.2 Clock Skew Optimization
    Phase 5.2 Clock Skew Optimization | Checksum: 287824a04
    
    Time (s): cpu = 00:04:13 ; elapsed = 00:03:10 . Memory (MB): peak = 2328.023 ; gain = 388.824
    Phase 5 Delay and Skew Optimization | Checksum: 287824a04
    
    Time (s): cpu = 00:04:13 ; elapsed = 00:03:11 . Memory (MB): peak = 2328.023 ; gain = 388.824
    
    Phase 6 Post Hold Fix
    
    Phase 6.1 Hold Fix Iter
    
    Phase 6.1.1 Update Timing
    Phase 6.1.1 Update Timing | Checksum: 24538e98c
    
    Time (s): cpu = 00:04:19 ; elapsed = 00:03:14 . Memory (MB): peak = 2328.023 ; gain = 388.824
    INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.213  | TNS=0.000  | WHS=0.045  | THS=0.000  |
    
    Phase 6.1 Hold Fix Iter | Checksum: 27c91f1b9
    
    Time (s): cpu = 00:04:19 ; elapsed = 00:03:14 . Memory (MB): peak = 2328.023 ; gain = 388.824
    Phase 6 Post Hold Fix | Checksum: 27c91f1b9
    
    Time (s): cpu = 00:04:19 ; elapsed = 00:03:14 . Memory (MB): peak = 2328.023 ; gain = 388.824
    
    Phase 7 Route finalize
    
    Router Utilization Summary
      Global Vertical Routing Utilization    = 2.00144 %
      Global Horizontal Routing Utilization  = 2.43422 %
      Routable Net Status*
      *Does not include unroutable nets such as driverless and loadless.
      Run report_route_status for detailed report.
      Number of Failed Nets               = 0
        (Failed Nets is the sum of unrouted and partially routed nets)
      Number of Unrouted Nets             = 0
      Number of Partially Routed Nets     = 0
      Number of Node Overlaps             = 0
    
    Phase 7 Route finalize | Checksum: 2a51a3bf0
    
    Time (s): cpu = 00:04:20 ; elapsed = 00:03:15 . Memory (MB): peak = 2328.023 ; gain = 388.824
    
    Phase 8 Verifying routed nets
    
     Verification completed successfully
    Phase 8 Verifying routed nets | Checksum: 2a51a3bf0
    
    Time (s): cpu = 00:04:20 ; elapsed = 00:03:15 . Memory (MB): peak = 2328.023 ; gain = 388.824
    
    Phase 9 Depositing Routes
    INFO: [Route 35-467] Router swapped GT pin i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[1].i_xcvrlb_1/i_xch/i_gtxe2_channel/GTREFCLK0 to physical pin GTXE2_CHANNEL_X0Y9/GTSOUTHREFCLK1
    Phase 9 Depositing Routes | Checksum: 2b2d65d89
    
    Time (s): cpu = 00:04:25 ; elapsed = 00:03:20 . Memory (MB): peak = 2328.023 ; gain = 388.824
    
    Phase 10 Post Router Timing
    INFO: [Route 35-57] Estimated Timing Summary | WNS=0.213  | TNS=0.000  | WHS=0.045  | THS=0.000  |
    
    INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
    Phase 10 Post Router Timing | Checksum: 2b2d65d89
    
    Time (s): cpu = 00:04:25 ; elapsed = 00:03:21 . Memory (MB): peak = 2328.023 ; gain = 388.824
    INFO: [Route 35-16] Router Completed Successfully
    
    Time (s): cpu = 00:04:25 ; elapsed = 00:03:21 . Memory (MB): peak = 2328.023 ; gain = 388.824
    
    Routing Is Done.
    INFO: [Common 17-83] Releasing license: Implementation
    97 Infos, 24 Warnings, 0 Critical Warnings and 0 Errors encountered.
    route_design completed successfully
    route_design: Time (s): cpu = 00:04:36 ; elapsed = 00:03:27 . Memory (MB): peak = 2328.023 ; gain = 388.824
    Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 2328.023 ; gain = 0.000
    INFO: [Timing 38-480] Writing timing data to binary archive.
    Writing placer database...
    Writing XDEF routing.
    Writing XDEF routing logical nets.
    Writing XDEF routing special nets.
    Write XDEF Complete: Time (s): cpu = 00:00:17 ; elapsed = 00:00:06 . Memory (MB): peak = 2328.023 ; gain = 0.000
    INFO: [Common 17-1381] The checkpoint 'E:/hdl_prj/impl_1/system_top_routed.dcp' has been generated.
    write_checkpoint: Time (s): cpu = 00:00:29 ; elapsed = 00:00:18 . Memory (MB): peak = 2328.023 ; gain = 0.000
    INFO: [runtcl-4] Executing : report_drc -file system_top_drc_routed.rpt -pb system_top_drc_routed.pb -rpx system_top_drc_routed.rpx
    Command: report_drc -file system_top_drc_routed.rpt -pb system_top_drc_routed.pb -rpx system_top_drc_routed.rpx
    INFO: [IP_Flow 19-1839] IP Catalog is up to date.
    INFO: [DRC 23-27] Running DRC with 2 threads
    INFO: [Coretcl 2-168] The results of DRC are in file E:/hdl_prj/impl_1/system_top_drc_routed.rpt.
    report_drc completed successfully
    report_drc: Time (s): cpu = 00:00:27 ; elapsed = 00:00:16 . Memory (MB): peak = 2328.023 ; gain = 0.000
    INFO: [runtcl-4] Executing : report_methodology -file system_top_methodology_drc_routed.rpt -pb system_top_methodology_drc_routed.pb -rpx system_top_methodology_drc_routed.rpx
    Command: report_methodology -file system_top_methodology_drc_routed.rpt -pb system_top_methodology_drc_routed.pb -rpx system_top_methodology_drc_routed.rpx
    INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'system_sys_rgmii_0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:7]
    INFO: [Timing 38-35] Done setting XDC timing constraints.
    INFO: [DRC 23-133] Running Methodology with 2 threads
    INFO: [Coretcl 2-1520] The results of Report Methodology are in file E:/hdl_prj/impl_1/system_top_methodology_drc_routed.rpt.
    report_methodology completed successfully
    report_methodology: Time (s): cpu = 00:00:45 ; elapsed = 00:00:25 . Memory (MB): peak = 2412.891 ; gain = 84.867
    INFO: [runtcl-4] Executing : report_power -file system_top_power_routed.rpt -pb system_top_power_summary_routed.pb -rpx system_top_power_routed.rpx
    Command: report_power -file system_top_power_routed.rpt -pb system_top_power_summary_routed.pb -rpx system_top_power_routed.rpx
    INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'system_sys_rgmii_0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [e:/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:7]
    INFO: [Timing 38-35] Done setting XDC timing constraints.
    Running Vector-less Activity Propagation...
    
    Finished Running Vector-less Activity Propagation
    WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
    Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
    111 Infos, 25 Warnings, 0 Critical Warnings and 0 Errors encountered.
    report_power completed successfully
    report_power: Time (s): cpu = 00:00:37 ; elapsed = 00:00:21 . Memory (MB): peak = 2415.055 ; gain = 2.164
    INFO: [runtcl-4] Executing : report_route_status -file system_top_route_status.rpt -pb system_top_route_status.pb
    INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file system_top_timing_summary_routed.rpt -pb system_top_timing_summary_routed.pb -rpx system_top_timing_summary_routed.rpx -warn_on_violation 
    INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
    INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
    WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
    INFO: [runtcl-4] Executing : report_incremental_reuse -file system_top_incremental_reuse_routed.rpt
    INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
    INFO: [runtcl-4] Executing : report_clock_utilization -file system_top_clock_utilization_routed.rpt
    INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file system_top_bus_skew_routed.rpt -pb system_top_bus_skew_routed.pb -rpx system_top_bus_skew_routed.rpx
    INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
    INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
    INFO: [Memdata 28-167] Found XPM memory block i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
    INFO: [Memdata 28-167] Found XPM memory block i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
    INFO: [Memdata 28-167] Found XPM memory block i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
    INFO: [Memdata 28-167] Found XPM memory block i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
    INFO: [Memdata 28-167] Found XPM memory block i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
    INFO: [Memdata 28-167] Found XPM memory block i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
    Command: write_bitstream -force system_top.bit
    Attempting to get a license for feature 'Implementation' and/or device 'xc7z035i'
    INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035i'
    Running DRC as a precondition to command write_bitstream
    INFO: [IP_Flow 19-1839] IP Catalog is up to date.
    INFO: [DRC 23-27] Running DRC with 2 threads
    WARNING: [DRC REQP-1577] Clock output buffering: MMCME2_ADV connectivity violation. The signal i_system_wrapper/system_i/sys_rgmii/U0/i_system_sys_rgmii_0_clocking/clk_10 on the i_system_wrapper/system_i/sys_rgmii/U0/i_system_sys_rgmii_0_clocking/mmcm_adv_inst/CLKOUT2 pin of i_system_wrapper/system_i/sys_rgmii/U0/i_system_sys_rgmii_0_clocking/mmcm_adv_inst does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[10] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[4]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[6] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[0]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[7] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[1]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[8] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[2]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ADDRBWRADDR[9] (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_0[3]) which is driven by a register (i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_waddr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ENARDEN (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_ENARDEN_cooolgate_en_sig_5) which is driven by a register (i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_control/d_data_cntrl_int_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ENARDEN (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_ENARDEN_cooolgate_en_sig_5) which is driven by a register (i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_control/d_data_cntrl_int_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg/ENARDEN (net: i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/i_mem/m_ram_reg_ENARDEN_cooolgate_en_sig_5) which is driven by a register (i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_cntrl/d_data_cntrl_int_reg[18]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg/ADDRARDADDR[6] (net: i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/Q[0]) which is driven by a register (i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_raddr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg/ADDRARDADDR[7] (net: i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/Q[1]) which is driven by a register (i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_raddr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg/ADDRARDADDR[8] (net: i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/Q[2]) which is driven by a register (i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_raddr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg has an input control pin i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/m_ram_reg/ADDRARDADDR[9] (net: i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/i_mem/Q[3]) which is driven by a register (i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_raddr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_ad_iqcor/g_loop[0].i_mul_i/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_ad_iqcor/g_loop[0].i_mul_q/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_ad_iqcor/g_loop[0].i_mul_i/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_ad_iqcor/g_loop[0].i_mul_q/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_ad_iqcor/g_loop[0].i_mul_i/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_ad_iqcor/g_loop[0].i_mul_q/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_ad_iqcor/g_loop[0].i_mul_i/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_ad_iqcor/g_loop[0].i_mul_q/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_0/i_ad_iqcor/g_loop[0].i_mul_i/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_0/i_ad_iqcor/g_loop[0].i_mul_q/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_0/i_dds/dds_phase[1].i_dds_2/i_dds_1_0/i_dds_scale/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_0/i_dds/dds_phase[1].i_dds_2/i_dds_1_1/i_dds_scale/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_1/i_ad_iqcor/g_loop[0].i_mul_i/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_1/i_ad_iqcor/g_loop[0].i_mul_q/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_1/i_dds/dds_phase[1].i_dds_2/i_dds_1_0/i_dds_scale/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_1/i_dds/dds_phase[1].i_dds_2/i_dds_1_1/i_dds_scale/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_2/i_ad_iqcor/g_loop[0].i_mul_i/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_2/i_ad_iqcor/g_loop[0].i_mul_q/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_2/i_dds/dds_phase[1].i_dds_2/i_dds_1_0/i_dds_scale/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_2/i_dds/dds_phase[1].i_dds_2/i_dds_1_1/i_dds_scale/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_3/i_ad_iqcor/g_loop[0].i_mul_i/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_3/i_ad_iqcor/g_loop[0].i_mul_q/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_3/i_dds/dds_phase[1].i_dds_2/i_dds_1_0/i_dds_scale/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_3/i_dds/dds_phase[1].i_dds_2/i_dds_1_1/i_dds_scale/i_mult_macro/MULT_MACRO.dsp_v5_1.DSP48_V5_1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
    INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (i_system_wrapper/system_i/axi_hdmi_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_mem/m_ram_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
    INFO: [Vivado 12-3199] DRC finished with 0 Errors, 13 Warnings, 25 Advisories
    INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
    INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
    Loading data files...
    Loading site data...
    Loading route data...
    Processing options...
    Creating bitmap...
    Creating bitstream...
    Writing bitstream ./system_top.bit...
    INFO: [Vivado 12-1842] Bitgen Completed Successfully.
    INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.).
    INFO: [Common 17-186] 'E:/hdl_prj/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Sun Mar 20 12:05:07 2022. For additional details about this file, please refer to the WebTalk help file at E:/Xilinx/Vivado/2019.1/doc/webtalk_introduction.html.
    INFO: [Common 17-83] Releasing license: Implementation
    162 Infos, 39 Warnings, 0 Critical Warnings and 0 Errors encountered.
    write_bitstream completed successfully
    write_bitstream: Time (s): cpu = 00:01:38 ; elapsed = 00:01:19 . Memory (MB): peak = 2848.449 ; gain = 429.000
    INFO: [Common 17-206] Exiting Vivado at Sun Mar 20 12:05:07 2022...
    

    2- Is the generated File"/system_top.bit" the right one?

    3- Could I use it  to build BOOT.BIN using Vivado BOOTGEN tool

    thank you for you patient

    and sorry for prolongation

    Regards

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