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FMCDAQ2-EBZ + iW-RainboW-G35M


I faced some issues running DAQ2 with G35M Dev Kit, I hope I can get support and solve these issues.

Setup Environment:

FPGA Package: xczu19eg-ffvc1760-1-i

Vivado/Vitis Version: 2020.1

Git Hub: Master (HDL & no-OS) - Cloned on 4 January 2022

First, I cloned (HDL and no-OS) projects for ZCU102 and compile them using Vivado and Vitis 2020.1 and I succeeded in that.

Then I did some changes in HDL and no-OS to be able to run the ZCU102 reference design with G35M Dev Kit. My changes are listed as follows.

HDL/no-OS Changes:

1. Change FPGA family from xczu9eg-2ffvb1156e to xczu19eg-ffvc1760-1-i

2. Configure PS to be compatible with G35M Dev Kit instead of zcu102 (such as DDR, Disable GPIO)

3. Un-Check (Place SYSREF in IOB) in axi_ad9144_jesd/tx and axi_ad9680_jesd/rx

- I did this because I got a timing issue and I couldn't solve it unless Un-Check (Place SYSREF in IOB). See timing.png below. Is this the right solution?

4. Change package pin in constrains file to be compatible with G35M Dev Kit instead of zcu102

5. Change iostandard in constrains file from LVDS to LVCMOS18 for these pins: rx_sysref_p/n and tx_sysref_p/n

- I did this because those pins are connected to HD bank. So LVDS is not an option, also there is no external termination on board.

- I solve this by configuring ad9523-1 to use LVCOMS18 instead of LVDS. See lvcoms18.png below. Is this the right solution?

lvcoms18.png (line 306 & 320)

Testing Result:

After doing the above changes, I succeeded in bit generation without timing issues and I could program the board from Vitis.

Also, I could see the output from DAC on the analyzer/oscilloscope and I could see the input to ADC on the iio-oscilloscope as well.

Until now, I had two issues I couldn't solve:

1. Currently I am using Option 3 (ADC 500; DAC 500 MSPS) because Option 1 doesn't work. 

The terminal output for option 1 is shown below:

For me, it seems everything is Ok.

So why I am still getting PN9 and PN23 mismatched? 

If the PN9 and PN23 are mismatched, does that mean I will receive not accurate data from ADC?

Should I worry about PN sequence mismatching? How could I solve it?

2. I couldn't run option 1 (ADC 1000; DAC 1000 MSPS). It hangs for some reason and it doesn't show any messages.

The terminal output for option 1 is shown below:

I did some debugging and I found it return Failure here:

I am assuming this happens because the speed grade is (-1). But the Option 2 (ADC 500; DAC 1000 MSPS) is working.

The terminal output for option 2 is shown below:

Please explain why this happened with Option 1 and did not happen with Option 2?  

Is there a way to solve this for Option 1 and can use 1000 MSPS for ADC and DAC?

I hope I could solve the above issue to continuously achieve my project goal.

My final project should have:

1. real input (ADC) and real output (DAC)

2. processing data inside the FPGA is complex (I/Q).

Any guidance to achieve my final project would be helpful.

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  • These are changes in ad9680.c

    int32_t ad9680_setup(struct ad9680_dev **device,
    		     const struct ad9680_init_param *init_param)
    	uint8_t chip_id;
    	uint8_t pll_stat;
    	int32_t ret;
    	struct ad9680_dev *dev;
    	ret = 0;
    	dev = (struct ad9680_dev *)malloc(sizeof(*dev));
    	if (!dev)
    		return -1;
    	/* SPI */
    	ret = no_os_spi_init(&dev->spi_desc, &init_param->spi_init);
    	if(chip_id != AD9680_CHIP_ID) {
    		printf("AD9680: Invalid CHIP ID (0x%x).\n", chip_id);
    		return -1;
    			 0x81);	// RESET
    	// L.M = 4.4
    	ad9680_spi_write(dev,0x200,0x02); //page72: table line 5
    	ad9680_spi_write(dev,0x201,0x01); //page94: decimation by 2
    	ad9680_spi_write(dev,0x310,0x43); //page95: decimation by 2, complex to real disable, gain enable
    	ad9680_spi_write(dev,0x330,0x43); //page96: decimation by 2, complex to real disable, gain enable
    	ad9680_spi_write(dev,0x311,0x00); //page96: only use channel A
    	ad9680_spi_write(dev,0x331,0x05); //page96: only use channel B
    	// fc 75 MHz, fs 500 MHz
    	// DDC1 - NCO
    	ad9680_spi_write(dev,0x314,0x66); //00 to 07 bits
    	ad9680_spi_write(dev,0x315,0x02); //08 to 11 bits
    	// DDC2 - NCO
    	ad9680_spi_write(dev,0x334,0x66); //00 to 07 bits
    	ad9680_spi_write(dev,0x335,0x02); //08 to 11 bits
    	ad9680_spi_write(dev,0x300,0x10); //DDC reset
    	ad9680_spi_write(dev,0x300,0x00); //DDC normal
    			 0x15);	// disable link, ilas enable
    			 0x1f);	// mf-frame-count
    			 0x2d);	// 14-bit
    			 0x2f);	// subclass-1, N'=16
    			 //0x88);	// m=2, l=4, f= 1
    			 0x91);	// m=4, l=4, f= 2
    	if (init_param->lane_rate_kbps < 6250000)
    				 0x10);	// low line rate mode must be enabled
    				 0x00);	// low line rate mode must be disabled
    			 0x14);	// link enable
    	if ((pll_stat & 0x80) != 0x80) {
    		printf("AD9680: PLL is NOT locked!\n");
    		ret = -1;
    	*device = dev;
    	return ret;

    Here the terminal output

    PMIC:	LD01 (BANK 67,68) set to 1.800V
    PMIC:	LD04 (BANK 88,89,90,91) set to 1.800V
    CLK:	Clk synthesizer-1 configured
    CLK:	Clk synthesizer-2 configured
    Powering on FMC & FMC plus
    FMC and FMCP+ powered on
    Xilinx Zynq MP First Stage Boot Loader 
    Release 2020.1   Jun 14 2022  -  11:48:17
    PMU-FW is not running, certain applications may not be supported.
    Available sampling rates:
    	1 - ADC 1000 MSPS; DAC 1000 MSPS
    	2 - ADC  500 MSPS; DAC 1000 MSPS
    	3 - ADC  500 MSPS; DAC  500 MSPS
    	4 - ADC  600 MSPS; DAC  600 MSPS
    	5 - ADC 1000 MSPS; DAC 2000 MSPS (2x interpolation)
    choose an option [default 1]:
    3 - ADC  500 MSPS; DAC  500 MSPS
    ad9144_xcvr: OK (5000000 kHz)
    ad9680_xcvr: OK (5000000 kHz)
    ad9680_adc: Successfully initialized (249996948 Hz)
    ad9144_dac: Successfully initialized (499993896 Hz)
    ad9680_jesd status:
    	Link is enabled
    	Measured Link Clock: 125.000 MHz
    	Reported Link Clock: 125.000 MHz
    	Lane rate: 5000.000 MHz
    	Lane rate / 40: 125.000 MHz
    	LMFC rate: 7.812 MHz
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    ad9144_jesd status:
    	Link is enabled
    	Measured Link Clock: 125.000 MHz
    	Reported Link Clock: 125.000 MHz
    	Lane rate: 5000.000 MHz
    	Lane rate / 40: 125.000 MHz
    	LMFC rate: 15.625 MHz
    	SYNC~: deasserted
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    fmcdaq2_test ad9680 - PN9 sequence mismatch!
    fmcdaq2_test ad9680 - PN23 �Running TinyIIOD server...
                                                          If successful, you may connect an IIO client application by:
                       1. Disconnecting the serial terminal you use to view this message.
                                                                                         2. Connecting the IIO client application using the serial backend configured as shown:
                                                                                	Baudrate: 115200
     	Data size: 8 bits
                             	Parity: none
                                                	Stop bits: 1
                                                                	Flow control: none

    Thank you

  • Hello,

    I reproduced the setup and it seems I have the same error and I'm working to fix it.



  • Dear Paul,

    Is there any news ?


  • Hello,

    I didn't managed to find a solution for this problem, but I'm working on it. Sorry for the delay!



  • Hello, 

    Do you still have this problem? Can you please open another thread if you do so it will be easier to answer?



  • Dear PaulPG,

    The problem still exists and I am going to open a new thread.