FMCDAQ2-EBZ + iW-RainboW-G35M

Hello,

  If you want to use the first option (1000 MSPS for ADC and DAC) you need to modify the following files:

    1. no-OS/drivers/axi_core/jesd204/axi_adxcvr.c

        line 221: you have to add "return ret;"

    2.no-OS/drivers/axi_core/jesd204/xilinx_transceiver.c

       line 453: you have to add "return SUCCESS;"

    3.no-OS/projects/fmcdaq2/src/app/fmcdaq2.c

       line 352: you have to set ".sys_clk_sel = 3,"

  After these changes you can use the sample rate for ADC and DAC at 1000 MSPS.

Thanks,
Paul

Hi Paul,

This is great, now it works for 1000 MSPS for ADC and DAC.

I understand from your changes that the ADC is configured to use QPLL instead of CPLL. Right?

Did you find a solution for PN sequence mismatching?

Hello, 

   Yes, now the ADC is configured to use QPLL instead of CPLL. We are still working on solving the PN sequence mismatch error. 

Thanks,

Paul

Dear Paul,

Did you find solution for PN sequence mismatch error ?

Thanks.

Any news ?

Hello, 

I'm sorry for the delayed response, I'll take a look at this issue and come back with an answer as soon as possible.

Thanks, 

Paul

Hello,
I'm sorry for the delayed response, the fix for the PN9 and PN23 mismatch error can be found here.

Thanks,
Paul

Hello,
I'm sorry for the delayed response, the fix for the PN9 and PN23 mismatch error can be found here.

Thanks,
Paul

Thank you PaulPG.

This solve mismatch error.

Hi Paul,

Mismatch error message disappered, but all data recevied from ADC are always zeros !!

Hi,

After the 0x573 register was changed the ADC needs a soft-reset and that's why you are getting 0 values. I  found out the real problem of the PN mismatch error and now the fix is in the main branch of the hdl repository. The source code from no-OS repository should remain the same, but these updates should be made to the hdl code. I'm sorry for the inconvenience and thank you for your patience!

I've changed the fix link with the final solution.

Dear Paual, 

I did these changes in tpl ip manually from vivado but still I am getting mismatch error.

Should I clone the master and configure it for iwave board again ? (FYI : My current project cloned on january)

Hello,

I would recommend cloning the main branch again and checking again if the error occurs.

Thanks,

Paul

PN Mismatch error is gone if the project compiled with default "make" parameters which is good news, Thank you Paul.

For my case I am using different parameters and the PN Mismatch still happen.

Default Parameters:

• ADC (L=4 and M=2)
• DAC (L=4 and M=2) 

My Parameters:

• ADC (L=4 and M=4)
• DAC (L=4 and M=2) 

Please help me here.

In no-os, I didn't do any changes and I got pn mismatch error.

Then I tried these changes:

- change quick conf. from 0x88 to 0x91

- do setup as shown in page 63 first row, but I choose decimation by 2 instead of 4

The link is up, but pn mismatch still there.

Hello,

Could you please send me the terminal output in this case? 

Thanks,

Paul 

These are changes in ad9680.c

int32_t ad9680_setup(struct ad9680_dev **device,
		     const struct ad9680_init_param *init_param)
{
	uint8_t chip_id;
	uint8_t pll_stat;
	int32_t ret;
	struct ad9680_dev *dev;

	ret = 0;

	dev = (struct ad9680_dev *)malloc(sizeof(*dev));
	if (!dev)
		return -1;

	/* SPI */
	ret = no_os_spi_init(&dev->spi_desc, &init_param->spi_init);

	ad9680_spi_read(dev,
			AD9680_REG_CHIP_ID_LOW,
			&chip_id);
	if(chip_id != AD9680_CHIP_ID) {
		printf("AD9680: Invalid CHIP ID (0x%x).\n", chip_id);
		return -1;
	}

	ad9680_spi_write(dev,
			 AD9680_REG_INTERFACE_CONF_A,
			 0x81);	// RESET
	no_os_mdelay(250);

	//###########################################
	// L.M = 4.4

	ad9680_spi_write(dev,0x200,0x02); //page72: table line 5
	ad9680_spi_write(dev,0x201,0x01); //page94: decimation by 2

	ad9680_spi_write(dev,0x310,0x43); //page95: decimation by 2, complex to real disable, gain enable
	ad9680_spi_write(dev,0x330,0x43); //page96: decimation by 2, complex to real disable, gain enable

	ad9680_spi_write(dev,0x311,0x00); //page96: only use channel A
	ad9680_spi_write(dev,0x331,0x05); //page96: only use channel B

	// fc 75 MHz, fs 500 MHz

	// DDC1 - NCO
	ad9680_spi_write(dev,0x314,0x66); //00 to 07 bits
	ad9680_spi_write(dev,0x315,0x02); //08 to 11 bits

	// DDC2 - NCO
	ad9680_spi_write(dev,0x334,0x66); //00 to 07 bits
	ad9680_spi_write(dev,0x335,0x02); //08 to 11 bits

	ad9680_spi_write(dev,0x300,0x10); //DDC reset
	ad9680_spi_write(dev,0x300,0x00); //DDC normal

	//###########################################


	ad9680_spi_write(dev,
			 AD9680_REG_LINK_CONTROL,
			 0x15);	// disable link, ilas enable
	ad9680_spi_write(dev,
			 AD9680_REG_JESD204B_MF_CTRL,
			 0x1f);	// mf-frame-count
	ad9680_spi_write(dev,
			 AD9680_REG_JESD204B_CSN_CONFIG,
			 0x2d);	// 14-bit
	ad9680_spi_write(dev,
			 AD9680_REG_JESD204B_SUBCLASS_CONFIG,
			 0x2f);	// subclass-1, N'=16
	ad9680_spi_write(dev,
			 AD9680_REG_JESD204B_QUICK_CONFIG,
			 //0x88);	// m=2, l=4, f= 1
			 0x91);	// m=4, l=4, f= 2
	if (init_param->lane_rate_kbps < 6250000)
		ad9680_spi_write(dev,
				 AD9680_REG_JESD204B_LANE_RATE_CTRL,
				 0x10);	// low line rate mode must be enabled
	else
		ad9680_spi_write(dev,
				 AD9680_REG_JESD204B_LANE_RATE_CTRL,
				 0x00);	// low line rate mode must be disabled
	ad9680_spi_write(dev,
			 AD9680_REG_LINK_CONTROL,
			 0x14);	// link enable
	no_os_mdelay(250);

	ad9680_spi_read(dev,
			AD9680_REG_JESD204B_PLL_LOCK_STATUS,
			&pll_stat);
	if ((pll_stat & 0x80) != 0x80) {
		printf("AD9680: PLL is NOT locked!\n");
		ret = -1;
	}

	*device = dev;

	return ret;
}

Here the terminal output

PMIC:	LD01 (BANK 67,68) set to 1.800V
PMIC:	LD04 (BANK 88,89,90,91) set to 1.800V
CLK:	Clk synthesizer-1 configured
CLK:	Clk synthesizer-2 configured
Powering on FMC & FMC plus
FMC and FMCP+ powered on
Xilinx Zynq MP First Stage Boot Loader 
Release 2020.1   Jun 14 2022  -  11:48:17
PMU-FW is not running, certain applications may not be supported.
Available sampling rates:
	1 - ADC 1000 MSPS; DAC 1000 MSPS
	2 - ADC  500 MSPS; DAC 1000 MSPS
	3 - ADC  500 MSPS; DAC  500 MSPS
	4 - ADC  600 MSPS; DAC  600 MSPS
	5 - ADC 1000 MSPS; DAC 2000 MSPS (2x interpolation)
choose an option [default 1]:
3 - ADC  500 MSPS; DAC  500 MSPS
ad9144_xcvr: OK (5000000 kHz)
ad9680_xcvr: OK (5000000 kHz)
ad9680_adc: Successfully initialized (249996948 Hz)
ad9144_dac: Successfully initialized (499993896 Hz)
ad9680_jesd status:
	Link is enabled
	Measured Link Clock: 125.000 MHz
	Reported Link Clock: 125.000 MHz
	Lane rate: 5000.000 MHz
	Lane rate / 40: 125.000 MHz
	LMFC rate: 7.812 MHz
	Link status: DATA
	SYSREF captured: Yes
	SYSREF alignment error: No
ad9144_jesd status:
	Link is enabled
	Measured Link Clock: 125.000 MHz
	Reported Link Clock: 125.000 MHz
	Lane rate: 5000.000 MHz
	Lane rate / 40: 125.000 MHz
	LMFC rate: 15.625 MHz
	SYNC~: deasserted
	Link status: DATA
	SYSREF captured: Yes
	SYSREF alignment error: No
fmcdaq2_test ad9680 - PN9 sequence mismatch!
fmcdaq2_test ad9680 - PN23 �Running TinyIIOD server...
                                                      If successful, you may connect an IIO client application by:
                   1. Disconnecting the serial terminal you use to view this message.
                                                                                     2. Connecting the IIO client application using the serial backend configured as shown:
                                                                            	Baudrate: 115200
 	Data size: 8 bits
                         	Parity: none
                                            	Stop bits: 1
                                                            	Flow control: none

Thank you