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FMCDAQ2-EBZ + iW-RainboW-G35M

Hi,

I faced some issues running DAQ2 with G35M Dev Kit, I hope I can get support and solve these issues.

Setup Environment:

FPGA Package: xczu19eg-ffvc1760-1-i

Vivado/Vitis Version: 2020.1

Git Hub: Master (HDL & no-OS) - Cloned on 4 January 2022

First, I cloned (HDL and no-OS) projects for ZCU102 and compile them using Vivado and Vitis 2020.1 and I succeeded in that.

Then I did some changes in HDL and no-OS to be able to run the ZCU102 reference design with G35M Dev Kit. My changes are listed as follows.

HDL/no-OS Changes:

1. Change FPGA family from xczu9eg-2ffvb1156e to xczu19eg-ffvc1760-1-i

2. Configure PS to be compatible with G35M Dev Kit instead of zcu102 (such as DDR, Disable GPIO)

3. Un-Check (Place SYSREF in IOB) in axi_ad9144_jesd/tx and axi_ad9680_jesd/rx

- I did this because I got a timing issue and I couldn't solve it unless Un-Check (Place SYSREF in IOB). See timing.png below. Is this the right solution?

4. Change package pin in constrains file to be compatible with G35M Dev Kit instead of zcu102

5. Change iostandard in constrains file from LVDS to LVCMOS18 for these pins: rx_sysref_p/n and tx_sysref_p/n

- I did this because those pins are connected to HD bank. So LVDS is not an option, also there is no external termination on board.

- I solve this by configuring ad9523-1 to use LVCOMS18 instead of LVDS. See lvcoms18.png below. Is this the right solution?

lvcoms18.png (line 306 & 320)

Testing Result:

After doing the above changes, I succeeded in bit generation without timing issues and I could program the board from Vitis.

Also, I could see the output from DAC on the analyzer/oscilloscope and I could see the input to ADC on the iio-oscilloscope as well.

Until now, I had two issues I couldn't solve:

1. Currently I am using Option 3 (ADC 500; DAC 500 MSPS) because Option 1 doesn't work. 

The terminal output for option 1 is shown below:

For me, it seems everything is Ok.

So why I am still getting PN9 and PN23 mismatched? 

If the PN9 and PN23 are mismatched, does that mean I will receive not accurate data from ADC?

Should I worry about PN sequence mismatching? How could I solve it?

2. I couldn't run option 1 (ADC 1000; DAC 1000 MSPS). It hangs for some reason and it doesn't show any messages.

The terminal output for option 1 is shown below:

I did some debugging and I found it return Failure here:

I am assuming this happens because the speed grade is (-1). But the Option 2 (ADC 500; DAC 1000 MSPS) is working.

The terminal output for option 2 is shown below:

Please explain why this happened with Option 1 and did not happen with Option 2?  

Is there a way to solve this for Option 1 and can use 1000 MSPS for ADC and DAC?

I hope I could solve the above issue to continuously achieve my project goal.

My final project should have:

1. real input (ADC) and real output (DAC)

2. processing data inside the FPGA is complex (I/Q).

Any guidance to achieve my final project would be helpful.

Parents
  • Sorry for the mistake.

    (Wrong) 1. ...... The terminal output for option 1 is shown below:

    (Correct) 1. ...... The terminal output for option 3 is shown below:

  • Hello,

    We've started looking into this issue.

    1. We're starting by reproducing the setup on ZCU102, as I'm not sure about the status of PN mismatch issue.

    2. By default we are using CPLL for RX and QPLL for TX. I think for -1 FPGAs, CPLL works up to 8.5.Gbps / a VCO_max of 4.25 which is not enough for the 10Gbps rate we use on the DAQ2. 

    You should be able to run both ADC and DAC on the QPLL. We have the same problem on the ZC706 and we are currently working on fixing the issue. 

    The physical layer of the TX path has access to the QPLL reconfiguration while on the RX path only at the CPLL configuration.

    Regards,

    Adrian

Reply
  • Hello,

    We've started looking into this issue.

    1. We're starting by reproducing the setup on ZCU102, as I'm not sure about the status of PN mismatch issue.

    2. By default we are using CPLL for RX and QPLL for TX. I think for -1 FPGAs, CPLL works up to 8.5.Gbps / a VCO_max of 4.25 which is not enough for the 10Gbps rate we use on the DAQ2. 

    You should be able to run both ADC and DAC on the QPLL. We have the same problem on the ZC706 and we are currently working on fixing the issue. 

    The physical layer of the TX path has access to the QPLL reconfiguration while on the RX path only at the CPLL configuration.

    Regards,

    Adrian

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