I would like to use the clock of the XO inside of my fpga design.
I found out this clock is passed trough the RF-chip XTALN--> CLK_OUT (https://www.analog.com/media/en/technical-documentation/data-sheets/ad9363.pdf)
1) How do I assure the CLK_OUT of the RF-chip is the DCXO? Found this in the datasheet of the AD9363
Output Clock. This pin can be configured to output either a buffered version of the external input clock (the digital controlled crystal oscillator (DCXO)) or a divided- down version of the internal ADC sample clock (ADC_CLK)
2) I found that the CLK_OUT is connected to P8 of the zynq 7010. But how do I include this port in the block design in Vivado? The port is already declared in the constrain file.
Can I just add a port and call it CLK_OUT? Or are there any others steps I should take?
3) Is the clock always passed? Or is it only passed when the RF-chip is in use? (transmitting and receiving).