How can I change "ADC Sample Rate" of AD9680 on FMCDAQ2

Hi Riache,

The clock generator on AD-FMCDAQ2-EBZ is AD9523-1 and you can obtain the initialization parameters using the Evaluation software from EVAL-AD9523-1 page.  In this case the closest value I found is 995 MHz (as seen in the picture below). Because the value you want is close to 1000MSPS you only need to change the values for N DIVIDER, R DIVIDER and VCO DIVIDER 1 and the lane rate and ref rate should remain as in the case of 1000MSPS.  Here you can find details on how to calculate all the clock generator parameters.

Thanks,

Paul

Hi, Paul.

Thanks a lot for reply.

I tried to change ADC sample rate (1GSPS to 995MSPS) by using your suggestion.

So, I edited some registers which you mentioned (R,N Divider) by IIO Oscilloscope tool as shown : 

But, ADC capture result was still 1000 samples as shown : 

(I counted 1000 samples by using .csv data)

(If it is applied rightly, it must be 995 samples because time period is set 1 us.)

In another way,

I tried to change frequency in IIO Device Attributes of Debug Tab.

However, It can't be changed too, as shown : 

(I edited the value 1000000000 → 995000000, and then I clicked write button. But the value was returned 1000000000.)

Is there a problem with the method I tried?

Please help me.

Thanks.

I got the 995MSPS sample rate finally.

I edited the value of "adi,pll2-m1-freq" in ".dtsi" file additionally.

So, I got correct 995MSPS and I could see the sample rate in IIO Oscilloscope as shown that : 

Then, I got the captured data of 995 samples during 1us time period.

I could success due to your detail help.

Thank you very much, Paul.

Have a good Christmas day~!

Hi Riache, 

I'm glad that I was able to help you. You too! 

Hi, 

   In this case you only need to modify a single adi-daq2.dtsi file depending on the architecture of the carrier board( arm / arm64 / microblaze). 

Thanks,

Paul

Hello Paul and Riache,

Thank you very much for your interesting discussions!

First of all, I had followed your discussion and the instructions given, since I wanted to change the sample rate of my DAC board. Actually, my DAC board is integrated in EVAL-FMCDAQ3-EBZ card and attached in the Xilinx Zynq ZC706 as the carrier board.

I wanted to change the sample rate of my DAC device because as I have explored the DDS mode can only handle the external (table) file with maximum of 1000000 samples. Meanwhile, since my DAC runs on 1.233 Gsps of sample rate and I want to generate 1 millisecond chirp signal, my file has the sample size of 1233000, which is larger than the maximum sample size DDS mode could handle. 

One of the solutions I had been thinking was to reduce the sample rate of DAC, therefore with the same signal's specification my table file will reduced respectively.

I changed the sample rate of my device as your instruction above. Here is the documentation.

After I changed the sample rate, I restart the IIO Oscilloscope application and found that the DAC sample rate were changed.

However, after I changed the sample rate of my DAC, I couldn't saw any signal generated by my DAC, though I put the DDS mode to "One CW Tone". But, if I reverted back the sample rate to the default value, the oscilloscope shown a sinusoid signal.

Therefore, with this reply, I would like to discuss with you about this problem. If you ever had any experience like this, would you mind sharing it here? That will be very helpful information. Looking forward to hearing from you.

Thank you very much. Have a nice day!

Hello,

I am trying to reproduce your setup and will get back with an answer as soon as possible.

Thanks,

Paul

Hello, 

What is the new sample rate you will need for the DAC? Also, will it be ok if you open a new thread for this question so it will be much easier to follow?

Thanks,

Paul

Hello PaulPG,

Thank you for your reply. I do really appreciate it.

Actually, I tried to change the sample rate below 1 Gsps. Let say, 150 Msps.

My main goal is to reduce the sample size of the signal file; therefore, the sample rate should be reduced as well.

An example of how you can reduce the sample rate of the DAC to 308.333MHz is as follows:

1. Rebuild the HDL project with this command:

make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=1 TX_JESD_M=2

1. Create the BOOT.BIN image using How to build the Zynq boot image BOOT.BIN wiki page.
2. Change the following lines in the adi-daq3.dtsi file:

      50: adi,sysref-k-div = <256>;

      62: adi,sysref-k-div = <256>;

      80: adi,sysref-k-div = <128>;

      90: adi,sysref-k-div = <256>;

      166: adi,jesd-link-mode = <7>;

        4.Rebuild the devicetree file using Building the Zynq Linux kernel and devicetrees from source wiki page.

Thanks,

Paul

Hello PaulPG,

Thanks for your kind response.

I have checked the adi-daq3.dtsi, since my card is FMCDAQ-3 (reference: github.com/.../adi-daq3.dtsi). However, the file contains different lines and content with your example in adi-daq2.dtsi.

Looking forward to your help.

Thanks 

Hello,

I'm sorry, I've updated the link for the dtsi file.

Thanks,

Paul

Hello,

I'm sorry, I've updated the link for the dtsi file.

Thanks,

Paul