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How can I change "ADC Sample Rate" of AD9680 on FMCDAQ2

Hello.

I'm using the AD-FMCDAQ2-EBZ module for utilizing the ADC (AD9680).

The sample rate of ADC was set 1000 MSPS automatically.

I want to change the ADC sample rate to 998MSPS or 997MSPS.

But I don't know whether it is possible or not.

Please let me know how to change the ADC sample rate.

Thanks.

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  • Hi Riache,

    The clock generator on AD-FMCDAQ2-EBZ is AD9523-1 and you can obtain the initialization parameters using the Evaluation software from EVAL-AD9523-1 page.  In this case the closest value I found is 995 MHz (as seen in the picture below). Because the value you want is close to 1000MSPS you only need to change the values for N DIVIDER, R DIVIDER and VCO DIVIDER 1 and the lane rate and ref rate should remain as in the case of 1000MSPS.  Here you can find details on how to calculate all the clock generator parameters.

    Thanks,

    Paul

  • Hi, Paul.

    Thanks a lot for reply.

     

    I tried to change ADC sample rate (1GSPS to 995MSPS) by using your suggestion.

    So, I edited some registers which you mentioned (R,N Divider) by IIO Oscilloscope tool as shown : 

     

    But, ADC capture result was still 1000 samples as shown : 

    (I counted 1000 samples by using .csv data)

    (If it is applied rightly, it must be 995 samples because time period is set 1 us.)

     

    In another way,

    I tried to change frequency in IIO Device Attributes of Debug Tab.

    However, It can't be changed too, as shown : 

    (I edited the value 1000000000 → 995000000, and then I clicked write button. But the value was returned 1000000000.)

      

    Is there a problem with the method I tried?

    Please help me.

     

    Thanks.

  • Hi Riache,

    The method you used is not appropriate in this case because the software will still read 1000 samples.

    One method to test the sample rate is:

    1. Take an external signal generator.
    2. Connect it to a RX channel.
    4. Plot the frequency domain characteristics.
    3. Read the harmonic frequency(using Peak Markers).
    4. Modify the clock generator parameters according to the previous answer.
    5. Plot the frequency domain characteristics again.
    6. Read the harmonic frequency and you will find a different value, which means that the value of the sampling rate has changed.


    If you want this test to be performed without an external source or to be performed with the IIO Oscilloscope software, then you will need to change the clock generator instantiation parameters in the devicetree(.dtsi) file.

    Here you can find the .dtsi file for arm architecture or arm64 architecture.

    I will modify this file and test the 995 MHz sampling rate and come back with a response.

    Thank,
    Paul

Reply
  • Hi Riache,

    The method you used is not appropriate in this case because the software will still read 1000 samples.

    One method to test the sample rate is:

    1. Take an external signal generator.
    2. Connect it to a RX channel.
    4. Plot the frequency domain characteristics.
    3. Read the harmonic frequency(using Peak Markers).
    4. Modify the clock generator parameters according to the previous answer.
    5. Plot the frequency domain characteristics again.
    6. Read the harmonic frequency and you will find a different value, which means that the value of the sampling rate has changed.


    If you want this test to be performed without an external source or to be performed with the IIO Oscilloscope software, then you will need to change the clock generator instantiation parameters in the devicetree(.dtsi) file.

    Here you can find the .dtsi file for arm architecture or arm64 architecture.

    I will modify this file and test the 995 MHz sampling rate and come back with a response.

    Thank,
    Paul

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