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AD9364 fast lock profile for frequency hoping through FPGA


I have implemented Frequency hopping in AD9364 through DSP and it is working. Now Because of some reason i wanted to shift FAST LOCK PROFILE writing through FPGA but Initial  AD9364 configuration is doing by DSP and after that DSP giving the control to FPGA for writing the AD FAST LOCK profile. Is this implementation is OK for AD9364?

FPGA using the same method used by DSP ( using 10 Mhz SPI clock, 8 bit transfer) but its affecting the LVDS clock (3.45 Mhz).

Please anyone help me to go further.

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  • After the initial configuration done by DSP, it store the profile data as a look up table in its internal memory and after that DSP providing profile word  to FPGA through PCIe interface . FPGA driving the 16 AD profile given by DSP  ( 8 TX and 8 RX AD profile for each frequency) to AD with 10Mhz SPI clock.  FPGA have data path to AD9364 through LVDS interface and FPGA to AD profile writing is affecting the AD9364 LVDS clock which was set by DSP at initial configuration.

    Let me know if more details required. please find the capture for AD profile writing from FPGA to AD.