weird phenomenon with the 7z035+adrv9001 reference design

Hi all,

we are using the 7z035+adrv9001 reference design provided by analog devices and we got some weird events that are describes below.

First of all as part of our project we build Tx custom IP cores which comes after the util_dac_2_upack IP (the tx2 transmit chain) , furthermore when we want to operate the board we execute ELF file which operates the TX libiio devices. ->the result of this part is successful.

But after that  we also adding in the Rx2 chain a Rx custom IP which is obviously separate in every aspect from the Tx2 logic (they use different clocks, resets and etc....) , now with the modified reference design which include the Tx2 custom logic and the Rx2 custom logic when we execute the same ELF file as earlier (which use only the tx2 libiio devices and the other devices are shutdown) the signal we get from tx2 port is very disturbed and noisy(while in the Tx2 only reference design the tx2 signal is detectible and cleaner)

with the assumption and verification that the tx and rx logics are separated(in reference design terms) what can be the reason  for the different outcomes?

with best regards .

Dror & Raz 

  • Hi Dror,

    check your timing constraints.

    What is your target sample rate ? 

    Can you please share the output of the report_timing_summary command from an implemented design ?

    Laszlo

  • Hi Dror,

    check your timing constraints.

    What is your target sample rate ? 

    Can you please share the output of the report_timing_summary command from an implemented design ?

    Laszlo

  • Hi Laszlo,

    Can you please share the output of the report_timing_summary command from an implemented design ?

    Laszlo

    What is your target sample rate ? 

    basicly our  two custom IP cores( the extended logic besides the ADI reference design logic) are needs to have clock of 51.2MHz , the "source" of this clock is generated via the dac_2_clk & adc_2_clk ports of the AXI_ADRV9002 IP , but before the clocks are getting into the two custom IP clock ports ( RX IP and TX IP custom logic) we need to empeshize that the clock which the axi_adrv9002 is generate is not 51.2MHz but actual 102.4MHz( due to the profile file that we load into the PS ) and therefore what we did is to export the  dac_2_clk & adc_2_clk ports outside of the wrapper level into the top level and divide the clock by 2 via BUFR and after that BUFG modules and then import the new clock signals into the relevant clocks which needed the 51.2MHz clock.

    thanks.

    Dror & Raz

  • The output of report_timing_summary tcl command is a detailed text format.  The capture you shared is only a summary.   Please share at least the "Clock summary" tab. The complete text file would be ideal.

    Thank you,

    Laszlo

  • Hi Laszlo this is the compelte texet file of the command

    report_timing_summary
    INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
    INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
    WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
    Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
    ------------------------------------------------------------------------------------
    | Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
    | Date         : Tue Dec 14 12:09:14 2021
    | Host         : DESKTOP-VVL5N7G running 64-bit major release  (build 9200)
    | Command      : report_timing_summary
    | Design       : system_top
    | Device       : 7z035i-fbg676
    | Speed File   : -2L  PRODUCTION 1.11 2014-09-11
    ------------------------------------------------------------------------------------
    
    Timing Summary Report
    
    ------------------------------------------------------------------------------------------------
    | Timer Settings
    | --------------
    ------------------------------------------------------------------------------------------------
    
      Enable Multi Corner Analysis               :  Yes
      Enable Pessimism Removal                   :  Yes
      Pessimism Removal Resolution               :  Nearest Common Node
      Enable Input Delay Default Clock           :  No
      Enable Preset / Clear Arcs                 :  No
      Disable Flight Delays                      :  No
      Ignore I/O Paths                           :  No
      Timing Early Launch at Borrowing Latches   :  No
      Borrow Time for Max Delay Exceptions       :  Yes
    
      Corner  Analyze    Analyze    
      Name    Max Paths  Min Paths  
      ------  ---------  ---------  
      Slow    Yes        Yes        
      Fast    Yes        Yes        
    
    
    
    check_timing report
    
    Table of Contents
    -----------------
    1. checking no_clock
    2. checking constant_clock
    3. checking pulse_width_clock
    4. checking unconstrained_internal_endpoints
    5. checking no_input_delay
    6. checking no_output_delay
    7. checking multiple_clock
    8. checking generated_clocks
    9. checking loops
    10. checking partial_input_delay
    11. checking partial_output_delay
    12. checking latch_loops
    
    1. checking no_clock
    --------------------
     There are 1121 register/latch pins with no clock driven by root clock pin: dbg_hub/sl_iport0_o[1] (HIGH)
    
     There are 1302 register/latch pins with no clock driven by root clock pin: dbg_hub/sl_iport1_o[1] (HIGH)
    
     There are 1445 register/latch pins with no clock driven by root clock pin: dbg_hub/sl_iport2_o[1] (HIGH)
    
     There are 1365 register/latch pins with no clock driven by root clock pin: dbg_hub/sl_iport3_o[1] (HIGH)
    
     There are 1254 register/latch pins with no clock driven by root clock pin: dbg_hub/sl_iport4_o[1] (HIGH)
    
     There are 1146 register/latch pins with no clock driven by root clock pin: dbg_hub/sl_iport5_o[1] (HIGH)
    
    
    2. checking constant_clock
    --------------------------
     There are 0 register/latch pins with constant_clock.
    
    
    3. checking pulse_width_clock
    -----------------------------
     There are 0 register/latch pins which need pulse_width check
    
    
    4. checking unconstrained_internal_endpoints
    --------------------------------------------
     There are 12047 pins that are not constrained for maximum delay. (HIGH)
    
     There are 0 pins that are not constrained for maximum delay due to constant clock.
    
    
    5. checking no_input_delay
    --------------------------
     There are 12 input ports with no input delay specified. (HIGH)
    
     There are 0 input ports with no input delay but user has a false path constraint.
    
    
    6. checking no_output_delay
    ---------------------------
     There are 51 ports with no output delay specified. (HIGH)
    
     There are 0 ports with no output delay but user has a false path constraint
    
     There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
    
    
    7. checking multiple_clock
    --------------------------
     There are 0 register/latch pins with multiple clocks.
    
    
    8. checking generated_clocks
    ----------------------------
     There are 0 generated clocks that are not connected to a clock source.
    
    
    9. checking loops
    -----------------
     There are 0 combinational loops in the design.
    
    
    10. checking partial_input_delay
    --------------------------------
     There are 0 input ports with partial input delay specified.
    
    
    11. checking partial_output_delay
    ---------------------------------
     There are 0 ports with partial output delay specified.
    
    
    12. checking latch_loops
    ------------------------
     There are 0 combinational latch loops in the design through latch input
    
    
    
    ------------------------------------------------------------------------------------------------
    | Design Timing Summary
    | ---------------------
    ------------------------------------------------------------------------------------------------
    
        WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
        -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
          3.502        0.000                      0               395750       -3.402     -633.956                  20367               395441        0.264        0.000                       0                167209  
    
    
    Timing constraints are not met.
    
    
    ------------------------------------------------------------------------------------------------
    | Clock Summary
    | -------------
    ------------------------------------------------------------------------------------------------
    
    Clock                                 Waveform(ns)         Period(ns)      Frequency(MHz)
    -----                                 ------------         ----------      --------------
    clk_fpga_0                            {0.000 5.000}        10.000          100.000         
    clk_fpga_1                            {0.000 2.500}        5.000           200.000         
      clk_out1_system_sys_audio_clkgen_0  {0.000 40.690}       81.380          12.288          
      clkfbout_system_sys_audio_clkgen_0  {0.000 22.500}       45.000          22.222          
      mmcm_clk_0_s                        {0.000 3.367}        6.735           148.485         
      mmcm_clk_1_s                        {0.000 3.367}        6.735           148.485         
      mmcm_clk_2_s                        {0.000 1.122}        2.245           445.455         
      mmcm_fb_clk_s                       {0.000 27.500}       55.000          18.182          
    rx1_dclk_out                          {0.000 6.250}        12.500          80.000          
      adc_clk_div_s                       {0.000 25.000}       50.000          20.000          
    rx2_dclk_out                          {0.000 6.250}        12.500          80.000          
      adc_clk_div_s_1                     {0.000 25.000}       50.000          20.000          
        adc_clk_in_s                      {0.000 50.000}       100.000         10.000          
        dac_clk_in_s                      {0.000 50.000}       100.000         10.000          
    spi0_clk                              {0.000 20.000}       40.000          25.000          
    spi1_clk                              {0.000 20.000}       40.000          25.000          
    tx1_dclk_out                          {0.000 6.250}        12.500          80.000          
    tx2_dclk_out                          {0.000 6.250}        12.500          80.000          
    
    
    ------------------------------------------------------------------------------------------------
    | Intra Clock Table
    | -----------------
    ------------------------------------------------------------------------------------------------
    
    Clock                                     WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -----                                     -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
    clk_fpga_0                                  6.300        0.000                      0                61018       -0.091     -194.061                  10440                61018        2.500        0.000                       0                 21520  
    clk_fpga_1                                  3.502        0.000                      0                   55       -0.006       -0.048                      8                   55        0.264        0.000                       0                    47  
      clk_out1_system_sys_audio_clkgen_0       79.880        0.000                      0                   61       -0.057       -0.978                     22                   61       39.922        0.000                       0                    37  
      clkfbout_system_sys_audio_clkgen_0                                                                                                                                                   43.929        0.000                       0                     2  
      mmcm_clk_0_s                              3.505        0.000                      0                 1418       -0.019       -0.338                     32                 1418        2.725        0.000                       0                   760  
      mmcm_clk_1_s                                                                                                                                                                          5.326        0.000                       0                     2  
      mmcm_clk_2_s                                                                                                                                                                          0.836        0.000                       0                     2  
      mmcm_fb_clk_s                                                                                                                                                                        45.000        0.000                       0                     3  
    rx1_dclk_out                                                                                                                                                                           11.251        0.000                       0                    12  
      adc_clk_div_s                            47.272        0.000                      0                14540       -0.131      -12.607                    505                14540       24.232        0.000                       0                 12416  
    rx2_dclk_out                                                                                                                                                                           11.251        0.000                       0                    12  
      adc_clk_div_s_1                          47.332        0.000                      0                11574       -0.237      -19.889                    957                11574       24.358        0.000                       0                  9091  
        adc_clk_in_s                           93.144        0.000                      0                73447       -0.091      -90.278                   4156                73447       49.232        0.000                       0                 23402  
        dac_clk_in_s                           92.507        0.000                      0               227288       -0.043      -86.647                   4179               227288       49.232        0.000                       0                 99903  
    
    
    ------------------------------------------------------------------------------------------------
    | Inter Clock Table
    | -----------------
    ------------------------------------------------------------------------------------------------
    
    From Clock                          To Clock                                WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
    ----------                          --------                                -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
    clk_out1_system_sys_audio_clkgen_0  clk_fpga_0                                9.082        0.000                      0                    4                                                                        
    adc_clk_div_s                       clk_fpga_0                                8.253        0.000                      0                   61                                                                        
    adc_clk_div_s_1                     clk_fpga_0                                9.249        0.000                      0                   11                                                                        
    adc_clk_in_s                        clk_fpga_0                                8.253        0.000                      0                   51                                                                        
    clk_fpga_0                          clk_out1_system_sys_audio_clkgen_0       80.462        0.000                      0                    5                                                                        
    clk_fpga_0                          adc_clk_div_s                             9.426        0.000                      0                  129                                                                        
    adc_clk_div_s_1                     adc_clk_div_s                            45.481        0.000                      0                   34       -3.402     -115.289                     34                   34  
    clk_fpga_0                          adc_clk_div_s_1                           9.432        0.000                      0                   15                                                                        
    adc_clk_div_s                       adc_clk_div_s_1                          45.476        0.000                      0                   34       -3.354     -113.821                     34                   34  
    adc_clk_in_s                        adc_clk_div_s_1                          47.180        0.000                      0                   47        0.637        0.000                      0                    1  
    dac_clk_in_s                        adc_clk_div_s_1                          99.485        0.000                      0                   40                                                                        
    clk_fpga_0                          adc_clk_in_s                              9.426        0.000                      0                  119                                                                        
    adc_clk_div_s_1                     adc_clk_in_s                             49.485        0.000                      0                   46                                                                        
    adc_clk_div_s_1                     dac_clk_in_s                             49.485        0.000                      0                   40                                                                        
    
    
    ------------------------------------------------------------------------------------------------
    | Other Path Groups Table
    | -----------------------
    ------------------------------------------------------------------------------------------------
    
    Path Group         From Clock         To Clock               WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
    ----------         ----------         --------               -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
    **async_default**  adc_clk_div_s      adc_clk_div_s           48.491        0.000                      0                 1113        0.198        0.000                      0                 1113  
    **async_default**  adc_clk_div_s_1    adc_clk_div_s_1         48.514        0.000                      0                  973        0.178        0.000                      0                  973  
    **async_default**  adc_clk_in_s       adc_clk_in_s            99.008        0.000                      0                   66        0.176        0.000                      0                   66  
    **async_default**  clk_fpga_0         clk_fpga_0               8.301        0.000                      0                 3529        0.178        0.000                      0                 3529  
    **async_default**  dac_clk_in_s       dac_clk_in_s            99.008        0.000                      0                   66        0.176        0.000                      0                   66  
    **async_default**  mmcm_clk_0_s       mmcm_clk_0_s             5.623        0.000                      0                  228        0.227        0.000                      0                  228  
    
    
    ------------------------------------------------------------------------------------------------
    | Timing Details
    | --------------
    ------------------------------------------------------------------------------------------------
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  clk_fpga_0
      To Clock:  clk_fpga_0
    
    Setup :            0  Failing Endpoints,  Worst Slack        6.300ns,  Total Violation        0.000ns
    Hold  :        10440  Failing Endpoints,  Worst Slack       -0.091ns,  Total Violation     -194.061ns
    PW    :            0  Failing Endpoints,  Worst Slack        2.500ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             6.300ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/axi_iic_fmc/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]/C
                                (rising edge-triggered cell FDRE clocked by clk_fpga_0  {rise@0.000ns fall@5.000ns period=10.000ns})
      Destination:            i_system_wrapper/system_i/sys_ps7/inst/PS7_i/MAXIGP0WREADY
                                (rising edge-triggered cell PS7 clocked by clk_fpga_0  {rise@0.000ns fall@5.000ns period=10.000ns})
      Path Group:             clk_fpga_0
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            10.000ns  (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
      Data Path Delay:        2.856ns  (logic 0.575ns (20.130%)  route 2.281ns (79.870%))
      Logic Levels:           6  (LUT2=1 LUT4=2 LUT5=1 LUT6=2)
      Clock Path Skew:        -0.021ns (DCD - SCD + CPR)
        Destination Clock Delay (DCD):    0.880ns = ( 10.880 - 10.000 ) 
        Source Clock Delay      (SCD):    0.932ns
        Clock Pessimism Removal (CPR):    0.031ns
      Clock Uncertainty:      0.154ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
        Total System Jitter     (TSJ):    0.071ns
        Total Input Jitter      (TIJ):    0.300ns
        Discrete Jitter          (DJ):    0.000ns
        Phase Error              (PE):    0.000ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock clk_fpga_0 rise edge)
                                                          0.000     0.000 r  
        PS7_X0Y0             PS7                          0.000     0.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
                             net (fo=1, unplaced)         0.419     0.419    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
                             BUFG (Prop_bufg_I_O)         0.093     0.512 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
                             net (fo=21577, unplaced)     0.419     0.932    i_system_wrapper/system_i/axi_iic_fmc/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_aclk
                             FDRE                                         r  i_system_wrapper/system_i/axi_iic_fmc/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]/C
      -------------------------------------------------------------------    -------------------
                             FDRE (Prop_fdre_C_Q)         0.233     1.165 f  i_system_wrapper/system_i/axi_iic_fmc/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]/Q
                             net (fo=5, unplaced)         0.444     1.609    i_system_wrapper/system_i/axi_iic_fmc/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_awready_0[0]
                             LUT4 (Prop_lut4_I1_O)        0.123     1.732 f  i_system_wrapper/system_i/axi_iic_fmc/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_wready_INST_0_i_1/O
                             net (fo=2, unplaced)         0.281     2.013    i_system_wrapper/system_i/axi_iic_fmc/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_wready_INST_0_i_1_n_0
                             LUT4 (Prop_lut4_I0_O)        0.043     2.056 r  i_system_wrapper/system_i/axi_iic_fmc/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_wready_INST_0/O
                             net (fo=7, unplaced)         0.305     2.361    i_system_wrapper/system_i/axi_cpu_interconnect/xbar/inst/gen_sasd.crossbar_sasd_0/splitter_aw/m_axi_wready[5]
                             LUT6 (Prop_lut6_I0_O)        0.043     2.404 r  i_system_wrapper/system_i/axi_cpu_interconnect/xbar/inst/gen_sasd.crossbar_sasd_0/splitter_aw/s_axi_wready[0]_INST_0_i_8/O
                             net (fo=2, unplaced)         0.281     2.685    i_system_wrapper/system_i/axi_cpu_interconnect/xbar/inst/gen_sasd.crossbar_sasd_0/splitter_aw/m_axi_wready_7_sn_1
                             LUT5 (Prop_lut5_I4_O)        0.043     2.728 r  i_system_wrapper/system_i/axi_cpu_interconnect/xbar/inst/gen_sasd.crossbar_sasd_0/splitter_aw/s_axi_wready[0]_INST_0_i_4/O
                             net (fo=1, unplaced)         0.270     2.998    i_system_wrapper/system_i/axi_cpu_interconnect/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/s_axi_wready[0]_2
                             LUT6 (Prop_lut6_I3_O)        0.043     3.041 f  i_system_wrapper/system_i/axi_cpu_interconnect/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/s_axi_wready[0]_INST_0_i_1/O
                             net (fo=2, unplaced)         0.281     3.322    i_system_wrapper/system_i/axi_cpu_interconnect/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/m_ready_d_reg[1]
                             LUT2 (Prop_lut2_I1_O)        0.047     3.369 r  i_system_wrapper/system_i/axi_cpu_interconnect/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/s_axi_wready[0]_INST_0/O
                             net (fo=1, unplaced)         0.419     3.788    i_system_wrapper/system_i/sys_ps7/inst/M_AXI_GP0_WREADY
        PS7_X0Y0             PS7                                          r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/MAXIGP0WREADY
      -------------------------------------------------------------------    -------------------
    
                             (clock clk_fpga_0 rise edge)
                                                         10.000    10.000 r  
        PS7_X0Y0             PS7                          0.000    10.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
                             net (fo=1, unplaced)         0.398    10.398    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
                             BUFG (Prop_bufg_I_O)         0.083    10.481 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
                             net (fo=21577, unplaced)     0.398    10.880    i_system_wrapper/system_i/sys_ps7/inst/M_AXI_GP0_ACLK
        PS7_X0Y0             PS7                                          r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/MAXIGP0ACLK
                             clock pessimism              0.031    10.911    
                             clock uncertainty           -0.154    10.757    
        PS7_X0Y0             PS7 (Setup_ps7_MAXIGP0ACLK_MAXIGP0WREADY)
                                                         -0.668    10.089    i_system_wrapper/system_i/sys_ps7/inst/PS7_i
      -------------------------------------------------------------------
                             required time                         10.089    
                             arrival time                          -3.788    
      -------------------------------------------------------------------
                             slack                                  6.300    
    
    
    
    
    
    Min Delay Paths
    --------------------------------------------------------------------------------------
    Slack (VIOLATED) :        -0.091ns  (arrival time - required time)
      Source:                 i_system_wrapper/system_i/axi_hp1_interconnect/inst/s02_entry_pipeline/s02_mmu/inst/r_sreg/m_vector_i_reg[1059]/C
                                (rising edge-triggered cell FDRE clocked by clk_fpga_0  {rise@0.000ns fall@5.000ns period=10.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001_tx1_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_mem/m_ram_reg/DIADI[0]
                                (rising edge-triggered cell RAMB36E1 clocked by clk_fpga_0  {rise@0.000ns fall@5.000ns period=10.000ns})
      Path Group:             clk_fpga_0
      Path Type:              Hold (Min at Fast Process Corner)
      Requirement:            0.000ns  (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
      Data Path Delay:        0.312ns  (logic 0.104ns (33.332%)  route 0.208ns (66.668%))
      Logic Levels:           0  
      Clock Path Skew:        0.145ns (DCD - SCD - CPR)
        Destination Clock Delay (DCD):    0.468ns
        Source Clock Delay      (SCD):    0.308ns
        Clock Pessimism Removal (CPR):    0.015ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock clk_fpga_0 rise edge)
                                                          0.000     0.000 r  
        PS7_X0Y0             PS7                          0.000     0.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
                             net (fo=1, unplaced)         0.208     0.208    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
                             BUFG (Prop_bufg_I_O)         0.026     0.234 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
                             net (fo=21577, unplaced)     0.074     0.308    i_system_wrapper/system_i/axi_hp1_interconnect/inst/s02_entry_pipeline/s02_mmu/inst/r_sreg/aclk
                             FDRE                                         r  i_system_wrapper/system_i/axi_hp1_interconnect/inst/s02_entry_pipeline/s02_mmu/inst/r_sreg/m_vector_i_reg[1059]/C
      -------------------------------------------------------------------    -------------------
                             FDRE (Prop_fdre_C_Q)         0.104     0.412 r  i_system_wrapper/system_i/axi_hp1_interconnect/inst/s02_entry_pipeline/s02_mmu/inst/r_sreg/m_vector_i_reg[1059]/Q
                             net (fo=1, unplaced)         0.208     0.620    i_system_wrapper/system_i/axi_adrv9001_tx1_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_mem/m_src_axi_rdata[0]
                             RAMB36E1                                     r  i_system_wrapper/system_i/axi_adrv9001_tx1_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_mem/m_ram_reg/DIADI[0]
      -------------------------------------------------------------------    -------------------
    
                             (clock clk_fpga_0 rise edge)
                                                          0.000     0.000 r  
        PS7_X0Y0             PS7                          0.000     0.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
                             net (fo=1, unplaced)         0.219     0.219    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
                             BUFG (Prop_bufg_I_O)         0.030     0.249 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
                             net (fo=21577, unplaced)     0.219     0.468    i_system_wrapper/system_i/axi_adrv9001_tx1_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_mem/m_src_axi_aclk
                             RAMB36E1                                     r  i_system_wrapper/system_i/axi_adrv9001_tx1_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_mem/m_ram_reg/CLKBWRCLK
                             clock pessimism             -0.015     0.453    
                             RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_DIADI[0])
                                                          0.258     0.711    i_system_wrapper/system_i/axi_adrv9001_tx1_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_mem/m_ram_reg
      -------------------------------------------------------------------
                             required time                         -0.711    
                             arrival time                           0.620    
      -------------------------------------------------------------------
                             slack                                 -0.091    
    
    
    
    
    
    Pulse Width Checks
    --------------------------------------------------------------------------------------
    Clock Name:         clk_fpga_0
    Waveform(ns):       { 0.000 5.000 }
    Period(ns):         10.000
    Sources:            { i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0] }
    
    Check Type        Corner  Lib Pin          Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location  Pin
    Min Period        n/a     MMCME2_ADV/DCLK  n/a            4.999         10.000      5.001                i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/DCLK
    Low Pulse Width   Slow    MMCME2_ADV/DCLK  n/a            2.500         5.000       2.500                i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/DCLK
    High Pulse Width  Slow    MMCME2_ADV/DCLK  n/a            2.500         5.000       2.501                i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/DCLK
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  clk_fpga_1
      To Clock:  clk_fpga_1
    
    Setup :            0  Failing Endpoints,  Worst Slack        3.502ns,  Total Violation        0.000ns
    Hold  :            8  Failing Endpoints,  Worst Slack       -0.006ns,  Total Violation       -0.048ns
    PW    :            0  Failing Endpoints,  Worst Slack        0.264ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             3.502ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/sys_200m_rstgen/U0/EXT_LPF/POR_SRL_I/CLK
                                (rising edge-triggered cell SRL16E clocked by clk_fpga_1  {rise@0.000ns fall@2.500ns period=5.000ns})
      Destination:            i_system_wrapper/system_i/sys_200m_rstgen/U0/EXT_LPF/lpf_int_reg/D
                                (rising edge-triggered cell FDRE clocked by clk_fpga_1  {rise@0.000ns fall@2.500ns period=5.000ns})
      Path Group:             clk_fpga_1
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            5.000ns  (clk_fpga_1 rise@5.000ns - clk_fpga_1 rise@0.000ns)
      Data Path Delay:        1.313ns  (logic 1.043ns (79.436%)  route 0.270ns (20.564%))
      Logic Levels:           1  (LUT4=1)
      Clock Path Skew:        -0.145ns (DCD - SCD + CPR)
        Destination Clock Delay (DCD):    0.920ns = ( 5.920 - 5.000 ) 
        Source Clock Delay      (SCD):    1.096ns
        Clock Pessimism Removal (CPR):    0.031ns
      Clock Uncertainty:      0.083ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
        Total System Jitter     (TSJ):    0.071ns
        Total Input Jitter      (TIJ):    0.150ns
        Discrete Jitter          (DJ):    0.000ns
        Phase Error              (PE):    0.000ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock clk_fpga_1 rise edge)
                                                          0.000     0.000 r  
        PS7_X0Y0             PS7                          0.000     0.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
                             net (fo=1, unplaced)         0.419     0.419    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
                             BUFG (Prop_bufg_I_O)         0.093     0.512 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
                             net (fo=46, unplaced)        0.584     1.096    i_system_wrapper/system_i/sys_200m_rstgen/U0/EXT_LPF/slowest_sync_clk
                             SRL16E                                       r  i_system_wrapper/system_i/sys_200m_rstgen/U0/EXT_LPF/POR_SRL_I/CLK
      -------------------------------------------------------------------    -------------------
                             SRL16E (Prop_srl16e_CLK_Q)
                                                          1.000     2.096 r  i_system_wrapper/system_i/sys_200m_rstgen/U0/EXT_LPF/POR_SRL_I/Q
                             net (fo=1, unplaced)         0.270     2.366    i_system_wrapper/system_i/sys_200m_rstgen/U0/EXT_LPF/Q
                             LUT4 (Prop_lut4_I3_O)        0.043     2.409 r  i_system_wrapper/system_i/sys_200m_rstgen/U0/EXT_LPF/lpf_int0/O
                             net (fo=1, unplaced)         0.000     2.409    i_system_wrapper/system_i/sys_200m_rstgen/U0/EXT_LPF/lpf_int0__0
                             FDRE                                         r  i_system_wrapper/system_i/sys_200m_rstgen/U0/EXT_LPF/lpf_int_reg/D
      -------------------------------------------------------------------    -------------------
    
                             (clock clk_fpga_1 rise edge)
                                                          5.000     5.000 r  
        PS7_X0Y0             PS7                          0.000     5.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
                             net (fo=1, unplaced)         0.398     5.398    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
                             BUFG (Prop_bufg_I_O)         0.083     5.481 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
                             net (fo=46, unplaced)        0.439     5.920    i_system_wrapper/system_i/sys_200m_rstgen/U0/EXT_LPF/slowest_sync_clk
                             FDRE                                         r  i_system_wrapper/system_i/sys_200m_rstgen/U0/EXT_LPF/lpf_int_reg/C
                             clock pessimism              0.031     5.951    
                             clock uncertainty           -0.083     5.869    
                             FDRE (Setup_fdre_C_D)        0.043     5.912    i_system_wrapper/system_i/sys_200m_rstgen/U0/EXT_LPF/lpf_int_reg
      -------------------------------------------------------------------
                             required time                          5.912    
                             arrival time                          -2.409    
      -------------------------------------------------------------------
                             slack                                  3.502    
    
    
    
    
    
    Min Delay Paths
    --------------------------------------------------------------------------------------
    Slack (VIOLATED) :        -0.006ns  (arrival time - required time)
      Source:                 i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_delay_cntrl_rx1/i_delay_rst_reg/rst_async_d1_reg/C
                                (rising edge-triggered cell FDPE clocked by clk_fpga_1  {rise@0.000ns fall@2.500ns period=5.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_delay_cntrl_rx1/i_delay_rst_reg/rst_async_d2_reg/D
                                (rising edge-triggered cell FDPE clocked by clk_fpga_1  {rise@0.000ns fall@2.500ns period=5.000ns})
      Path Group:             clk_fpga_1
      Path Type:              Hold (Min at Fast Process Corner)
      Requirement:            0.000ns  (clk_fpga_1 rise@0.000ns - clk_fpga_1 rise@0.000ns)
      Data Path Delay:        0.158ns  (logic 0.104ns (65.800%)  route 0.054ns (34.200%))
      Logic Levels:           0  
      Clock Path Skew:        0.145ns (DCD - SCD - CPR)
        Destination Clock Delay (DCD):    0.508ns
        Source Clock Delay      (SCD):    0.348ns
        Clock Pessimism Removal (CPR):    0.015ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock clk_fpga_1 rise edge)
                                                          0.000     0.000 r  
        PS7_X0Y0             PS7                          0.000     0.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
                             net (fo=1, unplaced)         0.208     0.208    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
                             BUFG (Prop_bufg_I_O)         0.026     0.234 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
                             net (fo=46, unplaced)        0.114     0.348    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_delay_cntrl_rx1/i_delay_rst_reg/delay_clk
                             FDPE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_delay_cntrl_rx1/i_delay_rst_reg/rst_async_d1_reg/C
      -------------------------------------------------------------------    -------------------
                             FDPE (Prop_fdpe_C_Q)         0.104     0.452 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_delay_cntrl_rx1/i_delay_rst_reg/rst_async_d1_reg/Q
                             net (fo=1, unplaced)         0.054     0.506    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_delay_cntrl_rx1/i_delay_rst_reg/rst_async_d1
                             FDPE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_delay_cntrl_rx1/i_delay_rst_reg/rst_async_d2_reg/D
      -------------------------------------------------------------------    -------------------
    
                             (clock clk_fpga_1 rise edge)
                                                          0.000     0.000 r  
        PS7_X0Y0             PS7                          0.000     0.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
                             net (fo=1, unplaced)         0.219     0.219    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
                             BUFG (Prop_bufg_I_O)         0.030     0.249 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
                             net (fo=46, unplaced)        0.259     0.508    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_delay_cntrl_rx1/i_delay_rst_reg/delay_clk
                             FDPE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_delay_cntrl_rx1/i_delay_rst_reg/rst_async_d2_reg/C
                             clock pessimism             -0.015     0.493    
                             FDPE (Hold_fdpe_C_D)         0.019     0.512    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_delay_cntrl_rx1/i_delay_rst_reg/rst_async_d2_reg
      -------------------------------------------------------------------
                             required time                         -0.512    
                             arrival time                           0.506    
      -------------------------------------------------------------------
                             slack                                 -0.006    
    
    
    
    
    
    Pulse Width Checks
    --------------------------------------------------------------------------------------
    Clock Name:         clk_fpga_1
    Waveform(ns):       { 0.000 2.500 }
    Period(ns):         5.000
    Sources:            { i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1] }
    
    Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location  Pin
    Min Period        n/a     IDELAYCTRL/REFCLK  n/a            2.438         5.000       2.562                i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_serdes/i_delay_ctrl/REFCLK
    Max Period        n/a     IDELAYCTRL/REFCLK  n/a            5.264         5.000       0.264                i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_serdes/i_delay_ctrl/REFCLK
    Low Pulse Width   Fast    MMCME2_ADV/CLKIN1  n/a            1.400         2.500       1.100                i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKIN1
    High Pulse Width  Slow    MMCME2_ADV/CLKIN1  n/a            1.400         2.500       1.100                i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKIN1
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  clk_out1_system_sys_audio_clkgen_0
      To Clock:  clk_out1_system_sys_audio_clkgen_0
    
    Setup :            0  Failing Endpoints,  Worst Slack       79.880ns,  Total Violation        0.000ns
    Hold  :           22  Failing Endpoints,  Worst Slack       -0.057ns,  Total Violation       -0.978ns
    PW    :            0  Failing Endpoints,  Worst Slack       39.922ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             79.880ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/tx_sync/cdc_sync_stage3_tick_reg/C
                                (rising edge-triggered cell FDRE clocked by clk_out1_system_sys_audio_clkgen_0  {rise@0.000ns fall@40.690ns period=81.380ns})
      Destination:            i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/tx_sync/out_data_reg[0]/CE
                                (rising edge-triggered cell FDRE clocked by clk_out1_system_sys_audio_clkgen_0  {rise@0.000ns fall@40.690ns period=81.380ns})
      Path Group:             clk_out1_system_sys_audio_clkgen_0
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            81.380ns  (clk_out1_system_sys_audio_clkgen_0 rise@81.380ns - clk_out1_system_sys_audio_clkgen_0 rise@0.000ns)
      Data Path Delay:        0.941ns  (logic 0.356ns (37.832%)  route 0.585ns (62.168%))
      Logic Levels:           1  (LUT2=1)
      Clock Path Skew:        -0.145ns (DCD - SCD + CPR)
        Destination Clock Delay (DCD):    1.914ns = ( 83.294 - 81.380 ) 
        Source Clock Delay      (SCD):    2.270ns
        Clock Pessimism Removal (CPR):    0.211ns
      Clock Uncertainty:      0.215ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
        Total System Jitter     (TSJ):    0.071ns
        Discrete Jitter          (DJ):    0.424ns
        Phase Error              (PE):    0.000ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock clk_out1_system_sys_audio_clkgen_0 rise edge)
                                                          0.000     0.000 r  
        PS7_X0Y0             PS7                          0.000     0.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
                             net (fo=1, unplaced)         0.419     0.419    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
                             BUFG (Prop_bufg_I_O)         0.093     0.512 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
                             net (fo=46, unplaced)        0.584     1.096    i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1
                             MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                          0.077     1.173 r  i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKOUT0
                             net (fo=1, unplaced)         0.419     1.593    i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out1_system_sys_audio_clkgen_0
                             BUFG (Prop_bufg_I_O)         0.093     1.686 r  i_system_wrapper/system_i/sys_audio_clkgen/inst/clkout1_buf/O
                             net (fo=35, unplaced)        0.584     2.270    i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/tx_sync/data_clk_i
                             FDRE                                         r  i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/tx_sync/cdc_sync_stage3_tick_reg/C
      -------------------------------------------------------------------    -------------------
                             FDRE (Prop_fdre_C_Q)         0.233     2.503 r  i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/tx_sync/cdc_sync_stage3_tick_reg/Q
                             net (fo=3, unplaced)         0.285     2.788    i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/tx_sync/cdc_sync_stage3_tick_1
                             LUT2 (Prop_lut2_I0_O)        0.123     2.911 r  i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/tx_sync/out_data[4]_i_1/O
                             net (fo=5, unplaced)         0.300     3.211    i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/tx_sync/out_data[4]_i_1_n_0
                             FDRE                                         r  i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/tx_sync/out_data_reg[0]/CE
      -------------------------------------------------------------------    -------------------
    
                             (clock clk_out1_system_sys_audio_clkgen_0 rise edge)
                                                         81.380    81.380 r  
        PS7_X0Y0             PS7                          0.000    81.380 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
                             net (fo=1, unplaced)         0.398    81.779    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
                             BUFG (Prop_bufg_I_O)         0.083    81.862 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
                             net (fo=46, unplaced)        0.439    82.301    i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1
                             MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                          0.073    82.374 r  i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKOUT0
                             net (fo=1, unplaced)         0.398    82.772    i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out1_system_sys_audio_clkgen_0
                             BUFG (Prop_bufg_I_O)         0.083    82.855 r  i_system_wrapper/system_i/sys_audio_clkgen/inst/clkout1_buf/O
                             net (fo=35, unplaced)        0.439    83.294    i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/tx_sync/data_clk_i
                             FDRE                                         r  i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/tx_sync/out_data_reg[0]/C
                             clock pessimism              0.211    83.505    
                             clock uncertainty           -0.215    83.290    
                             FDRE (Setup_fdre_C_CE)      -0.199    83.091    i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/tx_sync/out_data_reg[0]
      -------------------------------------------------------------------
                             required time                         83.091    
                             arrival time                          -3.211    
      -------------------------------------------------------------------
                             slack                                 79.880    
    
    
    
    
    
    Min Delay Paths
    --------------------------------------------------------------------------------------
    Slack (VIOLATED) :        -0.057ns  (arrival time - required time)
      Source:                 i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/rx_gen.rx_sync/wr_addr_reg[1]/C
                                (rising edge-triggered cell FDRE clocked by clk_out1_system_sys_audio_clkgen_0  {rise@0.000ns fall@40.690ns period=81.380ns})
      Destination:            i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMA/WADR1
                                (rising edge-triggered cell RAMD32 clocked by clk_out1_system_sys_audio_clkgen_0  {rise@0.000ns fall@40.690ns period=81.380ns})
      Path Group:             clk_out1_system_sys_audio_clkgen_0
      Path Type:              Hold (Min at Fast Process Corner)
      Requirement:            0.000ns  (clk_out1_system_sys_audio_clkgen_0 rise@0.000ns - clk_out1_system_sys_audio_clkgen_0 rise@0.000ns)
      Data Path Delay:        0.346ns  (logic 0.104ns (30.101%)  route 0.242ns (69.899%))
      Logic Levels:           0  
      Clock Path Skew:        0.145ns (DCD - SCD - CPR)
        Destination Clock Delay (DCD):    1.069ns
        Source Clock Delay      (SCD):    0.746ns
        Clock Pessimism Removal (CPR):    0.178ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock clk_out1_system_sys_audio_clkgen_0 rise edge)
                                                          0.000     0.000 r  
        PS7_X0Y0             PS7                          0.000     0.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
                             net (fo=1, unplaced)         0.208     0.208    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
                             BUFG (Prop_bufg_I_O)         0.026     0.234 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
                             net (fo=46, unplaced)        0.114     0.348    i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1
                             MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                          0.050     0.398 r  i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKOUT0
                             net (fo=1, unplaced)         0.208     0.606    i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out1_system_sys_audio_clkgen_0
                             BUFG (Prop_bufg_I_O)         0.026     0.632 r  i_system_wrapper/system_i/sys_audio_clkgen/inst/clkout1_buf/O
                             net (fo=35, unplaced)        0.114     0.746    i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/rx_gen.rx_sync/data_clk_i
                             FDRE                                         r  i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/rx_gen.rx_sync/wr_addr_reg[1]/C
      -------------------------------------------------------------------    -------------------
                             FDRE (Prop_fdre_C_Q)         0.104     0.850 r  i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/rx_gen.rx_sync/wr_addr_reg[1]/Q
                             net (fo=9, unplaced)         0.242     1.092    i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/ADDRD1
                             RAMD32                                       r  i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMA/WADR1
      -------------------------------------------------------------------    -------------------
    
                             (clock clk_out1_system_sys_audio_clkgen_0 rise edge)
                                                          0.000     0.000 r  
        PS7_X0Y0             PS7                          0.000     0.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
                             net (fo=1, unplaced)         0.219     0.219    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
                             BUFG (Prop_bufg_I_O)         0.030     0.249 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
                             net (fo=46, unplaced)        0.259     0.508    i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_in1
                             MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                          0.053     0.561 r  i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKOUT0
                             net (fo=1, unplaced)         0.219     0.780    i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out1_system_sys_audio_clkgen_0
                             BUFG (Prop_bufg_I_O)         0.030     0.810 r  i_system_wrapper/system_i/sys_audio_clkgen/inst/clkout1_buf/O
                             net (fo=35, unplaced)        0.259     1.069    i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/WCLK
                             RAMD32                                       r  i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMA/CLK
                             clock pessimism             -0.178     0.891    
                             RAMD32 (Hold_ramd32_CLK_WADR1)
                                                          0.258     1.149    i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMA
      -------------------------------------------------------------------
                             required time                         -1.149    
                             arrival time                           1.092    
      -------------------------------------------------------------------
                             slack                                 -0.057    
    
    
    
    
    
    Pulse Width Checks
    --------------------------------------------------------------------------------------
    Clock Name:         clk_out1_system_sys_audio_clkgen_0
    Waveform(ns):       { 0.000 40.690 }
    Period(ns):         81.380
    Sources:            { i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKOUT0 }
    
    Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location  Pin
    Min Period        n/a     BUFG/I              n/a            1.409         81.380      79.972               i_system_wrapper/system_i/sys_audio_clkgen/inst/clkout1_buf/I
    Max Period        n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       81.380      131.980              i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKOUT0
    Low Pulse Width   Fast    RAMD32/CLK          n/a            0.768         40.690      39.922               i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMA/CLK
    High Pulse Width  Slow    RAMD32/CLK          n/a            0.768         40.690      39.922               i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMA/CLK
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  clkfbout_system_sys_audio_clkgen_0
      To Clock:  clkfbout_system_sys_audio_clkgen_0
    
    Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    PW    :            0  Failing Endpoints,  Worst Slack       43.929ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Pulse Width Checks
    --------------------------------------------------------------------------------------
    Clock Name:         clkfbout_system_sys_audio_clkgen_0
    Waveform(ns):       { 0.000 22.500 }
    Period(ns):         45.000
    Sources:            { i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKFBOUT }
    
    Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location  Pin
    Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.071         45.000      43.929               i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKFBOUT
    Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       45.000      55.000               i_system_wrapper/system_i/sys_audio_clkgen/inst/mmcm_adv_inst/CLKFBIN
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  mmcm_clk_0_s
      To Clock:  mmcm_clk_0_s
    
    Setup :            0  Failing Endpoints,  Worst Slack        3.505ns,  Total Violation        0.000ns
    Hold  :           32  Failing Endpoints,  Worst Slack       -0.019ns,  Total Violation       -0.338ns
    PW    :            0  Failing Endpoints,  Worst Slack        2.725ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             3.505ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/d_data_cntrl_int_reg[176]/C
                                (rising edge-triggered cell FDCE clocked by mmcm_clk_0_s  {rise@0.000ns fall@3.367ns period=6.735ns})
      Destination:            i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vs_count_reg[0]/R
                                (rising edge-triggered cell FDRE clocked by mmcm_clk_0_s  {rise@0.000ns fall@3.367ns period=6.735ns})
      Path Group:             mmcm_clk_0_s
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            6.735ns  (mmcm_clk_0_s rise@6.735ns - mmcm_clk_0_s rise@0.000ns)
      Data Path Delay:        2.635ns  (logic 1.229ns (46.641%)  route 1.406ns (53.359%))
      Logic Levels:           6  (CARRY4=4 LUT2=1 LUT4=1)
      Clock Path Skew:        -0.145ns (DCD - SCD + CPR)
        Destination Clock Delay (DCD):    0.920ns = ( 7.655 - 6.735 ) 
        Source Clock Delay      (SCD):    1.096ns
        Clock Pessimism Removal (CPR):    0.031ns
      Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
        Total System Jitter     (TSJ):    0.071ns
        Discrete Jitter          (DJ):    0.286ns
        Phase Error              (PE):    0.000ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock mmcm_clk_0_s rise edge)
                                                          0.000     0.000 r  
        PS7_X0Y0             PS7                          0.000     0.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
                             net (fo=1, unplaced)         0.419     0.419    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
                             BUFG (Prop_bufg_I_O)         0.093     0.512 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
                             net (fo=46, unplaced)        0.584     1.096    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
                             MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                         -1.096     0.000 r  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
                             net (fo=1, unplaced)         0.419     0.419    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
                             BUFG (Prop_bufg_I_O)         0.093     0.512 r  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
                             net (fo=758, unplaced)       0.584     1.096    i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/hdmi_clk
                             FDCE                                         r  i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/d_data_cntrl_int_reg[176]/C
      -------------------------------------------------------------------    -------------------
                             FDCE (Prop_fdce_C_Q)         0.233     1.329 r  i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_xfer_cntrl/d_data_cntrl_int_reg[176]/Q
                             net (fo=3, unplaced)         0.207     1.536    i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_vsync_data_e_d_reg_0[159]
                             CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                          0.377     1.913 r  i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hl_width_s_carry/CO[3]
                             net (fo=1, unplaced)         0.007     1.920    i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hl_width_s_carry_n_0
                             CARRY4 (Prop_carry4_CI_CO[3])
                                                          0.054     1.974 r  i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hl_width_s_carry__0/CO[3]
                             net (fo=1, unplaced)         0.000     1.974    i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hl_width_s_carry__0_n_0
                             CARRY4 (Prop_carry4_CI_O[2])
                                                          0.120     2.094 f  i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hl_width_s_carry__1/O[2]
                             net (fo=2, unplaced)         0.253     2.347    i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hl_width_s[11]
                             LUT4 (Prop_lut4_I1_O)        0.137     2.484 r  i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count0_carry__0_i_3/O
                             net (fo=1, unplaced)         0.000     2.484    i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count0_carry__0_i_3_n_0
                             CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                          0.265     2.749 r  i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count0_carry__0/CO[3]
                             net (fo=33, unplaced)        0.497     3.246    i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_count0_carry__0_n_0
                             LUT2 (Prop_lut2_I1_O)        0.043     3.289 r  i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vs_count[0]_i_1/O
                             net (fo=16, unplaced)        0.442     3.731    i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vs_count
                             FDRE                                         r  i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vs_count_reg[0]/R
      -------------------------------------------------------------------    -------------------
    
                             (clock mmcm_clk_0_s rise edge)
                                                          6.735     6.735 r  
        PS7_X0Y0             PS7                          0.000     6.735 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
                             net (fo=1, unplaced)         0.398     7.133    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
                             BUFG (Prop_bufg_I_O)         0.083     7.216 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
                             net (fo=46, unplaced)        0.439     7.655    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
                             MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                         -0.920     6.735 r  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
                             net (fo=1, unplaced)         0.398     7.133    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
                             BUFG (Prop_bufg_I_O)         0.083     7.216 r  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
                             net (fo=758, unplaced)       0.439     7.655    i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_clk
                             FDRE                                         r  i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vs_count_reg[0]/C
                             clock pessimism              0.031     7.686    
                             clock uncertainty           -0.147     7.539    
                             FDRE (Setup_fdre_C_R)       -0.302     7.237    i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vs_count_reg[0]
      -------------------------------------------------------------------
                             required time                          7.237    
                             arrival time                          -3.731    
      -------------------------------------------------------------------
                             slack                                  3.505    
    
    
    
    
    
    Min Delay Paths
    --------------------------------------------------------------------------------------
    Slack (VIOLATED) :        -0.019ns  (arrival time - required time)
      Source:                 i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vsync_data_e_reg/C
                                (rising edge-triggered cell FDRE clocked by mmcm_clk_0_s  {rise@0.000ns fall@3.367ns period=6.735ns})
      Destination:            i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/i_csc_RGB2CrYCb/j_csc_1_Cr/sync_3_m_reg[1]_srl3/D
                                (rising edge-triggered cell SRL16E clocked by mmcm_clk_0_s  {rise@0.000ns fall@3.367ns period=6.735ns})
      Path Group:             mmcm_clk_0_s
      Path Type:              Hold (Min at Fast Process Corner)
      Requirement:            0.000ns  (mmcm_clk_0_s rise@0.000ns - mmcm_clk_0_s rise@0.000ns)
      Data Path Delay:        0.192ns  (logic 0.093ns (48.392%)  route 0.099ns (51.608%))
      Logic Levels:           0  
      Clock Path Skew:        0.145ns (DCD - SCD - CPR)
        Destination Clock Delay (DCD):    0.508ns
        Source Clock Delay      (SCD):    0.348ns
        Clock Pessimism Removal (CPR):    0.015ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock mmcm_clk_0_s rise edge)
                                                          0.000     0.000 r  
        PS7_X0Y0             PS7                          0.000     0.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
                             net (fo=1, unplaced)         0.208     0.208    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
                             BUFG (Prop_bufg_I_O)         0.026     0.234 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
                             net (fo=46, unplaced)        0.114     0.348    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
                             MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                         -0.348     0.000 r  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
                             net (fo=1, unplaced)         0.208     0.208    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
                             BUFG (Prop_bufg_I_O)         0.026     0.234 r  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
                             net (fo=758, unplaced)       0.114     0.348    i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_clk
                             FDRE                                         r  i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vsync_data_e_reg/C
      -------------------------------------------------------------------    -------------------
                             FDRE (Prop_fdre_C_Q)         0.093     0.441 r  i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_vsync_data_e_reg/Q
                             net (fo=2, unplaced)         0.099     0.540    i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/i_csc_RGB2CrYCb/j_csc_1_Cr/hdmi_vsync_data_e
                             SRL16E                                       r  i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/i_csc_RGB2CrYCb/j_csc_1_Cr/sync_3_m_reg[1]_srl3/D
      -------------------------------------------------------------------    -------------------
    
                             (clock mmcm_clk_0_s rise edge)
                                                          0.000     0.000 r  
        PS7_X0Y0             PS7                          0.000     0.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
                             net (fo=1, unplaced)         0.219     0.219    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
                             BUFG (Prop_bufg_I_O)         0.030     0.249 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
                             net (fo=46, unplaced)        0.259     0.508    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
                             MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                         -0.508     0.000 r  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
                             net (fo=1, unplaced)         0.219     0.219    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
                             BUFG (Prop_bufg_I_O)         0.030     0.249 r  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
                             net (fo=758, unplaced)       0.259     0.508    i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/i_csc_RGB2CrYCb/j_csc_1_Cr/hdmi_clk
                             SRL16E                                       r  i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/i_csc_RGB2CrYCb/j_csc_1_Cr/sync_3_m_reg[1]_srl3/CLK
                             clock pessimism             -0.015     0.493    
                             SRL16E (Hold_srl16e_CLK_D)
                                                          0.066     0.559    i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/i_csc_RGB2CrYCb/j_csc_1_Cr/sync_3_m_reg[1]_srl3
      -------------------------------------------------------------------
                             required time                         -0.559    
                             arrival time                           0.540    
      -------------------------------------------------------------------
                             slack                                 -0.019    
    
    
    
    
    
    Pulse Width Checks
    --------------------------------------------------------------------------------------
    Clock Name:         mmcm_clk_0_s
    Waveform(ns):       { 0.000 3.367 }
    Period(ns):         6.735
    Sources:            { i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0 }
    
    Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location  Pin
    Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            1.839         6.735       4.896                i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/i_mem/m_ram_reg/CLKARDCLK
    Max Period        n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       6.735       206.625              i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
    Low Pulse Width   Slow    SRL16E/CLK          n/a            0.642         3.367       2.725                i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_2d_reg_srl3/CLK
    High Pulse Width  Slow    SRL16E/CLK          n/a            0.642         3.367       2.725                i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_hs_2d_reg_srl3/CLK
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  mmcm_clk_1_s
      To Clock:  mmcm_clk_1_s
    
    Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    PW    :            0  Failing Endpoints,  Worst Slack        5.326ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Pulse Width Checks
    --------------------------------------------------------------------------------------
    Clock Name:         mmcm_clk_1_s
    Waveform(ns):       { 0.000 3.367 }
    Period(ns):         6.735
    Sources:            { i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT1 }
    
    Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location  Pin
    Min Period  n/a     BUFG/I              n/a            1.409         6.735       5.326                i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_1_bufg/I
    Max Period  n/a     MMCME2_ADV/CLKOUT1  n/a            213.360       6.735       206.625              i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT1
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  mmcm_clk_2_s
      To Clock:  mmcm_clk_2_s
    
    Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    PW    :            0  Failing Endpoints,  Worst Slack        0.836ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Pulse Width Checks
    --------------------------------------------------------------------------------------
    Clock Name:         mmcm_clk_2_s
    Waveform(ns):       { 0.000 1.122 }
    Period(ns):         2.245
    Sources:            { i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT2 }
    
    Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location  Pin
    Min Period  n/a     BUFG/I              n/a            1.409         2.245       0.836                i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_2_bufg/I
    Max Period  n/a     MMCME2_ADV/CLKOUT2  n/a            213.360       2.245       211.115              i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT2
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  mmcm_fb_clk_s
      To Clock:  mmcm_fb_clk_s
    
    Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    PW    :            0  Failing Endpoints,  Worst Slack       45.000ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Pulse Width Checks
    --------------------------------------------------------------------------------------
    Clock Name:         mmcm_fb_clk_s
    Waveform(ns):       { 0.000 27.500 }
    Period(ns):         55.000
    Sources:            { i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKFBOUT }
    
    Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location  Pin
    Min Period  n/a     BUFG/I              n/a            1.409         55.000      53.591               i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_fb_clk_bufg/I
    Max Period  n/a     MMCME2_ADV/CLKFBIN  n/a            100.000       55.000      45.000               i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKFBIN
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  rx1_dclk_out
      To Clock:  rx1_dclk_out
    
    Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    PW    :            0  Failing Endpoints,  Worst Slack       11.251ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Pulse Width Checks
    --------------------------------------------------------------------------------------
    Clock Name:         rx1_dclk_out
    Waveform(ns):       { 0.000 6.250 }
    Period(ns):         12.500
    Sources:            { rx1_dclk_in_p }
    
    Check Type  Corner  Lib Pin  Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location     Pin
    Min Period  n/a     BUFIO/I  n/a            1.249         12.500      11.251     BUFIO_X1Y18  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_clk_buf/I
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  adc_clk_div_s
      To Clock:  adc_clk_div_s
    
    Setup :            0  Failing Endpoints,  Worst Slack       47.272ns,  Total Violation        0.000ns
    Hold  :          505  Failing Endpoints,  Worst Slack       -0.131ns,  Total Violation      -12.607ns
    PW    :            0  Failing Endpoints,  Worst Slack       24.232ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             47.272ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/axi_adrv9001_tx1_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_mem/m_ram_reg/CLKARDCLK
                                (rising edge-triggered cell RAMB36E1 clocked by adc_clk_div_s  {rise@0.000ns fall@25.000ns period=50.000ns})
      Destination:            i_system_wrapper/system_i/util_dac_1_upack/inst/i_upack/fifo_rd_data_reg[16]/D
                                (rising edge-triggered cell FDRE clocked by adc_clk_div_s  {rise@0.000ns fall@25.000ns period=50.000ns})
      Path Group:             adc_clk_div_s
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            50.000ns  (adc_clk_div_s rise@50.000ns - adc_clk_div_s rise@0.000ns)
      Data Path Delay:        2.590ns  (logic 1.890ns (72.960%)  route 0.700ns (27.040%))
      Logic Levels:           2  (LUT3=1 LUT5=1)
      Clock Path Skew:        -0.145ns (DCD - SCD + CPR)
        Destination Clock Delay (DCD):    4.388ns = ( 54.388 - 50.000 ) 
        Source Clock Delay      (SCD):    7.970ns
        Clock Pessimism Removal (CPR):    3.438ns
      Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
        Total System Jitter     (TSJ):    0.071ns
        Total Input Jitter      (TIJ):    0.000ns
        Discrete Jitter          (DJ):    0.000ns
        Phase Error              (PE):    0.000ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock adc_clk_div_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        J4                                                0.000     5.000 r  rx1_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/rx1_dclk_in_p_dclk_in
        J4                   IBUFDS (Prop_ibufds_I_O)     0.870     5.870 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.354     6.224    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.650     6.874 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.584     7.458    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.093     7.551 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/I_bufg/O
                             net (fo=12415, unplaced)     0.419     7.970    i_system_wrapper/system_i/axi_adrv9001_tx1_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_mem/m_axis_aclk
                             RAMB36E1                                     r  i_system_wrapper/system_i/axi_adrv9001_tx1_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_mem/m_ram_reg/CLKARDCLK
      -------------------------------------------------------------------    -------------------
                             RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[0])
                                                          1.800     9.770 r  i_system_wrapper/system_i/axi_adrv9001_tx1_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_mem/m_ram_reg/DOADO[0]
                             net (fo=2, unplaced)         0.419    10.190    i_system_wrapper/system_i/util_dac_1_upack/inst/i_upack/i_pack_shell/gen_input_buffer.i_ext_ctrl_interconnect/s_axis_data[0]
                             LUT5 (Prop_lut5_I3_O)        0.043    10.233 r  i_system_wrapper/system_i/util_dac_1_upack/inst/i_upack/i_pack_shell/gen_input_buffer.i_ext_ctrl_interconnect/fifo_rd_data[0]_i_2/O
                             net (fo=2, unplaced)         0.281    10.514    i_system_wrapper/system_i/util_dac_1_upack/inst/i_upack/i_pack_shell/gen_input_buffer.i_ext_ctrl_interconnect/fifo_rd_data[0]_i_2_n_0
                             LUT3 (Prop_lut3_I2_O)        0.047    10.561 r  i_system_wrapper/system_i/util_dac_1_upack/inst/i_upack/i_pack_shell/gen_input_buffer.i_ext_ctrl_interconnect/fifo_rd_data[16]_i_1/O
                             net (fo=1, unplaced)         0.000    10.561    i_system_wrapper/system_i/util_dac_1_upack/inst/i_upack/deinterleaved_data[16]
                             FDRE                                         r  i_system_wrapper/system_i/util_dac_1_upack/inst/i_upack/fifo_rd_data_reg[16]/D
      -------------------------------------------------------------------    -------------------
    
                             (clock adc_clk_div_s rise edge)
                                                         50.000    50.000 r  
                             clock source latency         2.000    52.000    
        J4                                                0.000    52.000 r  rx1_dclk_in_p (IN)
                             net (fo=0)                   0.000    52.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/rx1_dclk_in_p_dclk_in
        J4                   IBUFDS (Prop_ibufds_I_O)     0.768    52.768 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.209    52.977    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.614    53.591 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.439    54.030    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.083    54.113 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/I_bufg/O
                             net (fo=12415, unplaced)     0.274    54.388    i_system_wrapper/system_i/util_dac_1_upack/inst/i_upack/clk
                             FDRE                                         r  i_system_wrapper/system_i/util_dac_1_upack/inst/i_upack/fifo_rd_data_reg[16]/C
                             clock pessimism              3.438    57.825    
                             clock uncertainty           -0.035    57.790    
                             FDRE (Setup_fdre_C_D)        0.043    57.833    i_system_wrapper/system_i/util_dac_1_upack/inst/i_upack/fifo_rd_data_reg[16]
      -------------------------------------------------------------------
                             required time                         57.833    
                             arrival time                         -10.561    
      -------------------------------------------------------------------
                             slack                                 47.272    
    
    
    
    
    
    Min Delay Paths
    --------------------------------------------------------------------------------------
    Slack (VIOLATED) :        -0.131ns  (arrival time - required time)
      Source:                 i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_up_dac_common/i_xfer_cntrl/d_data_cntrl_int_reg[0]/C
                                (rising edge-triggered cell FDCE clocked by adc_clk_div_s  {rise@0.000ns fall@25.000ns period=50.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_1_phy/i_serdes/g_data[0].i_serdes/RST
                                (rising edge-triggered cell OSERDESE2 clocked by adc_clk_div_s  {rise@0.000ns fall@25.000ns period=50.000ns})
      Path Group:             adc_clk_div_s
      Path Type:              Hold (Min at Fast Process Corner)
      Requirement:            0.000ns  (adc_clk_div_s rise@0.000ns - adc_clk_div_s rise@0.000ns)
      Data Path Delay:        0.621ns  (logic 0.168ns (27.032%)  route 0.453ns (72.968%))
      Logic Levels:           1  (LUT3=1)
      Clock Path Skew:        0.145ns (DCD - SCD - CPR)
        Destination Clock Delay (DCD):    6.378ns
        Source Clock Delay      (SCD):    2.830ns
        Clock Pessimism Removal (CPR):    3.403ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock adc_clk_div_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         2.000     2.000    
        J4                                                0.000     2.000 r  rx1_dclk_in_p (IN)
                             net (fo=0)                   0.000     2.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/rx1_dclk_in_p_dclk_in
        J4                   IBUFDS (Prop_ibufds_I_O)     0.353     2.353 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.040     2.393    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.223     2.616 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.114     2.730    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.026     2.756 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/I_bufg/O
                             net (fo=12415, unplaced)     0.074     2.830    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_up_dac_common/i_xfer_cntrl/adc_clk_div
                             FDCE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_up_dac_common/i_xfer_cntrl/d_data_cntrl_int_reg[0]/C
      -------------------------------------------------------------------    -------------------
                             FDCE (Prop_fdce_C_Q)         0.104     2.934 f  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_up_dac_common/i_xfer_cntrl/d_data_cntrl_int_reg[0]/Q
                             net (fo=43, unplaced)        0.245     3.179    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_up_dac_common/i_xfer_cntrl/Q[0]
                             LUT3 (Prop_lut3_I0_O)        0.064     3.243 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_up_dac_common/i_xfer_cntrl/g_data[0].i_serdes_i_9/O
                             net (fo=4, unplaced)         0.208     3.451    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_1_phy/i_serdes/RST0
        OLOGIC_X1Y242        OSERDESE2                                    r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_1_phy/i_serdes/g_data[0].i_serdes/RST
      -------------------------------------------------------------------    -------------------
    
                             (clock adc_clk_div_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        J4                                                0.000     5.000 r  rx1_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/rx1_dclk_in_p_dclk_in
        J4                   IBUFDS (Prop_ibufds_I_O)     0.434     5.434 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.185     5.619    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.251     5.870 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.259     6.129    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.030     6.159 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/I_bufg/O
                             net (fo=12415, unplaced)     0.219     6.378    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_1_phy/i_serdes/tx1_dclk_out_p_dclk_out
        OLOGIC_X1Y242        OSERDESE2                                    r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_1_phy/i_serdes/g_data[0].i_serdes/CLKDIV
                             clock pessimism             -3.403     2.975    
        OLOGIC_X1Y242        OSERDESE2 (Hold_oserdese2_CLKDIV_RST)
                                                          0.607     3.582    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_1_phy/i_serdes/g_data[0].i_serdes
      -------------------------------------------------------------------
                             required time                         -3.582    
                             arrival time                           3.451    
      -------------------------------------------------------------------
                             slack                                 -0.131    
    
    
    
    
    
    Pulse Width Checks
    --------------------------------------------------------------------------------------
    Clock Name:         adc_clk_div_s
    Waveform(ns):       { 0.000 25.000 }
    Period(ns):         50.000
    Sources:            { i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_div_clk_buf/O }
    
    Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location  Pin
    Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            1.839         50.000      48.161               i_system_wrapper/system_i/axi_adrv9001_rx1_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_mem/m_ram_reg/CLKBWRCLK
    Low Pulse Width   Fast    RAMD32/CLK          n/a            0.768         25.000      24.232               i_system_wrapper/system_i/axi_adrv9001_rx1_dma/inst/i_transfer/i_request_arb/eot_mem_dest_reg_r1_0_15_0_0/DP/CLK
    High Pulse Width  Slow    RAMD32/CLK          n/a            0.768         25.000      24.232               i_system_wrapper/system_i/axi_adrv9001_rx1_dma/inst/i_transfer/i_request_arb/eot_mem_dest_reg_r1_0_15_0_0/DP/CLK
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  rx2_dclk_out
      To Clock:  rx2_dclk_out
    
    Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    PW    :            0  Failing Endpoints,  Worst Slack       11.251ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Pulse Width Checks
    --------------------------------------------------------------------------------------
    Clock Name:         rx2_dclk_out
    Waveform(ns):       { 0.000 6.250 }
    Period(ns):         12.500
    Sources:            { rx2_dclk_in_p }
    
    Check Type  Corner  Lib Pin  Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location     Pin
    Min Period  n/a     BUFIO/I  n/a            1.249         12.500      11.251     BUFIO_X1Y17  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_buf/I
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  adc_clk_div_s_1
      To Clock:  adc_clk_div_s_1
    
    Setup :            0  Failing Endpoints,  Worst Slack       47.332ns,  Total Violation        0.000ns
    Hold  :          957  Failing Endpoints,  Worst Slack       -0.237ns,  Total Violation      -19.889ns
    PW    :            0  Failing Endpoints,  Worst Slack       24.358ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             47.332ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/ila_0/inst/ila_core_inst/en_adv_trigger_reg/C
                                (rising edge-triggered cell FDRE clocked by adc_clk_div_s_1  {rise@0.000ns fall@25.000ns period=50.000ns})
      Destination:            i_system_wrapper/system_i/ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg[0]/R
                                (rising edge-triggered cell FDRE clocked by adc_clk_div_s_1  {rise@0.000ns fall@25.000ns period=50.000ns})
      Path Group:             adc_clk_div_s_1
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            50.000ns  (adc_clk_div_s_1 rise@50.000ns - adc_clk_div_s_1 rise@0.000ns)
      Data Path Delay:        2.186ns  (logic 0.450ns (20.586%)  route 1.736ns (79.414%))
      Logic Levels:           3  (LUT3=2 SRLC32E=1)
      Clock Path Skew:        -0.145ns (DCD - SCD + CPR)
        Destination Clock Delay (DCD):    4.375ns = ( 54.375 - 50.000 ) 
        Source Clock Delay      (SCD):    7.958ns
        Clock Pessimism Removal (CPR):    3.438ns
      Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
        Total System Jitter     (TSJ):    0.071ns
        Total Input Jitter      (TIJ):    0.000ns
        Discrete Jitter          (DJ):    0.000ns
        Phase Error              (PE):    0.000ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock adc_clk_div_s_1 rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        M6                                                0.000     5.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.857     5.857 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.354     6.211    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.650     6.861 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.584     7.445    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.093     7.538 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.419     7.958    i_system_wrapper/system_i/ila_0/inst/ila_core_inst/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
                             FDRE                                         r  i_system_wrapper/system_i/ila_0/inst/ila_core_inst/en_adv_trigger_reg/C
      -------------------------------------------------------------------    -------------------
                             FDRE (Prop_fdre_C_Q)         0.233     8.191 f  i_system_wrapper/system_i/ila_0/inst/ila_core_inst/en_adv_trigger_reg/Q
                             net (fo=2, unplaced)         0.427     8.618    i_system_wrapper/system_i/ila_0/inst/ila_core_inst/u_ila_cap_ctrl/itrigger_out_reg_0
                             LUT3 (Prop_lut3_I0_O)        0.131     8.749 r  i_system_wrapper/system_i/ila_0/inst/ila_core_inst/u_ila_cap_ctrl/trigger_i/O
                             net (fo=19, unplaced)        0.466     9.215    i_system_wrapper/system_i/ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/A[2]
                             SRLC32E (Prop_srlc32e_A[2]_Q)
                                                          0.043     9.258 r  i_system_wrapper/system_i/ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_A/Q
                             net (fo=1, unplaced)         0.407     9.665    i_system_wrapper/system_i/ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.SRL_Q_1
                             LUT3 (Prop_lut3_I0_O)        0.043     9.708 r  i_system_wrapper/system_i/ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/iscnt[0]_i_1/O
                             net (fo=12, unplaced)        0.436    10.144    i_system_wrapper/system_i/ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST_n_2
                             FDRE                                         r  i_system_wrapper/system_i/ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg[0]/R
      -------------------------------------------------------------------    -------------------
    
                             (clock adc_clk_div_s_1 rise edge)
                                                         50.000    50.000 r  
                             clock source latency         2.000    52.000    
        M6                                                0.000    52.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000    52.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.756    52.756 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.209    52.965    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.614    53.579 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.439    54.018    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.083    54.101 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.274    54.375    i_system_wrapper/system_i/ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/probeDelay1_reg[11]
                             FDRE                                         r  i_system_wrapper/system_i/ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg[0]/C
                             clock pessimism              3.438    57.813    
                             clock uncertainty           -0.035    57.778    
                             FDRE (Setup_fdre_C_R)       -0.302    57.476    i_system_wrapper/system_i/ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg[0]
      -------------------------------------------------------------------
                             required time                         57.476    
                             arrival time                         -10.144    
      -------------------------------------------------------------------
                             slack                                 47.332    
    
    
    
    
    
    Min Delay Paths
    --------------------------------------------------------------------------------------
    Slack (VIOLATED) :        -0.237ns  (arrival time - required time)
      Source:                 i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1_ctrl_sync/cdc_sync_stage2_reg[0]/C
                                (rising edge-triggered cell FDRE clocked by adc_clk_div_s_1  {rise@0.000ns fall@25.000ns period=50.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_2_phy/i_serdes/g_data[0].i_serdes/RST
                                (rising edge-triggered cell OSERDESE2 clocked by adc_clk_div_s_1  {rise@0.000ns fall@25.000ns period=50.000ns})
      Path Group:             adc_clk_div_s_1
      Path Type:              Hold (Min at Fast Process Corner)
      Requirement:            0.000ns  (adc_clk_div_s_1 rise@0.000ns - adc_clk_div_s_1 rise@0.000ns)
      Data Path Delay:        0.515ns  (logic 0.169ns (32.823%)  route 0.346ns (67.177%))
      Logic Levels:           1  (LUT4=1)
      Clock Path Skew:        0.145ns (DCD - SCD - CPR)
        Destination Clock Delay (DCD):    6.365ns
        Source Clock Delay      (SCD):    2.817ns
        Clock Pessimism Removal (CPR):    3.403ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock adc_clk_div_s_1 rise edge)
                                                          0.000     0.000 r  
                             clock source latency         2.000     2.000    
        M6                                                0.000     2.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     2.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.341     2.341 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.040     2.381    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.223     2.604 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.114     2.718    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.026     2.744 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.074     2.817    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1_ctrl_sync/cdc_sync_stage2_reg[3]_0
                             FDRE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1_ctrl_sync/cdc_sync_stage2_reg[0]/C
      -------------------------------------------------------------------    -------------------
                             FDRE (Prop_fdre_C_Q)         0.104     2.921 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1_ctrl_sync/cdc_sync_stage2_reg[0]/Q
                             net (fo=2, unplaced)         0.138     3.059    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1_ctrl_sync/cdc_sync_stage2_reg_n_0_[0]
                             LUT4 (Prop_lut4_I2_O)        0.065     3.124 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1_ctrl_sync/g_data[0].i_serdes_i_9__0/O
                             net (fo=4, unplaced)         0.208     3.332    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_2_phy/i_serdes/RST0_1
        OLOGIC_X1Y208        OSERDESE2                                    r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_2_phy/i_serdes/g_data[0].i_serdes/RST
      -------------------------------------------------------------------    -------------------
    
                             (clock adc_clk_div_s_1 rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        M6                                                0.000     5.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.421     5.421 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.185     5.606    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.251     5.857 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.259     6.116    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.030     6.146 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.219     6.365    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_2_phy/i_serdes/dac_clk_div
        OLOGIC_X1Y208        OSERDESE2                                    r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_2_phy/i_serdes/g_data[0].i_serdes/CLKDIV
                             clock pessimism             -3.403     2.962    
        OLOGIC_X1Y208        OSERDESE2 (Hold_oserdese2_CLKDIV_RST)
                                                          0.607     3.569    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_2_phy/i_serdes/g_data[0].i_serdes
      -------------------------------------------------------------------
                             required time                         -3.569    
                             arrival time                           3.332    
      -------------------------------------------------------------------
                             slack                                 -0.237    
    
    
    
    
    
    Pulse Width Checks
    --------------------------------------------------------------------------------------
    Clock Name:         adc_clk_div_s_1
    Waveform(ns):       { 0.000 25.000 }
    Period(ns):         50.000
    Sources:            { i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O }
    
    Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location  Pin
    Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.095         50.000      47.905               i_system_wrapper/system_i/ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/CLKARDCLK
    Low Pulse Width   Slow    SRL16E/CLK          n/a            0.642         25.000      24.358               i_system_wrapper/system_i/FIFO_Delay_0/U0/FIFO_8192_16bit_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmgb.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/SAFETY_CKT_GEN.RSTA_SHFT_REG_reg[3]_srl3/CLK
    High Pulse Width  Slow    SRL16E/CLK          n/a            0.642         25.000      24.358               i_system_wrapper/system_i/FIFO_Delay_0/U0/FIFO_8192_16bit_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmgb.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/SAFETY_CKT_GEN.RSTA_SHFT_REG_reg[3]_srl3/CLK
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  adc_clk_in_s
      To Clock:  adc_clk_in_s
    
    Setup :            0  Failing Endpoints,  Worst Slack       93.144ns,  Total Violation        0.000ns
    Hold  :         4156  Failing Endpoints,  Worst Slack       -0.091ns,  Total Violation      -90.278ns
    PW    :            0  Failing Endpoints,  Worst Slack       49.232ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             93.144ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/Product_Im_1_reg[0]__0/CLK
                                (rising edge-triggered cell DSP48E1 clocked by adc_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Destination:            i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][29]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0/D
                                (rising edge-triggered cell SRL16E clocked by adc_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Path Group:             adc_clk_in_s
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            100.000ns  (adc_clk_in_s rise@100.000ns - adc_clk_in_s rise@0.000ns)
      Data Path Delay:        6.571ns  (logic 3.245ns (49.380%)  route 3.326ns (50.620%))
      Logic Levels:           22  (CARRY4=12 LUT2=1 LUT3=4 LUT4=3 LUT5=1 LUT6=1)
      Clock Path Skew:        -0.145ns (DCD - SCD + CPR)
        Destination Clock Delay (DCD):    5.950ns = ( 105.950 - 100.000 ) 
        Source Clock Delay      (SCD):    9.869ns
        Clock Pessimism Removal (CPR):    3.774ns
      Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
        Total System Jitter     (TSJ):    0.071ns
        Total Input Jitter      (TIJ):    0.000ns
        Discrete Jitter          (DJ):    0.000ns
        Phase Error              (PE):    0.000ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock adc_clk_in_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        M6                                                0.000     5.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.857     5.857 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.354     6.211    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.650     6.861 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.584     7.445    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.093     7.538 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.419     7.958    adc_clk_out_s
                             BUFR (Prop_bufr_I_O)         0.650     8.608 r  BUFR_inst2/O
                             net (fo=1, unplaced)         0.584     9.192    adc_clk_in_s
                             BUFG (Prop_bufg_I_O)         0.093     9.285 r  BUFG_inst2/O
                             net (fo=23764, unplaced)     0.584     9.869    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/IPCORE_CLK
                             DSP48E1                                      r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/Product_Im_1_reg[0]__0/CLK
      -------------------------------------------------------------------    -------------------
                             DSP48E1 (Prop_dsp48e1_CLK_P[0])
                                                          0.348    10.217 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/Product_Im_1_reg[0]__0/P[0]
                             net (fo=2, unplaced)         0.419    10.636    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/Product_Im_1_reg[0]__0_n_105
                             LUT2 (Prop_lut2_I0_O)        0.043    10.679 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][15]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_192/O
                             net (fo=1, unplaced)         0.000    10.679    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][15]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_192_n_0
                             CARRY4 (Prop_carry4_S[1]_CO[3])
                                                          0.256    10.935 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][15]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_185/CO[3]
                             net (fo=1, unplaced)         0.007    10.942    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][15]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_185_n_0
                             CARRY4 (Prop_carry4_CI_CO[3])
                                                          0.054    10.996 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][15]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_180/CO[3]
                             net (fo=1, unplaced)         0.000    10.996    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][15]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_180_n_0
                             CARRY4 (Prop_carry4_CI_CO[3])
                                                          0.054    11.050 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][15]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_175/CO[3]
                             net (fo=1, unplaced)         0.000    11.050    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][15]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_175_n_0
                             CARRY4 (Prop_carry4_CI_O[3])
                                                          0.157    11.207 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][15]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_174/O[3]
                             net (fo=2, unplaced)         0.302    11.509    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][15]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_174_n_4
                             LUT3 (Prop_lut3_I2_O)        0.120    11.629 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][15]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_169/O
                             net (fo=2, unplaced)         0.281    11.910    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][15]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_169_n_0
                             LUT4 (Prop_lut4_I3_O)        0.043    11.953 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][15]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_172/O
                             net (fo=1, unplaced)         0.000    11.953    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][15]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_172_n_0
                             CARRY4 (Prop_carry4_S[1]_CO[3])
                                                          0.256    12.209 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][15]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_159/CO[3]
                             net (fo=1, unplaced)         0.007    12.216    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][15]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_159_n_0
                             CARRY4 (Prop_carry4_CI_O[3])
                                                          0.157    12.373 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][19]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_159/O[3]
                             net (fo=2, unplaced)         0.302    12.675    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][19]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_159_n_4
                             LUT3 (Prop_lut3_I1_O)        0.120    12.795 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][19]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_113/O
                             net (fo=2, unplaced)         0.281    13.076    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][19]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_113_n_0
                             LUT4 (Prop_lut4_I3_O)        0.043    13.119 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][19]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_117/O
                             net (fo=1, unplaced)         0.000    13.119    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][19]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_117_n_0
                             CARRY4 (Prop_carry4_S[0]_CO[3])
                                                          0.246    13.365 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][19]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_56/CO[3]
                             net (fo=1, unplaced)         0.000    13.365    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][19]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_56_n_0
                             CARRY4 (Prop_carry4_CI_O[3])
                                                          0.157    13.522 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_PolyPhaseFIRFilter/intdelay_reg_1_reg[1][23]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_56/O[3]
                             net (fo=2, unplaced)         0.302    13.824    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][23]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_15_0[3]
                             LUT3 (Prop_lut3_I0_O)        0.120    13.944 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][23]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_37/O
                             net (fo=2, unplaced)         0.281    14.225    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][23]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_37_n_0
                             LUT4 (Prop_lut4_I3_O)        0.043    14.268 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][23]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_41/O
                             net (fo=1, unplaced)         0.000    14.268    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][23]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_41_n_0
                             CARRY4 (Prop_carry4_S[0]_CO[3])
                                                          0.246    14.514 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][23]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_15/CO[3]
                             net (fo=1, unplaced)         0.000    14.514    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][23]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_15_n_0
                             CARRY4 (Prop_carry4_CI_O[3])
                                                          0.157    14.671 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][27]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_15/O[3]
                             net (fo=3, unplaced)         0.309    14.980    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][27]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_15_n_4
                             LUT3 (Prop_lut3_I1_O)        0.120    15.100 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][27]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_17/O
                             net (fo=2, unplaced)         0.281    15.381    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][27]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_17_n_0
                             LUT5 (Prop_lut5_I1_O)        0.043    15.424 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][27]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_5/O
                             net (fo=2, unplaced)         0.253    15.677    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][27]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_5_n_0
                             LUT6 (Prop_lut6_I0_O)        0.043    15.720 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][27]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_9/O
                             net (fo=1, unplaced)         0.000    15.720    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][27]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_9_n_0
                             CARRY4 (Prop_carry4_S[0]_CO[3])
                                                          0.246    15.966 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][27]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_1/CO[3]
                             net (fo=1, unplaced)         0.000    15.966    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][27]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_1_n_0
                             CARRY4 (Prop_carry4_CI_O[1])
                                                          0.173    16.139 r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][31]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0_i_1/O[1]
                             net (fo=1, unplaced)         0.301    16.440    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/PolyPhaseFIRFilter_out1_im[29]
                             SRL16E                                       r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][29]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0/D
      -------------------------------------------------------------------    -------------------
    
                             (clock adc_clk_in_s rise edge)
                                                        100.000   100.000 r  
                             clock source latency         2.000   102.000    
        M6                                                0.000   102.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000   102.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.756   102.756 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.209   102.965    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.614   103.579 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.439   104.018    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.083   104.101 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.274   104.375    adc_clk_out_s
                             BUFR (Prop_bufr_I_O)         0.614   104.989 r  BUFR_inst2/O
                             net (fo=1, unplaced)         0.439   105.428    adc_clk_in_s
                             BUFG (Prop_bufg_I_O)         0.083   105.511 r  BUFG_inst2/O
                             net (fo=23764, unplaced)     0.439   105.950    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/IPCORE_CLK
                             SRL16E                                       r  i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][29]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0/CLK
                             clock pessimism              3.774   109.724    
                             clock uncertainty           -0.035   109.689    
                             SRL16E (Setup_srl16e_CLK_D)
                                                         -0.104   109.585    i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/intdelay_reg_1_reg[1][29]_srl2___U0_u_HDLRxIPCofinal_ip_dut_inst_u_HDLRxIPCofinal_ip_src_HDLRxIPCore_u_HDLRx_u_Channelizer_u_FFT_M_Point_u_FFT_HDL_Optimized1_intdelay_reg_5_reg_r_0
      -------------------------------------------------------------------
                             required time                        109.585    
                             arrival time                         -16.440    
      -------------------------------------------------------------------
                             slack                                 93.144    
    
    
    
    
    
    Min Delay Paths
    --------------------------------------------------------------------------------------
    Slack (VIOLATED) :        -0.091ns  (arrival time - required time)
      Source:                 i_system_wrapper/system_i/util_adc_2_pack/inst/i_cpack/packed_fifo_wr_data_reg[0]/C
                                (rising edge-triggered cell FDRE clocked by adc_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_mem/m_ram_reg_bram_0/DIBDI[0]
                                (rising edge-triggered cell RAMB36E1 clocked by adc_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Path Group:             adc_clk_in_s
      Path Type:              Hold (Min at Fast Process Corner)
      Requirement:            0.000ns  (adc_clk_in_s rise@0.000ns - adc_clk_in_s rise@0.000ns)
      Data Path Delay:        0.312ns  (logic 0.104ns (33.332%)  route 0.208ns (66.668%))
      Logic Levels:           0  
      Clock Path Skew:        0.145ns (DCD - SCD - CPR)
        Destination Clock Delay (DCD):    7.164ns
        Source Clock Delay      (SCD):    3.294ns
        Clock Pessimism Removal (CPR):    3.725ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock adc_clk_in_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         2.000     2.000    
        M6                                                0.000     2.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     2.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.341     2.341 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.040     2.381    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.223     2.604 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.114     2.718    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.026     2.744 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.074     2.817    adc_clk_out_s
                             BUFR (Prop_bufr_I_O)         0.223     3.040 r  BUFR_inst2/O
                             net (fo=1, unplaced)         0.114     3.154    adc_clk_in_s
                             BUFG (Prop_bufg_I_O)         0.026     3.180 r  BUFG_inst2/O
                             net (fo=23764, unplaced)     0.114     3.294    i_system_wrapper/system_i/util_adc_2_pack/inst/i_cpack/clk
                             FDRE                                         r  i_system_wrapper/system_i/util_adc_2_pack/inst/i_cpack/packed_fifo_wr_data_reg[0]/C
      -------------------------------------------------------------------    -------------------
                             FDRE (Prop_fdre_C_Q)         0.104     3.398 r  i_system_wrapper/system_i/util_adc_2_pack/inst/i_cpack/packed_fifo_wr_data_reg[0]/Q
                             net (fo=1, unplaced)         0.208     3.607    i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_mem/fifo_wr_din[0]
                             RAMB36E1                                     r  i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_mem/m_ram_reg_bram_0/DIBDI[0]
      -------------------------------------------------------------------    -------------------
    
                             (clock adc_clk_in_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        M6                                                0.000     5.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.421     5.421 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.185     5.606    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.251     5.857 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.259     6.116    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.030     6.146 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.219     6.365    adc_clk_out_s
                             BUFR (Prop_bufr_I_O)         0.251     6.616 r  BUFR_inst2/O
                             net (fo=1, unplaced)         0.259     6.875    adc_clk_in_s
                             BUFG (Prop_bufg_I_O)         0.030     6.905 r  BUFG_inst2/O
                             net (fo=23764, unplaced)     0.259     7.164    i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_mem/fifo_wr_clk
                             RAMB36E1                                     r  i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_mem/m_ram_reg_bram_0/CLKBWRCLK
                             clock pessimism             -3.725     3.439    
                             RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_DIBDI[0])
                                                          0.258     3.697    i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_mem/m_ram_reg_bram_0
      -------------------------------------------------------------------
                             required time                         -3.697    
                             arrival time                           3.607    
      -------------------------------------------------------------------
                             slack                                 -0.091    
    
    
    
    
    
    Pulse Width Checks
    --------------------------------------------------------------------------------------
    Clock Name:         adc_clk_in_s
    Waveform(ns):       { 0.000 50.000 }
    Period(ns):         100.000
    Sources:            { BUFR_inst2/O }
    
    Check Type        Corner  Lib Pin      Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location  Pin
    Min Period        n/a     DSP48E1/CLK  n/a            2.772         100.000     97.228               i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/u_SDF1_7_1/u_MUL4/Complex4Multiply_mult1_re_pipe1_reg/CLK
    Low Pulse Width   Slow    RAMD32/CLK   n/a            0.768         50.000      49.232               i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/u_SDF1_7_1/u_SDFCOMMUTATOR_7/u_dataXMEM_im_0_7/ram_reg_0_7_0_5/RAMA/CLK
    High Pulse Width  Slow    RAMD32/CLK   n/a            0.768         50.000      49.232               i_system_wrapper/system_i/HDLRxIPCofinal_ip_0/U0/u_HDLRxIPCofinal_ip_dut_inst/u_HDLRxIPCofinal_ip_src_HDLRxIPCore/u_HDLRx/u_Channelizer/u_FFT_M_Point/u_FFT_HDL_Optimized1/u_SDF1_7_1/u_SDFCOMMUTATOR_7/u_dataXMEM_im_0_7/ram_reg_0_7_0_5/RAMA/CLK
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  dac_clk_in_s
      To Clock:  dac_clk_in_s
    
    Setup :            0  Failing Endpoints,  Worst Slack       92.507ns,  Total Violation        0.000ns
    Hold  :         4179  Failing Endpoints,  Worst Slack       -0.043ns,  Total Violation      -86.647ns
    PW    :            0  Failing Endpoints,  Worst Slack       49.232ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             92.507ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Product_Im_1_reg[0]__0/CLK
                                (rising edge-triggered cell DSP48E1 clocked by dac_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Destination:            i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_Q/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/DIADI[13]
                                (rising edge-triggered cell RAMB18E1 clocked by dac_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Path Group:             dac_clk_in_s
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            100.000ns  (dac_clk_in_s rise@100.000ns - dac_clk_in_s rise@0.000ns)
      Data Path Delay:        6.690ns  (logic 3.245ns (48.506%)  route 3.445ns (51.494%))
      Logic Levels:           22  (CARRY4=12 LUT2=1 LUT3=4 LUT4=3 LUT5=1 LUT6=1)
      Clock Path Skew:        -0.145ns (DCD - SCD + CPR)
        Destination Clock Delay (DCD):    5.950ns = ( 105.950 - 100.000 ) 
        Source Clock Delay      (SCD):    9.869ns
        Clock Pessimism Removal (CPR):    3.774ns
      Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
        Total System Jitter     (TSJ):    0.071ns
        Total Input Jitter      (TIJ):    0.000ns
        Discrete Jitter          (DJ):    0.000ns
        Phase Error              (PE):    0.000ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock dac_clk_in_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        M6                                                0.000     5.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.857     5.857 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.354     6.211    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.650     6.861 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.584     7.445    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.093     7.538 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.419     7.958    dac_clk_out_s
                             BUFR (Prop_bufr_I_O)         0.650     8.608 r  BUFR_inst/O
                             net (fo=1, unplaced)         0.584     9.192    dac_clk_in_s
                             BUFG (Prop_bufg_I_O)         0.093     9.285 r  BUFG_inst/O
                             net (fo=100264, unplaced)    0.584     9.869    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/IPCORE_CLK
                             DSP48E1                                      r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Product_Im_1_reg[0]__0/CLK
      -------------------------------------------------------------------    -------------------
                             DSP48E1 (Prop_dsp48e1_CLK_P[0])
                                                          0.348    10.217 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Product_Im_1_reg[0]__0/P[0]
                             net (fo=2, unplaced)         0.419    10.636    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Product_Im_1_reg[0]__0_n_105
                             LUT2 (Prop_lut2_I0_O)        0.043    10.679 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_570/O
                             net (fo=1, unplaced)         0.000    10.679    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_570_n_0
                             CARRY4 (Prop_carry4_S[1]_CO[3])
                                                          0.256    10.935 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_563/CO[3]
                             net (fo=1, unplaced)         0.007    10.942    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_563_n_0
                             CARRY4 (Prop_carry4_CI_CO[3])
                                                          0.054    10.996 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_558/CO[3]
                             net (fo=1, unplaced)         0.000    10.996    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_558_n_0
                             CARRY4 (Prop_carry4_CI_CO[3])
                                                          0.054    11.050 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_553/CO[3]
                             net (fo=1, unplaced)         0.000    11.050    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_553_n_0
                             CARRY4 (Prop_carry4_CI_O[3])
                                                          0.157    11.207 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_548/O[3]
                             net (fo=2, unplaced)         0.302    11.509    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_548_n_4
                             LUT3 (Prop_lut3_I2_O)        0.120    11.629 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_542/O
                             net (fo=2, unplaced)         0.281    11.910    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_542_n_0
                             LUT4 (Prop_lut4_I3_O)        0.043    11.953 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_545/O
                             net (fo=1, unplaced)         0.000    11.953    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_545_n_0
                             CARRY4 (Prop_carry4_S[1]_CO[3])
                                                          0.256    12.209 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_516/CO[3]
                             net (fo=1, unplaced)         0.007    12.216    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_516_n_0
                             CARRY4 (Prop_carry4_CI_O[3])
                                                          0.157    12.373 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_430/O[3]
                             net (fo=2, unplaced)         0.302    12.675    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_430_n_4
                             LUT3 (Prop_lut3_I1_O)        0.120    12.795 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_247/O
                             net (fo=2, unplaced)         0.281    13.076    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_247_n_0
                             LUT4 (Prop_lut4_I3_O)        0.043    13.119 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_251/O
                             net (fo=1, unplaced)         0.000    13.119    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_251_n_0
                             CARRY4 (Prop_carry4_S[0]_CO[3])
                                                          0.246    13.365 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_131/CO[3]
                             net (fo=1, unplaced)         0.000    13.365    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[0]_INST_0_i_131_n_0
                             CARRY4 (Prop_carry4_CI_O[3])
                                                          0.157    13.522 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_PolyPhaseFIRFilter1/Imag_Out[4]_INST_0_i_55/O[3]
                             net (fo=2, unplaced)         0.302    13.824    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0_n_364
                             LUT3 (Prop_lut3_I0_O)        0.120    13.944 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/Imag_Out[4]_INST_0_i_36/O
                             net (fo=2, unplaced)         0.281    14.225    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/Imag_Out[4]_INST_0_i_36_n_0
                             LUT4 (Prop_lut4_I3_O)        0.043    14.268 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/Imag_Out[4]_INST_0_i_40/O
                             net (fo=1, unplaced)         0.000    14.268    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/Imag_Out[4]_INST_0_i_40_n_0
                             CARRY4 (Prop_carry4_S[0]_CO[3])
                                                          0.246    14.514 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/Imag_Out[4]_INST_0_i_14/CO[3]
                             net (fo=1, unplaced)         0.000    14.514    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/Imag_Out[4]_INST_0_i_14_n_0
                             CARRY4 (Prop_carry4_CI_O[3])
                                                          0.157    14.671 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/Imag_Out[8]_INST_0_i_14/O[3]
                             net (fo=3, unplaced)         0.309    14.980    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/Imag_Out[8]_INST_0_i_14_n_4
                             LUT3 (Prop_lut3_I1_O)        0.120    15.100 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/Imag_Out[8]_INST_0_i_16/O
                             net (fo=2, unplaced)         0.281    15.381    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/Imag_Out[8]_INST_0_i_16_n_0
                             LUT5 (Prop_lut5_I1_O)        0.043    15.424 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/Imag_Out[8]_INST_0_i_4/O
                             net (fo=2, unplaced)         0.253    15.677    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/Imag_Out[8]_INST_0_i_4_n_0
                             LUT6 (Prop_lut6_I0_O)        0.043    15.720 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/Imag_Out[8]_INST_0_i_8/O
                             net (fo=1, unplaced)         0.000    15.720    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/Imag_Out[8]_INST_0_i_8_n_0
                             CARRY4 (Prop_carry4_S[0]_CO[3])
                                                          0.246    15.966 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/Imag_Out[8]_INST_0/CO[3]
                             net (fo=1, unplaced)         0.000    15.966    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/Imag_Out[8]_INST_0_n_0
                             CARRY4 (Prop_carry4_CI_O[1])
                                                          0.173    16.139 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/Imag_Out[12]_INST_0/O[1]
                             net (fo=3, unplaced)         0.419    16.559    i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_Q/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/din[13]
                             RAMB18E1                                     r  i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_Q/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/DIADI[13]
      -------------------------------------------------------------------    -------------------
    
                             (clock dac_clk_in_s rise edge)
                                                        100.000   100.000 r  
                             clock source latency         2.000   102.000    
        M6                                                0.000   102.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000   102.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.756   102.756 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.209   102.965    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.614   103.579 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.439   104.018    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.083   104.101 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.274   104.375    dac_clk_out_s
                             BUFR (Prop_bufr_I_O)         0.614   104.989 r  BUFR_inst/O
                             net (fo=1, unplaced)         0.439   105.428    dac_clk_in_s
                             BUFG (Prop_bufg_I_O)         0.083   105.511 r  BUFG_inst/O
                             net (fo=100264, unplaced)    0.439   105.950    i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_Q/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/wr_clk
                             RAMB18E1                                     r  i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_Q/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/CLKARDCLK
                             clock pessimism              3.774   109.724    
                             clock uncertainty           -0.035   109.689    
                             RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[13])
                                                         -0.623   109.066    i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_Q/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram
      -------------------------------------------------------------------
                             required time                        109.066    
                             arrival time                         -16.559    
      -------------------------------------------------------------------
                             slack                                 92.507    
    
    
    
    
    
    Min Delay Paths
    --------------------------------------------------------------------------------------
    Slack (VIOLATED) :        -0.043ns  (arrival time - required time)
      Source:                 i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_IFFT_M_Point/u_IFFT_HDL_Optimized/u_SDF1_1_1/u_SDFCOMMUTATOR_1/SDFCummutator_wrXData_im_reg_reg[2]/C
                                (rising edge-triggered cell FDRE clocked by dac_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Destination:            i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_IFFT_M_Point/u_IFFT_HDL_Optimized/u_SDF1_1_1/u_SDFCOMMUTATOR_1/u_dataXMEM_im_0_1/ram_reg_0_7_0_5/RAMB/I
                                (rising edge-triggered cell RAMD32 clocked by dac_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Path Group:             dac_clk_in_s
      Path Type:              Hold (Min at Fast Process Corner)
      Requirement:            0.000ns  (dac_clk_in_s rise@0.000ns - dac_clk_in_s rise@0.000ns)
      Data Path Delay:        0.198ns  (logic 0.104ns (52.598%)  route 0.094ns (47.402%))
      Logic Levels:           0  
      Clock Path Skew:        0.145ns (DCD - SCD - CPR)
        Destination Clock Delay (DCD):    7.164ns
        Source Clock Delay      (SCD):    3.294ns
        Clock Pessimism Removal (CPR):    3.725ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock dac_clk_in_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         2.000     2.000    
        M6                                                0.000     2.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     2.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.341     2.341 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.040     2.381    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.223     2.604 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.114     2.718    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.026     2.744 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.074     2.817    dac_clk_out_s
                             BUFR (Prop_bufr_I_O)         0.223     3.040 r  BUFR_inst/O
                             net (fo=1, unplaced)         0.114     3.154    dac_clk_in_s
                             BUFG (Prop_bufg_I_O)         0.026     3.180 r  BUFG_inst/O
                             net (fo=100264, unplaced)    0.114     3.294    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_IFFT_M_Point/u_IFFT_HDL_Optimized/u_SDF1_1_1/u_SDFCOMMUTATOR_1/IPCORE_CLK
                             FDRE                                         r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_IFFT_M_Point/u_IFFT_HDL_Optimized/u_SDF1_1_1/u_SDFCOMMUTATOR_1/SDFCummutator_wrXData_im_reg_reg[2]/C
      -------------------------------------------------------------------    -------------------
                             FDRE (Prop_fdre_C_Q)         0.104     3.398 r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_IFFT_M_Point/u_IFFT_HDL_Optimized/u_SDF1_1_1/u_SDFCOMMUTATOR_1/SDFCummutator_wrXData_im_reg_reg[2]/Q
                             net (fo=1, unplaced)         0.094     3.492    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_IFFT_M_Point/u_IFFT_HDL_Optimized/u_SDF1_1_1/u_SDFCOMMUTATOR_1/u_dataXMEM_im_0_1/ram_reg_0_7_0_5/DIB0
                             RAMD32                                       r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_IFFT_M_Point/u_IFFT_HDL_Optimized/u_SDF1_1_1/u_SDFCOMMUTATOR_1/u_dataXMEM_im_0_1/ram_reg_0_7_0_5/RAMB/I
      -------------------------------------------------------------------    -------------------
    
                             (clock dac_clk_in_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        M6                                                0.000     5.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.421     5.421 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.185     5.606    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.251     5.857 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.259     6.116    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.030     6.146 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.219     6.365    dac_clk_out_s
                             BUFR (Prop_bufr_I_O)         0.251     6.616 r  BUFR_inst/O
                             net (fo=1, unplaced)         0.259     6.875    dac_clk_in_s
                             BUFG (Prop_bufg_I_O)         0.030     6.905 r  BUFG_inst/O
                             net (fo=100264, unplaced)    0.259     7.164    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_IFFT_M_Point/u_IFFT_HDL_Optimized/u_SDF1_1_1/u_SDFCOMMUTATOR_1/u_dataXMEM_im_0_1/ram_reg_0_7_0_5/WCLK
                             RAMD32                                       r  i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_IFFT_M_Point/u_IFFT_HDL_Optimized/u_SDF1_1_1/u_SDFCOMMUTATOR_1/u_dataXMEM_im_0_1/ram_reg_0_7_0_5/RAMB/CLK
                             clock pessimism             -3.725     3.439    
                             RAMD32 (Hold_ramd32_CLK_I)
                                                          0.096     3.535    i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_IFFT_M_Point/u_IFFT_HDL_Optimized/u_SDF1_1_1/u_SDFCOMMUTATOR_1/u_dataXMEM_im_0_1/ram_reg_0_7_0_5/RAMB
      -------------------------------------------------------------------
                             required time                         -3.535    
                             arrival time                           3.492    
      -------------------------------------------------------------------
                             slack                                 -0.043    
    
    
    
    
    
    Pulse Width Checks
    --------------------------------------------------------------------------------------
    Clock Name:         dac_clk_in_s
    Waveform(ns):       { 0.000 50.000 }
    Period(ns):         100.000
    Sources:            { BUFR_inst/O }
    
    Check Type        Corner  Lib Pin      Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location  Pin
    Min Period        n/a     DSP48E1/CLK  n/a            2.772         100.000     97.228               i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_IFFT_M_Point/u_IFFT_HDL_Optimized/u_SDF1_9_1/u_MUL4/Complex4Multiply_mult2_re_pipe1_reg/CLK
    Low Pulse Width   Slow    RAMD32/CLK   n/a            0.768         50.000      49.232               i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_IFFT_M_Point/u_IFFT_HDL_Optimized/u_SDF1_9_1/u_SDFCOMMUTATOR_9/u_dataXMEM_im_0_9/ram_reg_0_7_0_5/RAMA/CLK
    High Pulse Width  Slow    RAMD32/CLK   n/a            0.768         50.000      49.232               i_system_wrapper/system_i/HDLTx_noaxi_int16IPC_0/U0/u_HDLTx_noaxi_int16IPCo_ip_dut_inst/u_HDLTx_noaxi_int16IPCo_ip_src_HDLTxIPCore/u_HDLTx/u_M_SynthesizerHDLOptimized2/u_IFFT_M_Point/u_IFFT_HDL_Optimized/u_SDF1_9_1/u_SDFCOMMUTATOR_9/u_dataXMEM_im_0_9/ram_reg_0_7_0_5/RAMA/CLK
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  clk_out1_system_sys_audio_clkgen_0
      To Clock:  clk_fpga_0
    
    Setup :            0  Failing Endpoints,  Worst Slack        9.082ns,  Total Violation        0.000ns
    Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             9.082ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMB/CLK
                                (rising edge-triggered cell RAMD32 clocked by clk_out1_system_sys_audio_clkgen_0  {rise@0.000ns fall@40.690ns period=81.380ns})
      Destination:            i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/rx_gen.rx_sync/out_data_reg[2]/D
                                (rising edge-triggered cell FDRE clocked by clk_fpga_0  {rise@0.000ns fall@5.000ns period=10.000ns})
      Path Group:             clk_fpga_0
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            10.000ns  (MaxDelay Path 10.000ns)
      Data Path Delay:        0.905ns  (logic 0.713ns (78.785%)  route 0.192ns (21.215%))
      Logic Levels:           0  
      Timing Exception:       MaxDelay Path 10.000ns -datapath_only
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                                                          0.000     0.000 r  i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMB/CLK
                             RAMD32 (Prop_ramd32_CLK_O)
                                                          0.713     0.713 r  i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/rx_gen.rx_sync/fifo_reg_0_3_0_4/RAMB/O
                             net (fo=1, unplaced)         0.192     0.905    i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/rx_gen.rx_sync/out_data0__0[2]
                             FDRE                                         r  i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/rx_gen.rx_sync/out_data_reg[2]/D
      -------------------------------------------------------------------    -------------------
    
                             max delay                   10.000    10.000    
                             FDRE (Setup_fdre_C_D)       -0.013     9.987    i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/rx_gen.rx_sync/out_data_reg[2]
      -------------------------------------------------------------------
                             required time                          9.987    
                             arrival time                          -0.905    
      -------------------------------------------------------------------
                             slack                                  9.082    
    
    
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  adc_clk_div_s
      To Clock:  clk_fpga_0
    
    Setup :            0  Failing Endpoints,  Worst Slack        8.253ns,  Total Violation        0.000ns
    Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             8.253ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/axi_adrv9001_rx1_dma/inst/i_transfer/i_request_arb/eot_mem_dest_reg_r2_0_15_0_0/DP/CLK
                                (rising edge-triggered cell RAMD32 clocked by adc_clk_div_s  {rise@0.000ns fall@25.000ns period=50.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001_rx1_dma/inst/i_transfer/i_request_arb/i_dest_dma_mm/i_addr_gen/length_reg[0]/S
                                (rising edge-triggered cell FDSE clocked by clk_fpga_0  {rise@0.000ns fall@5.000ns period=10.000ns})
      Path Group:             clk_fpga_0
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            10.000ns  (MaxDelay Path 10.000ns)
      Data Path Delay:        1.445ns  (logic 0.739ns (51.142%)  route 0.706ns (48.858%))
      Logic Levels:           1  (LUT2=1)
      Timing Exception:       MaxDelay Path 10.000ns -datapath_only
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                                                          0.000     0.000 r  i_system_wrapper/system_i/axi_adrv9001_rx1_dma/inst/i_transfer/i_request_arb/eot_mem_dest_reg_r2_0_15_0_0/DP/CLK
                             RAMD32 (Prop_ramd32_CLK_O)
                                                          0.696     0.696 f  i_system_wrapper/system_i/axi_adrv9001_rx1_dma/inst/i_transfer/i_request_arb/eot_mem_dest_reg_r2_0_15_0_0/DP/O
                             net (fo=4, unplaced)         0.294     0.990    i_system_wrapper/system_i/axi_adrv9001_rx1_dma/inst/i_transfer/i_request_arb/i_dest_dma_mm/i_addr_gen/dest_address_eot
                             LUT2 (Prop_lut2_I1_O)        0.043     1.033 r  i_system_wrapper/system_i/axi_adrv9001_rx1_dma/inst/i_transfer/i_request_arb/i_dest_dma_mm/i_addr_gen/length[3]_i_1/O
                             net (fo=4, unplaced)         0.412     1.445    i_system_wrapper/system_i/axi_adrv9001_rx1_dma/inst/i_transfer/i_request_arb/i_dest_dma_mm/i_addr_gen/length
                             FDSE                                         r  i_system_wrapper/system_i/axi_adrv9001_rx1_dma/inst/i_transfer/i_request_arb/i_dest_dma_mm/i_addr_gen/length_reg[0]/S
      -------------------------------------------------------------------    -------------------
    
                             max delay                   10.000    10.000    
                             FDSE (Setup_fdse_C_S)       -0.302     9.698    i_system_wrapper/system_i/axi_adrv9001_rx1_dma/inst/i_transfer/i_request_arb/i_dest_dma_mm/i_addr_gen/length_reg[0]
      -------------------------------------------------------------------
                             required time                          9.698    
                             arrival time                          -1.445    
      -------------------------------------------------------------------
                             slack                                  8.253    
    
    
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  adc_clk_div_s_1
      To Clock:  clk_fpga_0
    
    Setup :            0  Failing Endpoints,  Worst Slack        9.249ns,  Total Violation        0.000ns
    Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             9.249ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/axi_adrv9001_tx2_dma/inst/i_transfer/i_request_arb/i_response_manager/i_dest_response_fifo/cdc_sync_fifo_ram_reg[0]/C
                                (rising edge-triggered cell FDRE clocked by adc_clk_div_s_1  {rise@0.000ns fall@25.000ns period=50.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001_tx2_dma/inst/i_transfer/i_request_arb/i_response_manager/req_eot_reg/D
                                (rising edge-triggered cell FDRE clocked by clk_fpga_0  {rise@0.000ns fall@5.000ns period=10.000ns})
      Path Group:             clk_fpga_0
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            10.000ns  (MaxDelay Path 10.000ns)
      Data Path Delay:        0.794ns  (logic 0.360ns (45.340%)  route 0.434ns (54.660%))
      Logic Levels:           1  (LUT5=1)
      Timing Exception:       MaxDelay Path 10.000ns -datapath_only
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                                                          0.000     0.000 r  i_system_wrapper/system_i/axi_adrv9001_tx2_dma/inst/i_transfer/i_request_arb/i_response_manager/i_dest_response_fifo/cdc_sync_fifo_ram_reg[0]/C
                             FDRE (Prop_fdre_C_Q)         0.233     0.233 r  i_system_wrapper/system_i/axi_adrv9001_tx2_dma/inst/i_transfer/i_request_arb/i_response_manager/i_dest_response_fifo/cdc_sync_fifo_ram_reg[0]/Q
                             net (fo=1, unplaced)         0.434     0.667    i_system_wrapper/system_i/axi_adrv9001_tx2_dma/inst/i_transfer/i_request_arb/i_response_manager/i_dest_response_fifo/i_waddr_sync/cdc_sync_fifo_ram
                             LUT5 (Prop_lut5_I0_O)        0.127     0.794 r  i_system_wrapper/system_i/axi_adrv9001_tx2_dma/inst/i_transfer/i_request_arb/i_response_manager/i_dest_response_fifo/i_waddr_sync/req_eot_i_1/O
                             net (fo=1, unplaced)         0.000     0.794    i_system_wrapper/system_i/axi_adrv9001_tx2_dma/inst/i_transfer/i_request_arb/i_response_manager/i_dest_response_fifo_n_5
                             FDRE                                         r  i_system_wrapper/system_i/axi_adrv9001_tx2_dma/inst/i_transfer/i_request_arb/i_response_manager/req_eot_reg/D
      -------------------------------------------------------------------    -------------------
    
                             max delay                   10.000    10.000    
                             FDRE (Setup_fdre_C_D)        0.043    10.043    i_system_wrapper/system_i/axi_adrv9001_tx2_dma/inst/i_transfer/i_request_arb/i_response_manager/req_eot_reg
      -------------------------------------------------------------------
                             required time                         10.043    
                             arrival time                          -0.794    
      -------------------------------------------------------------------
                             slack                                  9.249    
    
    
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  adc_clk_in_s
      To Clock:  clk_fpga_0
    
    Setup :            0  Failing Endpoints,  Worst Slack        8.253ns,  Total Violation        0.000ns
    Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             8.253ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/eot_mem_dest_reg_r2_0_15_0_0/DP/CLK
                                (rising edge-triggered cell RAMD32 clocked by adc_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_dest_dma_mm/i_addr_gen/length_reg[0]/S
                                (rising edge-triggered cell FDSE clocked by clk_fpga_0  {rise@0.000ns fall@5.000ns period=10.000ns})
      Path Group:             clk_fpga_0
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            10.000ns  (MaxDelay Path 10.000ns)
      Data Path Delay:        1.445ns  (logic 0.739ns (51.142%)  route 0.706ns (48.858%))
      Logic Levels:           1  (LUT2=1)
      Timing Exception:       MaxDelay Path 10.000ns -datapath_only
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                                                          0.000     0.000 r  i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/eot_mem_dest_reg_r2_0_15_0_0/DP/CLK
                             RAMD32 (Prop_ramd32_CLK_O)
                                                          0.696     0.696 f  i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/eot_mem_dest_reg_r2_0_15_0_0/DP/O
                             net (fo=4, unplaced)         0.294     0.990    i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_dest_dma_mm/i_addr_gen/dest_address_eot
                             LUT2 (Prop_lut2_I1_O)        0.043     1.033 r  i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_dest_dma_mm/i_addr_gen/length[3]_i_1/O
                             net (fo=4, unplaced)         0.412     1.445    i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_dest_dma_mm/i_addr_gen/length
                             FDSE                                         r  i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_dest_dma_mm/i_addr_gen/length_reg[0]/S
      -------------------------------------------------------------------    -------------------
    
                             max delay                   10.000    10.000    
                             FDSE (Setup_fdse_C_S)       -0.302     9.698    i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_dest_dma_mm/i_addr_gen/length_reg[0]
      -------------------------------------------------------------------
                             required time                          9.698    
                             arrival time                          -1.445    
      -------------------------------------------------------------------
                             slack                                  8.253    
    
    
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  clk_fpga_0
      To Clock:  clk_out1_system_sys_audio_clkgen_0
    
    Setup :            0  Failing Endpoints,  Worst Slack       80.462ns,  Total Violation        0.000ns
    Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             80.462ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/tx_sync/fifo_reg_0_3_0_4/RAMB/CLK
                                (rising edge-triggered cell RAMD32 clocked by clk_fpga_0  {rise@0.000ns fall@5.000ns period=10.000ns})
      Destination:            i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/tx_sync/out_data_reg[2]/D
                                (rising edge-triggered cell FDRE clocked by clk_out1_system_sys_audio_clkgen_0  {rise@0.000ns fall@40.690ns period=81.380ns})
      Path Group:             clk_out1_system_sys_audio_clkgen_0
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            81.380ns  (MaxDelay Path 81.380ns)
      Data Path Delay:        0.905ns  (logic 0.713ns (78.785%)  route 0.192ns (21.215%))
      Logic Levels:           0  
      Timing Exception:       MaxDelay Path 81.380ns -datapath_only
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                                                          0.000     0.000 r  i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/tx_sync/fifo_reg_0_3_0_4/RAMB/CLK
                             RAMD32 (Prop_ramd32_CLK_O)
                                                          0.713     0.713 r  i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/tx_sync/fifo_reg_0_3_0_4/RAMB/O
                             net (fo=1, unplaced)         0.192     0.905    i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/tx_sync/out_data0[2]
                             FDRE                                         r  i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/tx_sync/out_data_reg[2]/D
      -------------------------------------------------------------------    -------------------
    
                             max delay                   81.380    81.380    
                             FDRE (Setup_fdre_C_D)       -0.013    81.367    i_system_wrapper/system_i/axi_i2s_adi/U0/ctrl/tx_sync/out_data_reg[2]
      -------------------------------------------------------------------
                             required time                         81.367    
                             arrival time                          -0.905    
      -------------------------------------------------------------------
                             slack                                 80.462    
    
    
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  clk_fpga_0
      To Clock:  adc_clk_div_s
    
    Setup :            0  Failing Endpoints,  Worst Slack        9.426ns,  Total Violation        0.000ns
    Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             9.426ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/axi_adrv9001_rx1_dma/inst/i_transfer/i_request_arb/i_store_and_forward/dest_id_reg[0]/C
                                (rising edge-triggered cell FDRE clocked by clk_fpga_0  {rise@0.000ns fall@5.000ns period=10.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001_rx1_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_src_sync_id/cdc_sync_stage1_reg[0]/D
                                (rising edge-triggered cell FDRE clocked by adc_clk_div_s  {rise@0.000ns fall@25.000ns period=50.000ns})
      Path Group:             adc_clk_div_s
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            10.000ns  (MaxDelay Path 10.000ns)
      Data Path Delay:        0.481ns  (logic 0.233ns (48.441%)  route 0.248ns (51.559%))
      Logic Levels:           0  
      Timing Exception:       MaxDelay Path 10.000ns -datapath_only
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                                                          0.000     0.000 r  i_system_wrapper/system_i/axi_adrv9001_rx1_dma/inst/i_transfer/i_request_arb/i_store_and_forward/dest_id_reg[0]/C
                             FDRE (Prop_fdre_C_Q)         0.233     0.233 r  i_system_wrapper/system_i/axi_adrv9001_rx1_dma/inst/i_transfer/i_request_arb/i_store_and_forward/dest_id_reg[0]/Q
                             net (fo=19, unplaced)        0.248     0.481    i_system_wrapper/system_i/axi_adrv9001_rx1_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_src_sync_id/Q[0]
                             FDRE                                         r  i_system_wrapper/system_i/axi_adrv9001_rx1_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_src_sync_id/cdc_sync_stage1_reg[0]/D
      -------------------------------------------------------------------    -------------------
    
                             max delay                   10.000    10.000    
                             FDRE (Setup_fdre_C_D)       -0.093     9.907    i_system_wrapper/system_i/axi_adrv9001_rx1_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_src_sync_id/cdc_sync_stage1_reg[0]
      -------------------------------------------------------------------
                             required time                          9.907    
                             arrival time                          -0.481    
      -------------------------------------------------------------------
                             slack                                  9.426    
    
    
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  adc_clk_div_s_1
      To Clock:  adc_clk_div_s
    
    Setup :            0  Failing Endpoints,  Worst Slack       45.481ns,  Total Violation        0.000ns
    Hold  :           34  Failing Endpoints,  Worst Slack       -3.402ns,  Total Violation     -115.289ns
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             45.481ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_cntrl/d_data_cntrl_int_reg[38]/C
                                (rising edge-triggered cell FDCE clocked by adc_clk_div_s_1  {rise@0.000ns fall@25.000ns period=50.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_rx_channel_2/adc_valid_in_d_reg/D
                                (rising edge-triggered cell FDRE clocked by adc_clk_div_s  {rise@0.000ns fall@25.000ns period=50.000ns})
      Path Group:             adc_clk_div_s
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            50.000ns  (adc_clk_div_s rise@50.000ns - adc_clk_div_s_1 rise@0.000ns)
      Data Path Delay:        0.956ns  (logic 0.356ns (37.238%)  route 0.600ns (62.761%))
      Logic Levels:           1  (LUT6=1)
      Clock Path Skew:        -3.570ns (DCD - SCD + CPR)
        Destination Clock Delay (DCD):    4.388ns = ( 54.388 - 50.000 ) 
        Source Clock Delay      (SCD):    7.958ns
        Clock Pessimism Removal (CPR):    0.000ns
      Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
        Total System Jitter     (TSJ):    0.071ns
        Total Input Jitter      (TIJ):    0.000ns
        Discrete Jitter          (DJ):    0.000ns
        Phase Error              (PE):    0.000ns
      Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock adc_clk_div_s_1 rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        M6                                                0.000     5.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.857     5.857 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.354     6.211    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.650     6.861 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.584     7.445    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.093     7.538 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.419     7.958    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_cntrl/d_xfer_toggle_reg_0
                             FDCE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_cntrl/d_data_cntrl_int_reg[38]/C
      -------------------------------------------------------------------    -------------------
                             FDCE (Prop_fdce_C_Q)         0.233     8.191 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_cntrl/d_data_cntrl_int_reg[38]/Q
                             net (fo=35, unplaced)        0.600     8.791    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1_ctrl_sync/rx2_single_lane_loc
                             LUT6 (Prop_lut6_I0_O)        0.123     8.914 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1_ctrl_sync/adc_valid_in_d_i_1__0/O
                             net (fo=1, unplaced)         0.000     8.914    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_rx_channel_2/adc_valid_B0
                             FDRE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_rx_channel_2/adc_valid_in_d_reg/D
      -------------------------------------------------------------------    -------------------
    
                             (clock adc_clk_div_s rise edge)
                                                         50.000    50.000 r  
                             clock source latency         2.000    52.000    
        J4                                                0.000    52.000 r  rx1_dclk_in_p (IN)
                             net (fo=0)                   0.000    52.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/rx1_dclk_in_p_dclk_in
        J4                   IBUFDS (Prop_ibufds_I_O)     0.768    52.768 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.209    52.977    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.614    53.591 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.439    54.030    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.083    54.113 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/I_bufg/O
                             net (fo=12415, unplaced)     0.274    54.388    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_rx_channel_2/adc_clk_div
                             FDRE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_rx_channel_2/adc_valid_in_d_reg/C
                             clock pessimism              0.000    54.388    
                             clock uncertainty           -0.035    54.352    
                             FDRE (Setup_fdre_C_D)        0.043    54.395    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_rx_channel_2/adc_valid_in_d_reg
      -------------------------------------------------------------------
                             required time                         54.395    
                             arrival time                          -8.914    
      -------------------------------------------------------------------
                             slack                                 45.481    
    
    
    
    
    
    Min Delay Paths
    --------------------------------------------------------------------------------------
    Slack (VIOLATED) :        -3.402ns  (arrival time - required time)
      Source:                 i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_link/i_rx_pack_8_to_16_1/odata_reg[0]/C
                                (rising edge-triggered cell FDRE clocked by adc_clk_div_s_1  {rise@0.000ns fall@25.000ns period=50.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_rx_channel_3/adc_data_in_d_reg[0]/D
                                (rising edge-triggered cell FDRE clocked by adc_clk_div_s  {rise@0.000ns fall@25.000ns period=50.000ns})
      Path Group:             adc_clk_div_s
      Path Type:              Hold (Min at Fast Process Corner)
      Requirement:            0.000ns  (adc_clk_div_s rise@0.000ns - adc_clk_div_s_1 rise@0.000ns)
      Data Path Delay:        0.263ns  (logic 0.168ns (63.947%)  route 0.095ns (36.053%))
      Logic Levels:           1  (LUT5=1)
      Clock Path Skew:        3.560ns (DCD - SCD - CPR)
        Destination Clock Delay (DCD):    6.378ns
        Source Clock Delay      (SCD):    2.817ns
        Clock Pessimism Removal (CPR):    -0.000ns
      Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
        Total System Jitter     (TSJ):    0.071ns
        Total Input Jitter      (TIJ):    0.000ns
        Discrete Jitter          (DJ):    0.000ns
        Phase Error              (PE):    0.000ns
      Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock adc_clk_div_s_1 rise edge)
                                                          0.000     0.000 r  
                             clock source latency         2.000     2.000    
        M6                                                0.000     2.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     2.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.341     2.341 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.040     2.381    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.223     2.604 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.114     2.718    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.026     2.744 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.074     2.817    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_link/i_rx_pack_8_to_16_1/CLK
                             FDRE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_link/i_rx_pack_8_to_16_1/odata_reg[0]/C
      -------------------------------------------------------------------    -------------------
                             FDRE (Prop_fdre_C_Q)         0.104     2.921 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_link/i_rx_pack_8_to_16_1/odata_reg[0]/Q
                             net (fo=1, unplaced)         0.095     3.016    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1_ctrl_sync/adc_data_in_d_reg[15]_1[0]
                             LUT5 (Prop_lut5_I4_O)        0.064     3.080 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1_ctrl_sync/adc_data_in_d[0]_i_1__0/O
                             net (fo=2, unplaced)         0.000     3.080    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_rx_channel_3/adc_data_in_d_reg[15]_0[0]
                             FDRE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_rx_channel_3/adc_data_in_d_reg[0]/D
      -------------------------------------------------------------------    -------------------
    
                             (clock adc_clk_div_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        J4                                                0.000     5.000 r  rx1_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/rx1_dclk_in_p_dclk_in
        J4                   IBUFDS (Prop_ibufds_I_O)     0.434     5.434 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.185     5.619    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.251     5.870 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.259     6.129    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.030     6.159 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/I_bufg/O
                             net (fo=12415, unplaced)     0.219     6.378    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_rx_channel_3/adc_clk_div
                             FDRE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_rx_channel_3/adc_data_in_d_reg[0]/C
                             clock pessimism              0.000     6.378    
                             clock uncertainty            0.035     6.413    
                             FDRE (Hold_fdre_C_D)         0.069     6.482    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_rx_channel_3/adc_data_in_d_reg[0]
      -------------------------------------------------------------------
                             required time                         -6.482    
                             arrival time                           3.080    
      -------------------------------------------------------------------
                             slack                                 -3.402    
    
    
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  clk_fpga_0
      To Clock:  adc_clk_div_s_1
    
    Setup :            0  Failing Endpoints,  Worst Slack        9.432ns,  Total Violation        0.000ns
    Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             9.432ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/axi_adrv9001_tx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/src_id_reg[0]/C
                                (rising edge-triggered cell FDRE clocked by clk_fpga_0  {rise@0.000ns fall@5.000ns period=10.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001_tx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_dest_sync_id/cdc_sync_stage1_reg[0]/D
                                (rising edge-triggered cell FDRE clocked by adc_clk_div_s_1  {rise@0.000ns fall@25.000ns period=50.000ns})
      Path Group:             adc_clk_div_s_1
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            10.000ns  (MaxDelay Path 10.000ns)
      Data Path Delay:        0.475ns  (logic 0.233ns (49.053%)  route 0.242ns (50.947%))
      Logic Levels:           0  
      Timing Exception:       MaxDelay Path 10.000ns -datapath_only
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                                                          0.000     0.000 r  i_system_wrapper/system_i/axi_adrv9001_tx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/src_id_reg[0]/C
                             FDRE (Prop_fdre_C_Q)         0.233     0.233 r  i_system_wrapper/system_i/axi_adrv9001_tx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/src_id_reg[0]/Q
                             net (fo=15, unplaced)        0.242     0.475    i_system_wrapper/system_i/axi_adrv9001_tx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_dest_sync_id/cdc_sync_stage1_reg[3]_0[0]
                             FDRE                                         r  i_system_wrapper/system_i/axi_adrv9001_tx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_dest_sync_id/cdc_sync_stage1_reg[0]/D
      -------------------------------------------------------------------    -------------------
    
                             max delay                   10.000    10.000    
                             FDRE (Setup_fdre_C_D)       -0.093     9.907    i_system_wrapper/system_i/axi_adrv9001_tx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_dest_sync_id/cdc_sync_stage1_reg[0]
      -------------------------------------------------------------------
                             required time                          9.907    
                             arrival time                          -0.475    
      -------------------------------------------------------------------
                             slack                                  9.432    
    
    
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  adc_clk_div_s
      To Clock:  adc_clk_div_s_1
    
    Setup :            0  Failing Endpoints,  Worst Slack       45.476ns,  Total Violation        0.000ns
    Hold  :           34  Failing Endpoints,  Worst Slack       -3.354ns,  Total Violation     -113.821ns
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             45.476ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tdd_1/tdd_sync_cntr_reg/C
                                (rising edge-triggered cell FDRE clocked by adc_clk_div_s  {rise@0.000ns fall@25.000ns period=50.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tdd_2/i_tdd_control/tdd_sync_d1_reg/D
                                (rising edge-triggered cell FDRE clocked by adc_clk_div_s_1  {rise@0.000ns fall@25.000ns period=50.000ns})
      Path Group:             adc_clk_div_s_1
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            50.000ns  (adc_clk_div_s_1 rise@50.000ns - adc_clk_div_s rise@0.000ns)
      Data Path Delay:        0.936ns  (logic 0.399ns (42.628%)  route 0.537ns (57.372%))
      Logic Levels:           2  (LUT2=2)
      Clock Path Skew:        -3.595ns (DCD - SCD + CPR)
        Destination Clock Delay (DCD):    4.375ns = ( 54.375 - 50.000 ) 
        Source Clock Delay      (SCD):    7.970ns
        Clock Pessimism Removal (CPR):    0.000ns
      Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
        Total System Jitter     (TSJ):    0.071ns
        Total Input Jitter      (TIJ):    0.000ns
        Discrete Jitter          (DJ):    0.000ns
        Phase Error              (PE):    0.000ns
      Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock adc_clk_div_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        J4                                                0.000     5.000 r  rx1_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/rx1_dclk_in_p_dclk_in
        J4                   IBUFDS (Prop_ibufds_I_O)     0.870     5.870 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.354     6.224    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.650     6.874 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.584     7.458    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.093     7.551 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/I_bufg/O
                             net (fo=12415, unplaced)     0.419     7.970    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tdd_1/adc_clk_div
                             FDRE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tdd_1/tdd_sync_cntr_reg/C
      -------------------------------------------------------------------    -------------------
                             FDRE (Prop_fdre_C_Q)         0.233     8.203 f  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tdd_1/tdd_sync_cntr_reg/Q
                             net (fo=1, unplaced)         0.267     8.470    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tdd_1/tdd_sync_cntr1
                             LUT2 (Prop_lut2_I0_O)        0.123     8.593 f  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tdd_1/tdd_sync_cntr_INST_0/O
                             net (fo=1, unplaced)         0.270     8.863    i_system_wrapper/tdd_sync_cntr
                             LUT2 (Prop_lut2_I1_O)        0.043     8.906 r  i_system_wrapper/system_i_i_34/O
                             net (fo=2, unplaced)         0.000     8.906    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tdd_2/i_tdd_control/tdd_sync
                             FDRE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tdd_2/i_tdd_control/tdd_sync_d1_reg/D
      -------------------------------------------------------------------    -------------------
    
                             (clock adc_clk_div_s_1 rise edge)
                                                         50.000    50.000 r  
                             clock source latency         2.000    52.000    
        M6                                                0.000    52.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000    52.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.756    52.756 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.209    52.965    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.614    53.579 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.439    54.018    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.083    54.101 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.274    54.375    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tdd_2/i_tdd_control/out_reg[0]
                             FDRE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tdd_2/i_tdd_control/tdd_sync_d1_reg/C
                             clock pessimism              0.000    54.375    
                             clock uncertainty           -0.035    54.340    
                             FDRE (Setup_fdre_C_D)        0.043    54.383    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tdd_2/i_tdd_control/tdd_sync_d1_reg
      -------------------------------------------------------------------
                             required time                         54.383    
                             arrival time                          -8.906    
      -------------------------------------------------------------------
                             slack                                 45.476    
    
    
    
    
    
    Min Delay Paths
    --------------------------------------------------------------------------------------
    Slack (VIOLATED) :        -3.354ns  (arrival time - required time)
      Source:                 i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_tx_channel_2/dac_data_iq_out_reg[0]/C
                                (rising edge-triggered cell FDRE clocked by adc_clk_div_s  {rise@0.000ns fall@25.000ns period=50.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001/inst/i_core/tx1_data_i_B_d_reg[0]/D
                                (rising edge-triggered cell FDRE clocked by adc_clk_div_s_1  {rise@0.000ns fall@25.000ns period=50.000ns})
      Path Group:             adc_clk_div_s_1
      Path Type:              Hold (Min at Fast Process Corner)
      Requirement:            0.000ns  (adc_clk_div_s_1 rise@0.000ns - adc_clk_div_s rise@0.000ns)
      Data Path Delay:        0.203ns  (logic 0.104ns (51.186%)  route 0.099ns (48.814%))
      Logic Levels:           0  
      Clock Path Skew:        3.535ns (DCD - SCD - CPR)
        Destination Clock Delay (DCD):    6.365ns
        Source Clock Delay      (SCD):    2.830ns
        Clock Pessimism Removal (CPR):    -0.000ns
      Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
        Total System Jitter     (TSJ):    0.071ns
        Total Input Jitter      (TIJ):    0.000ns
        Discrete Jitter          (DJ):    0.000ns
        Phase Error              (PE):    0.000ns
      Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock adc_clk_div_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         2.000     2.000    
        J4                                                0.000     2.000 r  rx1_dclk_in_p (IN)
                             net (fo=0)                   0.000     2.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/rx1_dclk_in_p_dclk_in
        J4                   IBUFDS (Prop_ibufds_I_O)     0.353     2.353 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.040     2.393    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.223     2.616 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.114     2.730    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.026     2.756 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/I_bufg/O
                             net (fo=12415, unplaced)     0.074     2.830    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_tx_channel_2/adc_clk_div
                             FDRE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_tx_channel_2/dac_data_iq_out_reg[0]/C
      -------------------------------------------------------------------    -------------------
                             FDRE (Prop_fdre_C_Q)         0.104     2.934 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_tx_channel_2/dac_data_iq_out_reg[0]/Q
                             net (fo=2, unplaced)         0.099     3.033    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/tx1_data_i_B[0]
                             FDRE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/tx1_data_i_B_d_reg[0]/D
      -------------------------------------------------------------------    -------------------
    
                             (clock adc_clk_div_s_1 rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        M6                                                0.000     5.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.421     5.421 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.185     5.606    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.251     5.857 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.259     6.116    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.030     6.146 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.219     6.365    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/d_xfer_count_reg[0]
                             FDRE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/tx1_data_i_B_d_reg[0]/C
                             clock pessimism              0.000     6.365    
                             clock uncertainty            0.035     6.401    
                             FDRE (Hold_fdre_C_D)        -0.013     6.388    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/tx1_data_i_B_d_reg[0]
      -------------------------------------------------------------------
                             required time                         -6.388    
                             arrival time                           3.033    
      -------------------------------------------------------------------
                             slack                                 -3.354    
    
    
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  adc_clk_in_s
      To Clock:  adc_clk_div_s_1
    
    Setup :            0  Failing Endpoints,  Worst Slack       47.180ns,  Total Violation        0.000ns
    Hold  :            0  Failing Endpoints,  Worst Slack        0.637ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             47.180ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_src_dma_fifo/overflow_reg/C
                                (rising edge-triggered cell FDRE clocked by adc_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_status/d_acc_data_reg[0]/D
                                (rising edge-triggered cell FDCE clocked by adc_clk_div_s_1  {rise@0.000ns fall@25.000ns period=50.000ns})
      Path Group:             adc_clk_div_s_1
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            50.000ns  (adc_clk_div_s_1 rise@50.000ns - adc_clk_in_s rise@0.000ns)
      Data Path Delay:        0.772ns  (logic 0.356ns (46.114%)  route 0.416ns (53.886%))
      Logic Levels:           1  (LUT5=1)
      Clock Path Skew:        -2.056ns (DCD - SCD + CPR)
        Destination Clock Delay (DCD):    4.375ns = ( 54.375 - 50.000 ) 
        Source Clock Delay      (SCD):    9.869ns
        Clock Pessimism Removal (CPR):    3.438ns
      Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
        Total System Jitter     (TSJ):    0.071ns
        Total Input Jitter      (TIJ):    0.000ns
        Discrete Jitter          (DJ):    0.000ns
        Phase Error              (PE):    0.000ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock adc_clk_in_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        M6                                                0.000     5.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.857     5.857 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.354     6.211    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.650     6.861 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.584     7.445    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.093     7.538 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.419     7.958    adc_clk_out_s
                             BUFR (Prop_bufr_I_O)         0.650     8.608 r  BUFR_inst2/O
                             net (fo=1, unplaced)         0.584     9.192    adc_clk_in_s
                             BUFG (Prop_bufg_I_O)         0.093     9.285 r  BUFG_inst2/O
                             net (fo=23764, unplaced)     0.584     9.869    i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_src_dma_fifo/fifo_wr_clk
                             FDRE                                         r  i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_src_dma_fifo/overflow_reg/C
      -------------------------------------------------------------------    -------------------
                             FDRE (Prop_fdre_C_Q)         0.233    10.102 r  i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_src_dma_fifo/overflow_reg/Q
                             net (fo=1, unplaced)         0.416    10.518    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_status/adc_2_dovf
                             LUT5 (Prop_lut5_I3_O)        0.123    10.641 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_status/d_acc_data[0]_i_1__2/O
                             net (fo=1, unplaced)         0.000    10.641    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_status/d_acc_data[0]
                             FDCE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_status/d_acc_data_reg[0]/D
      -------------------------------------------------------------------    -------------------
    
                             (clock adc_clk_div_s_1 rise edge)
                                                         50.000    50.000 r  
                             clock source latency         2.000    52.000    
        M6                                                0.000    52.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000    52.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.756    52.756 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.209    52.965    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.614    53.579 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.439    54.018    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.083    54.101 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.274    54.375    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_status/d_xfer_state_reg_0
                             FDCE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_status/d_acc_data_reg[0]/C
                             clock pessimism              3.438    57.813    
                             clock uncertainty           -0.035    57.778    
                             FDCE (Setup_fdce_C_D)        0.043    57.821    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_status/d_acc_data_reg[0]
      -------------------------------------------------------------------
                             required time                         57.821    
                             arrival time                         -10.641    
      -------------------------------------------------------------------
                             slack                                 47.180    
    
    
    
    
    
    Min Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             0.637ns  (arrival time - required time)
      Source:                 i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_src_dma_fifo/overflow_reg/C
                                (rising edge-triggered cell FDRE clocked by adc_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_status/d_acc_data_reg[0]/D
                                (rising edge-triggered cell FDCE clocked by adc_clk_div_s_1  {rise@0.000ns fall@25.000ns period=50.000ns})
      Path Group:             adc_clk_div_s_1
      Path Type:              Hold (Min at Fast Process Corner)
      Requirement:            0.000ns  (adc_clk_div_s_1 rise@0.000ns - adc_clk_in_s rise@0.000ns)
      Data Path Delay:        0.374ns  (logic 0.168ns (44.884%)  route 0.206ns (55.116%))
      Logic Levels:           1  (LUT5=1)
      Clock Path Skew:        -0.332ns (DCD - SCD - CPR)
        Destination Clock Delay (DCD):    6.365ns
        Source Clock Delay      (SCD):    3.294ns
        Clock Pessimism Removal (CPR):    3.403ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock adc_clk_in_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         2.000     2.000    
        M6                                                0.000     2.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     2.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.341     2.341 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.040     2.381    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.223     2.604 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.114     2.718    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.026     2.744 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.074     2.817    adc_clk_out_s
                             BUFR (Prop_bufr_I_O)         0.223     3.040 r  BUFR_inst2/O
                             net (fo=1, unplaced)         0.114     3.154    adc_clk_in_s
                             BUFG (Prop_bufg_I_O)         0.026     3.180 r  BUFG_inst2/O
                             net (fo=23764, unplaced)     0.114     3.294    i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_src_dma_fifo/fifo_wr_clk
                             FDRE                                         r  i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_src_dma_fifo/overflow_reg/C
      -------------------------------------------------------------------    -------------------
                             FDRE (Prop_fdre_C_Q)         0.104     3.398 r  i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_src_dma_fifo/overflow_reg/Q
                             net (fo=1, unplaced)         0.206     3.605    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_status/adc_2_dovf
                             LUT5 (Prop_lut5_I3_O)        0.064     3.669 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_status/d_acc_data[0]_i_1__2/O
                             net (fo=1, unplaced)         0.000     3.669    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_status/d_acc_data[0]
                             FDCE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_status/d_acc_data_reg[0]/D
      -------------------------------------------------------------------    -------------------
    
                             (clock adc_clk_div_s_1 rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        M6                                                0.000     5.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.421     5.421 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.185     5.606    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.251     5.857 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.259     6.116    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.030     6.146 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.219     6.365    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_status/d_xfer_state_reg_0
                             FDCE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_status/d_acc_data_reg[0]/C
                             clock pessimism             -3.403     2.962    
                             FDCE (Hold_fdce_C_D)         0.069     3.031    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_status/d_acc_data_reg[0]
      -------------------------------------------------------------------
                             required time                         -3.031    
                             arrival time                           3.669    
      -------------------------------------------------------------------
                             slack                                  0.637    
    
    
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  dac_clk_in_s
      To Clock:  adc_clk_div_s_1
    
    Setup :            0  Failing Endpoints,  Worst Slack       99.485ns,  Total Violation        0.000ns
    Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             99.485ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
                                (rising edge-triggered cell FDRE clocked by dac_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Destination:            i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                                (rising edge-triggered cell FDRE clocked by adc_clk_div_s_1  {rise@0.000ns fall@25.000ns period=50.000ns})
      Path Group:             adc_clk_div_s_1
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            100.000ns  (MaxDelay Path 100.000ns)
      Data Path Delay:        0.422ns  (logic 0.233ns (55.213%)  route 0.189ns (44.787%))
      Logic Levels:           0  
      Timing Exception:       MaxDelay Path 100.000ns -datapath_only
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                                                          0.000     0.000 r  i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
                             FDRE (Prop_fdre_C_Q)         0.233     0.233 r  i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                             net (fo=1, unplaced)         0.189     0.422    i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0]
                             FDRE                                         r  i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
      -------------------------------------------------------------------    -------------------
    
                             max delay                  100.000   100.000    
                             FDRE (Setup_fdre_C_D)       -0.093    99.907    i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]
      -------------------------------------------------------------------
                             required time                         99.907    
                             arrival time                          -0.422    
      -------------------------------------------------------------------
                             slack                                 99.485    
    
    
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  clk_fpga_0
      To Clock:  adc_clk_in_s
    
    Setup :            0  Failing Endpoints,  Worst Slack        9.426ns,  Total Violation        0.000ns
    Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             9.426ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/dest_id_reg[0]/C
                                (rising edge-triggered cell FDRE clocked by clk_fpga_0  {rise@0.000ns fall@5.000ns period=10.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_src_sync_id/cdc_sync_stage1_reg[0]/D
                                (rising edge-triggered cell FDRE clocked by adc_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Path Group:             adc_clk_in_s
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            10.000ns  (MaxDelay Path 10.000ns)
      Data Path Delay:        0.481ns  (logic 0.233ns (48.441%)  route 0.248ns (51.559%))
      Logic Levels:           0  
      Timing Exception:       MaxDelay Path 10.000ns -datapath_only
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                                                          0.000     0.000 r  i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/dest_id_reg[0]/C
                             FDRE (Prop_fdre_C_Q)         0.233     0.233 r  i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/dest_id_reg[0]/Q
                             net (fo=19, unplaced)        0.248     0.481    i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_src_sync_id/Q[0]
                             FDRE                                         r  i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_src_sync_id/cdc_sync_stage1_reg[0]/D
      -------------------------------------------------------------------    -------------------
    
                             max delay                   10.000    10.000    
                             FDRE (Setup_fdre_C_D)       -0.093     9.907    i_system_wrapper/system_i/axi_adrv9001_rx2_dma/inst/i_transfer/i_request_arb/i_store_and_forward/i_src_sync_id/cdc_sync_stage1_reg[0]
      -------------------------------------------------------------------
                             required time                          9.907    
                             arrival time                          -0.481    
      -------------------------------------------------------------------
                             slack                                  9.426    
    
    
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  adc_clk_div_s_1
      To Clock:  adc_clk_in_s
    
    Setup :            0  Failing Endpoints,  Worst Slack       49.485ns,  Total Violation        0.000ns
    Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             49.485ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/FIFO_Delay_0/U0/FIFO_8192_16bit_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
                                (rising edge-triggered cell FDRE clocked by adc_clk_div_s_1  {rise@0.000ns fall@25.000ns period=50.000ns})
      Destination:            i_system_wrapper/system_i/FIFO_Delay_0/U0/FIFO_8192_16bit_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                                (rising edge-triggered cell FDRE clocked by adc_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Path Group:             adc_clk_in_s
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            50.000ns  (MaxDelay Path 50.000ns)
      Data Path Delay:        0.422ns  (logic 0.233ns (55.213%)  route 0.189ns (44.787%))
      Logic Levels:           0  
      Timing Exception:       MaxDelay Path 50.000ns -datapath_only
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                                                          0.000     0.000 r  i_system_wrapper/system_i/FIFO_Delay_0/U0/FIFO_8192_16bit_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
                             FDRE (Prop_fdre_C_Q)         0.233     0.233 r  i_system_wrapper/system_i/FIFO_Delay_0/U0/FIFO_8192_16bit_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                             net (fo=1, unplaced)         0.189     0.422    i_system_wrapper/system_i/FIFO_Delay_0/U0/FIFO_8192_16bit_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0]
                             FDRE                                         r  i_system_wrapper/system_i/FIFO_Delay_0/U0/FIFO_8192_16bit_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
      -------------------------------------------------------------------    -------------------
    
                             max delay                   50.000    50.000    
                             FDRE (Setup_fdre_C_D)       -0.093    49.907    i_system_wrapper/system_i/FIFO_Delay_0/U0/FIFO_8192_16bit_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]
      -------------------------------------------------------------------
                             required time                         49.907    
                             arrival time                          -0.422    
      -------------------------------------------------------------------
                             slack                                 49.485    
    
    
    
    
    
    ---------------------------------------------------------------------------------------------------
    From Clock:  adc_clk_div_s_1
      To Clock:  dac_clk_in_s
    
    Setup :            0  Failing Endpoints,  Worst Slack       49.485ns,  Total Violation        0.000ns
    Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             49.485ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                                (rising edge-triggered cell FDRE clocked by adc_clk_div_s_1  {rise@0.000ns fall@25.000ns period=50.000ns})
      Destination:            i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                                (rising edge-triggered cell FDRE clocked by dac_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Path Group:             dac_clk_in_s
      Path Type:              Setup (Max at Slow Process Corner)
      Requirement:            50.000ns  (MaxDelay Path 50.000ns)
      Data Path Delay:        0.422ns  (logic 0.233ns (55.213%)  route 0.189ns (44.787%))
      Logic Levels:           0  
      Timing Exception:       MaxDelay Path 50.000ns -datapath_only
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                                                          0.000     0.000 r  i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                             FDRE (Prop_fdre_C_Q)         0.233     0.233 r  i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                             net (fo=1, unplaced)         0.189     0.422    i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0]
                             FDRE                                         r  i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
      -------------------------------------------------------------------    -------------------
    
                             max delay                   50.000    50.000    
                             FDRE (Setup_fdre_C_D)       -0.093    49.907    i_system_wrapper/system_i/FIFO_Expander_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]
      -------------------------------------------------------------------
                             required time                         49.907    
                             arrival time                          -0.422    
      -------------------------------------------------------------------
                             slack                                 49.485    
    
    
    
    
    
    ---------------------------------------------------------------------------------------------------
    Path Group:  **async_default**
    From Clock:  adc_clk_div_s
      To Clock:  adc_clk_div_s
    
    Setup :            0  Failing Endpoints,  Worst Slack       48.491ns,  Total Violation        0.000ns
    Hold  :            0  Failing Endpoints,  Worst Slack        0.198ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             48.491ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_up_dac_common/i_xfer_cntrl/d_data_cntrl_int_reg[0]/C
                                (rising edge-triggered cell FDCE clocked by adc_clk_div_s  {rise@0.000ns fall@25.000ns period=50.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_tx_channel_0/i_up_dac_channel/i_xfer_cntrl/d_data_cntrl_int_reg[0]/CLR
                                (recovery check against rising-edge clock adc_clk_div_s  {rise@0.000ns fall@25.000ns period=50.000ns})
      Path Group:             **async_default**
      Path Type:              Recovery (Max at Slow Process Corner)
      Requirement:            50.000ns  (adc_clk_div_s rise@50.000ns - adc_clk_div_s rise@0.000ns)
      Data Path Delay:        1.154ns  (logic 0.356ns (30.849%)  route 0.798ns (69.151%))
      Logic Levels:           1  (LUT1=1)
      Clock Path Skew:        -0.145ns (DCD - SCD + CPR)
        Destination Clock Delay (DCD):    4.388ns = ( 54.388 - 50.000 ) 
        Source Clock Delay      (SCD):    7.970ns
        Clock Pessimism Removal (CPR):    3.438ns
      Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
        Total System Jitter     (TSJ):    0.071ns
        Total Input Jitter      (TIJ):    0.000ns
        Discrete Jitter          (DJ):    0.000ns
        Phase Error              (PE):    0.000ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock adc_clk_div_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        J4                                                0.000     5.000 r  rx1_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/rx1_dclk_in_p_dclk_in
        J4                   IBUFDS (Prop_ibufds_I_O)     0.870     5.870 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.354     6.224    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.650     6.874 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.584     7.458    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.093     7.551 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/I_bufg/O
                             net (fo=12415, unplaced)     0.419     7.970    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_up_dac_common/i_xfer_cntrl/adc_clk_div
                             FDCE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_up_dac_common/i_xfer_cntrl/d_data_cntrl_int_reg[0]/C
      -------------------------------------------------------------------    -------------------
                             FDCE (Prop_fdce_C_Q)         0.233     8.203 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_up_dac_common/i_xfer_cntrl/d_data_cntrl_int_reg[0]/Q
                             net (fo=43, unplaced)        0.270     8.473    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_up_dac_common/i_xfer_cntrl/Q[0]
                             LUT1 (Prop_lut1_I0_O)        0.123     8.596 f  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_up_dac_common/i_xfer_cntrl/dac_1_rst_INST_0/O
                             net (fo=591, unplaced)       0.528     9.124    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_tx_channel_0/i_up_dac_channel/i_xfer_cntrl/d_data_cntrl_int_reg[0]_1
                             FDCE                                         f  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_tx_channel_0/i_up_dac_channel/i_xfer_cntrl/d_data_cntrl_int_reg[0]/CLR
      -------------------------------------------------------------------    -------------------
    
                             (clock adc_clk_div_s rise edge)
                                                         50.000    50.000 r  
                             clock source latency         2.000    52.000    
        J4                                                0.000    52.000 r  rx1_dclk_in_p (IN)
                             net (fo=0)                   0.000    52.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/rx1_dclk_in_p_dclk_in
        J4                   IBUFDS (Prop_ibufds_I_O)     0.768    52.768 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.209    52.977    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.614    53.591 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.439    54.030    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.083    54.113 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/I_bufg/O
                             net (fo=12415, unplaced)     0.274    54.388    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_tx_channel_0/i_up_dac_channel/i_xfer_cntrl/adc_clk_div
                             FDCE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_tx_channel_0/i_up_dac_channel/i_xfer_cntrl/d_data_cntrl_int_reg[0]/C
                             clock pessimism              3.438    57.825    
                             clock uncertainty           -0.035    57.790    
                             FDCE (Recov_fdce_C_CLR)     -0.175    57.615    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_tx_channel_0/i_up_dac_channel/i_xfer_cntrl/d_data_cntrl_int_reg[0]
      -------------------------------------------------------------------
                             required time                         57.615    
                             arrival time                          -9.124    
      -------------------------------------------------------------------
                             slack                                 48.491    
    
    
    
    
    
    Min Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             0.198ns  (arrival time - required time)
      Source:                 i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_up_adc_common/i_core_rst_reg/rst_reg/C
                                (rising edge-triggered cell FDRE clocked by adc_clk_div_s  {rise@0.000ns fall@25.000ns period=50.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_up_adc_common/i_clock_mon/d_count_run_m1_reg/CLR
                                (removal check against rising-edge clock adc_clk_div_s  {rise@0.000ns fall@25.000ns period=50.000ns})
      Path Group:             **async_default**
      Path Type:              Removal (Min at Fast Process Corner)
      Requirement:            0.000ns  (adc_clk_div_s rise@0.000ns - adc_clk_div_s rise@0.000ns)
      Data Path Delay:        0.239ns  (logic 0.104ns (43.535%)  route 0.135ns (56.465%))
      Logic Levels:           0  
      Clock Path Skew:        0.145ns (DCD - SCD - CPR)
        Destination Clock Delay (DCD):    6.378ns
        Source Clock Delay      (SCD):    2.830ns
        Clock Pessimism Removal (CPR):    3.403ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock adc_clk_div_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         2.000     2.000    
        J4                                                0.000     2.000 r  rx1_dclk_in_p (IN)
                             net (fo=0)                   0.000     2.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/rx1_dclk_in_p_dclk_in
        J4                   IBUFDS (Prop_ibufds_I_O)     0.353     2.353 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.040     2.393    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.223     2.616 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.114     2.730    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.026     2.756 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/I_bufg/O
                             net (fo=12415, unplaced)     0.074     2.830    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_up_adc_common/i_core_rst_reg/adc_clk_div
                             FDRE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_up_adc_common/i_core_rst_reg/rst_reg/C
      -------------------------------------------------------------------    -------------------
                             FDRE (Prop_fdre_C_Q)         0.104     2.934 f  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_up_adc_common/i_core_rst_reg/rst_reg/Q
                             net (fo=23, unplaced)        0.135     3.069    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_up_adc_common/i_clock_mon/AR[0]
                             FDCE                                         f  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_up_adc_common/i_clock_mon/d_count_run_m1_reg/CLR
      -------------------------------------------------------------------    -------------------
    
                             (clock adc_clk_div_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        J4                                                0.000     5.000 r  rx1_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/rx1_dclk_in_p_dclk_in
        J4                   IBUFDS (Prop_ibufds_I_O)     0.434     5.434 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.185     5.619    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.251     5.870 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.259     6.129    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.030     6.159 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/I_bufg/O
                             net (fo=12415, unplaced)     0.219     6.378    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_up_adc_common/i_clock_mon/adc_clk_div
                             FDCE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_up_adc_common/i_clock_mon/d_count_run_m1_reg/C
                             clock pessimism             -3.403     2.975    
                             FDCE (Remov_fdce_C_CLR)     -0.104     2.871    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx1/core_enabled.i_up_adc_common/i_clock_mon/d_count_run_m1_reg
      -------------------------------------------------------------------
                             required time                         -2.871    
                             arrival time                           3.069    
      -------------------------------------------------------------------
                             slack                                  0.198    
    
    
    
    
    
    ---------------------------------------------------------------------------------------------------
    Path Group:  **async_default**
    From Clock:  adc_clk_div_s_1
      To Clock:  adc_clk_div_s_1
    
    Setup :            0  Failing Endpoints,  Worst Slack       48.514ns,  Total Violation        0.000ns
    Hold  :            0  Failing Endpoints,  Worst Slack        0.178ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             48.514ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_cntrl/d_data_cntrl_int_reg[0]/C
                                (rising edge-triggered cell FDCE clocked by adc_clk_div_s_1  {rise@0.000ns fall@25.000ns period=50.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_rx_channel_0/i_up_adc_channel/i_xfer_cntrl/d_data_cntrl_int_reg[0]/CLR
                                (recovery check against rising-edge clock adc_clk_div_s_1  {rise@0.000ns fall@25.000ns period=50.000ns})
      Path Group:             **async_default**
      Path Type:              Recovery (Max at Slow Process Corner)
      Requirement:            50.000ns  (adc_clk_div_s_1 rise@50.000ns - adc_clk_div_s_1 rise@0.000ns)
      Data Path Delay:        1.131ns  (logic 0.356ns (31.477%)  route 0.775ns (68.523%))
      Logic Levels:           1  (LUT1=1)
      Clock Path Skew:        -0.145ns (DCD - SCD + CPR)
        Destination Clock Delay (DCD):    4.375ns = ( 54.375 - 50.000 ) 
        Source Clock Delay      (SCD):    7.958ns
        Clock Pessimism Removal (CPR):    3.438ns
      Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
        Total System Jitter     (TSJ):    0.071ns
        Total Input Jitter      (TIJ):    0.000ns
        Discrete Jitter          (DJ):    0.000ns
        Phase Error              (PE):    0.000ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock adc_clk_div_s_1 rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        M6                                                0.000     5.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.857     5.857 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.354     6.211    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.650     6.861 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.584     7.445    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.093     7.538 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.419     7.958    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_cntrl/d_xfer_toggle_reg_0
                             FDCE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_cntrl/d_data_cntrl_int_reg[0]/C
      -------------------------------------------------------------------    -------------------
                             FDCE (Prop_fdce_C_Q)         0.233     8.191 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_cntrl/d_data_cntrl_int_reg[0]/Q
                             net (fo=17, unplaced)        0.247     8.438    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_cntrl/d_data_cntrl_int_reg[0]_1
                             LUT1 (Prop_lut1_I0_O)        0.123     8.561 f  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_up_adc_common/i_xfer_cntrl/d_data_cntrl_int[72]_i_2/O
                             net (fo=574, unplaced)       0.528     9.089    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_rx_channel_0/i_up_adc_channel/i_xfer_cntrl/AR[0]
                             FDCE                                         f  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_rx_channel_0/i_up_adc_channel/i_xfer_cntrl/d_data_cntrl_int_reg[0]/CLR
      -------------------------------------------------------------------    -------------------
    
                             (clock adc_clk_div_s_1 rise edge)
                                                         50.000    50.000 r  
                             clock source latency         2.000    52.000    
        M6                                                0.000    52.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000    52.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.756    52.756 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.209    52.965    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.614    53.579 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.439    54.018    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.083    54.101 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.274    54.375    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_rx_channel_0/i_up_adc_channel/i_xfer_cntrl/d_xfer_toggle_reg_0
                             FDCE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_rx_channel_0/i_up_adc_channel/i_xfer_cntrl/d_data_cntrl_int_reg[0]/C
                             clock pessimism              3.438    57.813    
                             clock uncertainty           -0.035    57.778    
                             FDCE (Recov_fdce_C_CLR)     -0.175    57.603    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_rx2/core_enabled.i_rx_channel_0/i_up_adc_channel/i_xfer_cntrl/d_data_cntrl_int_reg[0]
      -------------------------------------------------------------------
                             required time                         57.603    
                             arrival time                          -9.089    
      -------------------------------------------------------------------
                             slack                                 48.514    
    
    
    
    
    
    Min Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             0.178ns  (arrival time - required time)
      Source:                 i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C
                                (rising edge-triggered cell FDPE clocked by adc_clk_div_s_1  {rise@0.000ns fall@25.000ns period=50.000ns})
      Destination:            i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/PRE
                                (removal check against rising-edge clock adc_clk_div_s_1  {rise@0.000ns fall@25.000ns period=50.000ns})
      Path Group:             **async_default**
      Path Type:              Removal (Min at Fast Process Corner)
      Requirement:            0.000ns  (adc_clk_div_s_1 rise@0.000ns - adc_clk_div_s_1 rise@0.000ns)
      Data Path Delay:        0.217ns  (logic 0.104ns (48.021%)  route 0.113ns (51.979%))
      Logic Levels:           0  
      Clock Path Skew:        0.145ns (DCD - SCD - CPR)
        Destination Clock Delay (DCD):    6.365ns
        Source Clock Delay      (SCD):    2.817ns
        Clock Pessimism Removal (CPR):    3.403ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock adc_clk_div_s_1 rise edge)
                                                          0.000     0.000 r  
                             clock source latency         2.000     2.000    
        M6                                                0.000     2.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     2.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.341     2.341 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.040     2.381    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.223     2.604 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.114     2.718    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.026     2.744 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.074     2.817    i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
                             FDPE                                         r  i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C
      -------------------------------------------------------------------    -------------------
                             FDPE (Prop_fdpe_C_Q)         0.104     2.921 f  i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/Q
                             net (fo=3, unplaced)         0.113     3.034    i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/out
                             FDPE                                         f  i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/PRE
      -------------------------------------------------------------------    -------------------
    
                             (clock adc_clk_div_s_1 rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        M6                                                0.000     5.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.421     5.421 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.185     5.606    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.251     5.857 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.259     6.116    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.030     6.146 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.219     6.365    i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/wr_clk
                             FDPE                                         r  i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/C
                             clock pessimism             -3.403     2.962    
                             FDPE (Remov_fdpe_C_PRE)     -0.106     2.856    i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg
      -------------------------------------------------------------------
                             required time                         -2.856    
                             arrival time                           3.034    
      -------------------------------------------------------------------
                             slack                                  0.178    
    
    
    
    
    
    ---------------------------------------------------------------------------------------------------
    Path Group:  **async_default**
    From Clock:  adc_clk_in_s
      To Clock:  adc_clk_in_s
    
    Setup :            0  Failing Endpoints,  Worst Slack       99.008ns,  Total Violation        0.000ns
    Hold  :            0  Failing Endpoints,  Worst Slack        0.176ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             99.008ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C
                                (rising edge-triggered cell FDPE clocked by adc_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Destination:            i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE
                                (recovery check against rising-edge clock adc_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Path Group:             **async_default**
      Path Type:              Recovery (Max at Slow Process Corner)
      Requirement:            100.000ns  (adc_clk_in_s rise@100.000ns - adc_clk_in_s rise@0.000ns)
      Data Path Delay:        0.524ns  (logic 0.233ns (44.466%)  route 0.291ns (55.534%))
      Logic Levels:           0  
      Clock Path Skew:        -0.145ns (DCD - SCD + CPR)
        Destination Clock Delay (DCD):    5.950ns = ( 105.950 - 100.000 ) 
        Source Clock Delay      (SCD):    9.869ns
        Clock Pessimism Removal (CPR):    3.774ns
      Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
        Total System Jitter     (TSJ):    0.071ns
        Total Input Jitter      (TIJ):    0.000ns
        Discrete Jitter          (DJ):    0.000ns
        Phase Error              (PE):    0.000ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock adc_clk_in_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        M6                                                0.000     5.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.857     5.857 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.354     6.211    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.650     6.861 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.584     7.445    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.093     7.538 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.419     7.958    adc_clk_out_s
                             BUFR (Prop_bufr_I_O)         0.650     8.608 r  BUFR_inst2/O
                             net (fo=1, unplaced)         0.584     9.192    adc_clk_in_s
                             BUFG (Prop_bufg_I_O)         0.093     9.285 r  BUFG_inst2/O
                             net (fo=23764, unplaced)     0.584     9.869    i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
                             FDPE                                         r  i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C
      -------------------------------------------------------------------    -------------------
                             FDPE (Prop_fdpe_C_Q)         0.233    10.102 f  i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q
                             net (fo=50, unplaced)        0.291    10.393    i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/AS[0]
                             FDPE                                         f  i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE
      -------------------------------------------------------------------    -------------------
    
                             (clock adc_clk_in_s rise edge)
                                                        100.000   100.000 r  
                             clock source latency         2.000   102.000    
        M6                                                0.000   102.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000   102.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.756   102.756 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.209   102.965    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.614   103.579 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.439   104.018    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.083   104.101 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.274   104.375    adc_clk_out_s
                             BUFR (Prop_bufr_I_O)         0.614   104.989 r  BUFR_inst2/O
                             net (fo=1, unplaced)         0.439   105.428    adc_clk_in_s
                             BUFG (Prop_bufg_I_O)         0.083   105.511 r  BUFG_inst2/O
                             net (fo=23764, unplaced)     0.439   105.950    i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/rd_clk
                             FDPE                                         r  i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/C
                             clock pessimism              3.774   109.724    
                             clock uncertainty           -0.035   109.689    
                             FDPE (Recov_fdpe_C_PRE)     -0.288   109.401    i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg
      -------------------------------------------------------------------
                             required time                        109.401    
                             arrival time                         -10.393    
      -------------------------------------------------------------------
                             slack                                 99.008    
    
    
    
    
    
    Min Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             0.176ns  (arrival time - required time)
      Source:                 i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C
                                (rising edge-triggered cell FDPE clocked by adc_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Destination:            i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR
                                (removal check against rising-edge clock adc_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Path Group:             **async_default**
      Path Type:              Removal (Min at Fast Process Corner)
      Requirement:            0.000ns  (adc_clk_in_s rise@0.000ns - adc_clk_in_s rise@0.000ns)
      Data Path Delay:        0.217ns  (logic 0.104ns (48.021%)  route 0.113ns (51.979%))
      Logic Levels:           0  
      Clock Path Skew:        0.145ns (DCD - SCD - CPR)
        Destination Clock Delay (DCD):    7.164ns
        Source Clock Delay      (SCD):    3.294ns
        Clock Pessimism Removal (CPR):    3.725ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock adc_clk_in_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         2.000     2.000    
        M6                                                0.000     2.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     2.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.341     2.341 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.040     2.381    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.223     2.604 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.114     2.718    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.026     2.744 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.074     2.817    adc_clk_out_s
                             BUFR (Prop_bufr_I_O)         0.223     3.040 r  BUFR_inst2/O
                             net (fo=1, unplaced)         0.114     3.154    adc_clk_in_s
                             BUFG (Prop_bufg_I_O)         0.026     3.180 r  BUFG_inst2/O
                             net (fo=23764, unplaced)     0.114     3.294    i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk
                             FDPE                                         r  i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C
      -------------------------------------------------------------------    -------------------
                             FDPE (Prop_fdpe_C_Q)         0.104     3.398 f  i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/Q
                             net (fo=3, unplaced)         0.113     3.511    i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst_rd_reg2
                             FDCE                                         f  i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR
      -------------------------------------------------------------------    -------------------
    
                             (clock adc_clk_in_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        M6                                                0.000     5.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.421     5.421 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.185     5.606    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.251     5.857 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.259     6.116    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.030     6.146 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.219     6.365    adc_clk_out_s
                             BUFR (Prop_bufr_I_O)         0.251     6.616 r  BUFR_inst2/O
                             net (fo=1, unplaced)         0.259     6.875    adc_clk_in_s
                             BUFG (Prop_bufg_I_O)         0.030     6.905 r  BUFG_inst2/O
                             net (fo=23764, unplaced)     0.259     7.164    i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
                             FDCE                                         r  i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/C
                             clock pessimism             -3.725     3.439    
                             FDCE (Remov_fdce_C_CLR)     -0.104     3.335    i_system_wrapper/system_i/Streamer_Top_1/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]
      -------------------------------------------------------------------
                             required time                         -3.335    
                             arrival time                           3.511    
      -------------------------------------------------------------------
                             slack                                  0.176    
    
    
    
    
    
    ---------------------------------------------------------------------------------------------------
    Path Group:  **async_default**
    From Clock:  clk_fpga_0
      To Clock:  clk_fpga_0
    
    Setup :            0  Failing Endpoints,  Worst Slack        8.301ns,  Total Violation        0.000ns
    Hold  :            0  Failing Endpoints,  Worst Slack        0.178ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             8.301ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/sys_rstgen/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                                (rising edge-triggered cell FDRE clocked by clk_fpga_0  {rise@0.000ns fall@5.000ns period=10.000ns})
      Destination:            i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_up_dac_common/up_core_preset_reg/PRE
                                (recovery check against rising-edge clock clk_fpga_0  {rise@0.000ns fall@5.000ns period=10.000ns})
      Path Group:             **async_default**
      Path Type:              Recovery (Max at Slow Process Corner)
      Requirement:            10.000ns  (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
      Data Path Delay:        1.192ns  (logic 0.356ns (29.866%)  route 0.836ns (70.134%))
      Logic Levels:           1  (LUT1=1)
      Clock Path Skew:        -0.145ns (DCD - SCD + CPR)
        Destination Clock Delay (DCD):    0.756ns = ( 10.756 - 10.000 ) 
        Source Clock Delay      (SCD):    0.932ns
        Clock Pessimism Removal (CPR):    0.031ns
      Clock Uncertainty:      0.154ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
        Total System Jitter     (TSJ):    0.071ns
        Total Input Jitter      (TIJ):    0.300ns
        Discrete Jitter          (DJ):    0.000ns
        Phase Error              (PE):    0.000ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock clk_fpga_0 rise edge)
                                                          0.000     0.000 r  
        PS7_X0Y0             PS7                          0.000     0.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
                             net (fo=1, unplaced)         0.419     0.419    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
                             BUFG (Prop_bufg_I_O)         0.093     0.512 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
                             net (fo=21577, unplaced)     0.419     0.932    i_system_wrapper/system_i/sys_rstgen/U0/slowest_sync_clk
                             FDRE                                         r  i_system_wrapper/system_i/sys_rstgen/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
      -------------------------------------------------------------------    -------------------
                             FDRE (Prop_fdre_C_Q)         0.233     1.165 r  i_system_wrapper/system_i/sys_rstgen/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                             net (fo=198, unplaced)       0.308     1.473    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_tx_channel_2/i_up_dac_channel/i_xfer_cntrl/s_axi_aresetn
                             LUT1 (Prop_lut1_I0_O)        0.123     1.596 f  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_tx_channel_2/i_up_dac_channel/i_xfer_cntrl/up_axi_awready_int_i_1/O
                             net (fo=5494, unplaced)      0.528     2.124    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_up_dac_common/up_xfer_toggle_m1_reg
                             FDPE                                         f  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_up_dac_common/up_core_preset_reg/PRE
      -------------------------------------------------------------------    -------------------
    
                             (clock clk_fpga_0 rise edge)
                                                         10.000    10.000 r  
        PS7_X0Y0             PS7                          0.000    10.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
                             net (fo=1, unplaced)         0.398    10.398    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
                             BUFG (Prop_bufg_I_O)         0.083    10.481 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
                             net (fo=21577, unplaced)     0.274    10.756    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_up_dac_common/s_axi_aclk
                             FDPE                                         r  i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_up_dac_common/up_core_preset_reg/C
                             clock pessimism              0.031    10.787    
                             clock uncertainty           -0.154    10.633    
                             FDPE (Recov_fdpe_C_PRE)     -0.208    10.425    i_system_wrapper/system_i/axi_adrv9001/inst/i_core/i_tx1/core_enabled.i_up_dac_common/up_core_preset_reg
      -------------------------------------------------------------------
                             required time                         10.425    
                             arrival time                          -2.124    
      -------------------------------------------------------------------
                             slack                                  8.301    
    
    
    
    
    
    Min Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             0.178ns  (arrival time - required time)
      Source:                 i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_clkgen/up_mmcm_preset_reg/C
                                (rising edge-triggered cell FDPE clocked by clk_fpga_0  {rise@0.000ns fall@5.000ns period=10.000ns})
      Destination:            i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_clkgen/i_mmcm_rst_reg/rst_async_d1_reg/PRE
                                (removal check against rising-edge clock clk_fpga_0  {rise@0.000ns fall@5.000ns period=10.000ns})
      Path Group:             **async_default**
      Path Type:              Removal (Min at Fast Process Corner)
      Requirement:            0.000ns  (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
      Data Path Delay:        0.217ns  (logic 0.104ns (48.021%)  route 0.113ns (51.979%))
      Logic Levels:           0  
      Clock Path Skew:        0.145ns (DCD - SCD - CPR)
        Destination Clock Delay (DCD):    0.468ns
        Source Clock Delay      (SCD):    0.308ns
        Clock Pessimism Removal (CPR):    0.015ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock clk_fpga_0 rise edge)
                                                          0.000     0.000 r  
        PS7_X0Y0             PS7                          0.000     0.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
                             net (fo=1, unplaced)         0.208     0.208    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
                             BUFG (Prop_bufg_I_O)         0.026     0.234 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
                             net (fo=21577, unplaced)     0.074     0.308    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_clkgen/s_axi_aclk
                             FDPE                                         r  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_clkgen/up_mmcm_preset_reg/C
      -------------------------------------------------------------------    -------------------
                             FDPE (Prop_fdpe_C_Q)         0.104     0.412 f  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_clkgen/up_mmcm_preset_reg/Q
                             net (fo=3, unplaced)         0.113     0.525    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_clkgen/i_mmcm_rst_reg/up_mmcm_preset
                             FDPE                                         f  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_clkgen/i_mmcm_rst_reg/rst_async_d1_reg/PRE
      -------------------------------------------------------------------    -------------------
    
                             (clock clk_fpga_0 rise edge)
                                                          0.000     0.000 r  
        PS7_X0Y0             PS7                          0.000     0.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]
                             net (fo=1, unplaced)         0.219     0.219    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[0]
                             BUFG (Prop_bufg_I_O)         0.030     0.249 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
                             net (fo=21577, unplaced)     0.219     0.468    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_clkgen/i_mmcm_rst_reg/s_axi_aclk
                             FDPE                                         r  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_clkgen/i_mmcm_rst_reg/rst_async_d1_reg/C
                             clock pessimism             -0.015     0.453    
                             FDPE (Remov_fdpe_C_PRE)     -0.106     0.347    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_up_clkgen/i_mmcm_rst_reg/rst_async_d1_reg
      -------------------------------------------------------------------
                             required time                         -0.347    
                             arrival time                           0.525    
      -------------------------------------------------------------------
                             slack                                  0.178    
    
    
    
    
    
    ---------------------------------------------------------------------------------------------------
    Path Group:  **async_default**
    From Clock:  dac_clk_in_s
      To Clock:  dac_clk_in_s
    
    Setup :            0  Failing Endpoints,  Worst Slack       99.008ns,  Total Violation        0.000ns
    Hold  :            0  Failing Endpoints,  Worst Slack        0.176ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             99.008ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C
                                (rising edge-triggered cell FDPE clocked by dac_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Destination:            i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE
                                (recovery check against rising-edge clock dac_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Path Group:             **async_default**
      Path Type:              Recovery (Max at Slow Process Corner)
      Requirement:            100.000ns  (dac_clk_in_s rise@100.000ns - dac_clk_in_s rise@0.000ns)
      Data Path Delay:        0.524ns  (logic 0.233ns (44.466%)  route 0.291ns (55.534%))
      Logic Levels:           0  
      Clock Path Skew:        -0.145ns (DCD - SCD + CPR)
        Destination Clock Delay (DCD):    5.950ns = ( 105.950 - 100.000 ) 
        Source Clock Delay      (SCD):    9.869ns
        Clock Pessimism Removal (CPR):    3.774ns
      Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
        Total System Jitter     (TSJ):    0.071ns
        Total Input Jitter      (TIJ):    0.000ns
        Discrete Jitter          (DJ):    0.000ns
        Phase Error              (PE):    0.000ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock dac_clk_in_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        M6                                                0.000     5.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.857     5.857 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.354     6.211    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.650     6.861 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.584     7.445    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.093     7.538 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.419     7.958    dac_clk_out_s
                             BUFR (Prop_bufr_I_O)         0.650     8.608 r  BUFR_inst/O
                             net (fo=1, unplaced)         0.584     9.192    dac_clk_in_s
                             BUFG (Prop_bufg_I_O)         0.093     9.285 r  BUFG_inst/O
                             net (fo=100264, unplaced)    0.584     9.869    i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
                             FDPE                                         r  i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C
      -------------------------------------------------------------------    -------------------
                             FDPE (Prop_fdpe_C_Q)         0.233    10.102 f  i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q
                             net (fo=50, unplaced)        0.291    10.393    i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/AS[0]
                             FDPE                                         f  i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE
      -------------------------------------------------------------------    -------------------
    
                             (clock dac_clk_in_s rise edge)
                                                        100.000   100.000 r  
                             clock source latency         2.000   102.000    
        M6                                                0.000   102.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000   102.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.756   102.756 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.209   102.965    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.614   103.579 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.439   104.018    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.083   104.101 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.274   104.375    dac_clk_out_s
                             BUFR (Prop_bufr_I_O)         0.614   104.989 r  BUFR_inst/O
                             net (fo=1, unplaced)         0.439   105.428    dac_clk_in_s
                             BUFG (Prop_bufg_I_O)         0.083   105.511 r  BUFG_inst/O
                             net (fo=100264, unplaced)    0.439   105.950    i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/rd_clk
                             FDPE                                         r  i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/C
                             clock pessimism              3.774   109.724    
                             clock uncertainty           -0.035   109.689    
                             FDPE (Recov_fdpe_C_PRE)     -0.288   109.401    i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg
      -------------------------------------------------------------------
                             required time                        109.401    
                             arrival time                         -10.393    
      -------------------------------------------------------------------
                             slack                                 99.008    
    
    
    
    
    
    Min Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             0.176ns  (arrival time - required time)
      Source:                 i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C
                                (rising edge-triggered cell FDPE clocked by dac_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Destination:            i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR
                                (removal check against rising-edge clock dac_clk_in_s  {rise@0.000ns fall@50.000ns period=100.000ns})
      Path Group:             **async_default**
      Path Type:              Removal (Min at Fast Process Corner)
      Requirement:            0.000ns  (dac_clk_in_s rise@0.000ns - dac_clk_in_s rise@0.000ns)
      Data Path Delay:        0.217ns  (logic 0.104ns (48.021%)  route 0.113ns (51.979%))
      Logic Levels:           0  
      Clock Path Skew:        0.145ns (DCD - SCD - CPR)
        Destination Clock Delay (DCD):    7.164ns
        Source Clock Delay      (SCD):    3.294ns
        Clock Pessimism Removal (CPR):    3.725ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock dac_clk_in_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         2.000     2.000    
        M6                                                0.000     2.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     2.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.341     2.341 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.040     2.381    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.223     2.604 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.114     2.718    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.026     2.744 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.074     2.817    dac_clk_out_s
                             BUFR (Prop_bufr_I_O)         0.223     3.040 r  BUFR_inst/O
                             net (fo=1, unplaced)         0.114     3.154    dac_clk_in_s
                             BUFG (Prop_bufg_I_O)         0.026     3.180 r  BUFG_inst/O
                             net (fo=100264, unplaced)    0.114     3.294    i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk
                             FDPE                                         r  i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C
      -------------------------------------------------------------------    -------------------
                             FDPE (Prop_fdpe_C_Q)         0.104     3.398 f  i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/Q
                             net (fo=3, unplaced)         0.113     3.511    i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst_rd_reg2
                             FDCE                                         f  i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR
      -------------------------------------------------------------------    -------------------
    
                             (clock dac_clk_in_s rise edge)
                                                          0.000     0.000 r  
                             clock source latency         5.000     5.000    
        M6                                                0.000     5.000 r  rx2_dclk_in_p (IN)
                             net (fo=0)                   0.000     5.000    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/rx2_dclk_in_p_dclk_in
        M6                   IBUFDS (Prop_ibufds_I_O)     0.421     5.421 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_in_ibuf/O
                             net (fo=2, unplaced)         0.185     5.606    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/clk_in_s
                             BUFR (Prop_bufr_I_O)         0.251     5.857 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O
                             net (fo=1, unplaced)         0.259     6.116    i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/adc_clk_div_s
                             BUFG (Prop_bufg_I_O)         0.030     6.146 r  i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/I_bufg/O
                             net (fo=9098, unplaced)      0.219     6.365    dac_clk_out_s
                             BUFR (Prop_bufr_I_O)         0.251     6.616 r  BUFR_inst/O
                             net (fo=1, unplaced)         0.259     6.875    dac_clk_in_s
                             BUFG (Prop_bufg_I_O)         0.030     6.905 r  BUFG_inst/O
                             net (fo=100264, unplaced)    0.259     7.164    i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
                             FDCE                                         r  i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/C
                             clock pessimism             -3.725     3.439    
                             FDCE (Remov_fdce_C_CLR)     -0.104     3.335    i_system_wrapper/system_i/Streamer_Top_0/U0/FIFO_Data_I/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]
      -------------------------------------------------------------------
                             required time                         -3.335    
                             arrival time                           3.511    
      -------------------------------------------------------------------
                             slack                                  0.176    
    
    
    
    
    
    ---------------------------------------------------------------------------------------------------
    Path Group:  **async_default**
    From Clock:  mmcm_clk_0_s
      To Clock:  mmcm_clk_0_s
    
    Setup :            0  Failing Endpoints,  Worst Slack        5.623ns,  Total Violation        0.000ns
    Hold  :            0  Failing Endpoints,  Worst Slack        0.227ns,  Total Violation        0.000ns
    ---------------------------------------------------------------------------------------------------
    
    
    Max Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             5.623ns  (required time - arrival time)
      Source:                 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/rst_reg/C
                                (rising edge-triggered cell FDRE clocked by mmcm_clk_0_s  {rise@0.000ns fall@3.367ns period=6.735ns})
      Destination:            i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_fs_ret_toggle_m1_reg/CLR
                                (recovery check against rising-edge clock mmcm_clk_0_s  {rise@0.000ns fall@3.367ns period=6.735ns})
      Path Group:             **async_default**
      Path Type:              Recovery (Max at Slow Process Corner)
      Requirement:            6.735ns  (mmcm_clk_0_s rise@6.735ns - mmcm_clk_0_s rise@0.000ns)
      Data Path Delay:        0.564ns  (logic 0.233ns (41.312%)  route 0.331ns (58.688%))
      Logic Levels:           0  
      Clock Path Skew:        -0.145ns (DCD - SCD + CPR)
        Destination Clock Delay (DCD):    0.920ns = ( 7.655 - 6.735 ) 
        Source Clock Delay      (SCD):    1.096ns
        Clock Pessimism Removal (CPR):    0.031ns
      Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
        Total System Jitter     (TSJ):    0.071ns
        Discrete Jitter          (DJ):    0.286ns
        Phase Error              (PE):    0.000ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock mmcm_clk_0_s rise edge)
                                                          0.000     0.000 r  
        PS7_X0Y0             PS7                          0.000     0.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
                             net (fo=1, unplaced)         0.419     0.419    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
                             BUFG (Prop_bufg_I_O)         0.093     0.512 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
                             net (fo=46, unplaced)        0.584     1.096    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
                             MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                         -1.096     0.000 r  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
                             net (fo=1, unplaced)         0.419     0.419    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
                             BUFG (Prop_bufg_I_O)         0.093     0.512 r  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
                             net (fo=758, unplaced)       0.584     1.096    i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/hdmi_clk
                             FDRE                                         r  i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/rst_reg/C
      -------------------------------------------------------------------    -------------------
                             FDRE (Prop_fdre_C_Q)         0.233     1.329 f  i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/rst_reg/Q
                             net (fo=243, unplaced)       0.331     1.660    i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_rst
                             FDCE                                         f  i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_fs_ret_toggle_m1_reg/CLR
      -------------------------------------------------------------------    -------------------
    
                             (clock mmcm_clk_0_s rise edge)
                                                          6.735     6.735 r  
        PS7_X0Y0             PS7                          0.000     6.735 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
                             net (fo=1, unplaced)         0.398     7.133    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
                             BUFG (Prop_bufg_I_O)         0.083     7.216 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
                             net (fo=46, unplaced)        0.439     7.655    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
                             MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                         -0.920     6.735 r  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
                             net (fo=1, unplaced)         0.398     7.133    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
                             BUFG (Prop_bufg_I_O)         0.083     7.216 r  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
                             net (fo=758, unplaced)       0.439     7.655    i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_clk
                             FDCE                                         r  i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_fs_ret_toggle_m1_reg/C
                             clock pessimism              0.031     7.686    
                             clock uncertainty           -0.147     7.539    
                             FDCE (Recov_fdce_C_CLR)     -0.255     7.284    i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_fs_ret_toggle_m1_reg
      -------------------------------------------------------------------
                             required time                          7.284    
                             arrival time                          -1.660    
      -------------------------------------------------------------------
                             slack                                  5.623    
    
    
    
    
    
    Min Delay Paths
    --------------------------------------------------------------------------------------
    Slack (MET) :             0.227ns  (arrival time - required time)
      Source:                 i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/rst_reg/C
                                (rising edge-triggered cell FDRE clocked by mmcm_clk_0_s  {rise@0.000ns fall@3.367ns period=6.735ns})
      Destination:            i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_fs_ret_toggle_m1_reg/CLR
                                (removal check against rising-edge clock mmcm_clk_0_s  {rise@0.000ns fall@3.367ns period=6.735ns})
      Path Group:             **async_default**
      Path Type:              Removal (Min at Fast Process Corner)
      Requirement:            0.000ns  (mmcm_clk_0_s rise@0.000ns - mmcm_clk_0_s rise@0.000ns)
      Data Path Delay:        0.268ns  (logic 0.104ns (38.785%)  route 0.164ns (61.215%))
      Logic Levels:           0  
      Clock Path Skew:        0.145ns (DCD - SCD - CPR)
        Destination Clock Delay (DCD):    0.508ns
        Source Clock Delay      (SCD):    0.348ns
        Clock Pessimism Removal (CPR):    0.015ns
    
        Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
      -------------------------------------------------------------------    -------------------
                             (clock mmcm_clk_0_s rise edge)
                                                          0.000     0.000 r  
        PS7_X0Y0             PS7                          0.000     0.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
                             net (fo=1, unplaced)         0.208     0.208    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
                             BUFG (Prop_bufg_I_O)         0.026     0.234 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
                             net (fo=46, unplaced)        0.114     0.348    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
                             MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                         -0.348     0.000 r  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
                             net (fo=1, unplaced)         0.208     0.208    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
                             BUFG (Prop_bufg_I_O)         0.026     0.234 r  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
                             net (fo=758, unplaced)       0.114     0.348    i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/hdmi_clk
                             FDRE                                         r  i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/rst_reg/C
      -------------------------------------------------------------------    -------------------
                             FDRE (Prop_fdre_C_Q)         0.104     0.452 f  i_system_wrapper/system_i/axi_hdmi_core/inst/i_up/i_core_rst_reg/rst_reg/Q
                             net (fo=243, unplaced)       0.164     0.616    i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_rst
                             FDCE                                         f  i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_fs_ret_toggle_m1_reg/CLR
      -------------------------------------------------------------------    -------------------
    
                             (clock mmcm_clk_0_s rise edge)
                                                          0.000     0.000 r  
        PS7_X0Y0             PS7                          0.000     0.000 r  i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]
                             net (fo=1, unplaced)         0.219     0.219    i_system_wrapper/system_i/sys_ps7/inst/FCLK_CLK_unbuffered[1]
                             BUFG (Prop_bufg_I_O)         0.030     0.249 r  i_system_wrapper/system_i/sys_ps7/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O
                             net (fo=46, unplaced)        0.259     0.508    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/clk
                             MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                         -0.508     0.000 r  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0
                             net (fo=1, unplaced)         0.219     0.219    i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s
                             BUFG (Prop_bufg_I_O)         0.030     0.249 r  i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_clk_0_bufg/O
                             net (fo=758, unplaced)       0.259     0.508    i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_clk
                             FDCE                                         r  i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_fs_ret_toggle_m1_reg/C
                             clock pessimism             -0.015     0.493    
                             FDCE (Remov_fdce_C_CLR)     -0.104     0.389    i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_fs_ret_toggle_m1_reg
      -------------------------------------------------------------------
                             required time                         -0.389    
                             arrival time                           0.616    
      -------------------------------------------------------------------
                             slack                                  0.227    
    
    
    
    
    
    report_timing_summary: Time (s): cpu = 00:00:17 ; elapsed = 00:00:12 . Memory (MB): peak = 8679.270 ; gain = 0.000