Code source for AD9250-250EBZ KC705

Hi,
I'm John from Jicamarca Radio Observatory, we are trying to communicate the AD9250-250EBZ with the KC705 through FMC HPC interface, we have managed to build the project form the  repository https://wiki.analog.com/resources/fpga/xilinx/fmc/ad-fmcjesdadc1-ebz, but since the compiled project is used for another evaluation board for the AD9250 (that include a CPLD). We would like to know if you have information on source code to test the evaluation board for the AD9250 shown in the photos (this is more simple, without CPLD).
Waiting for your support, Regards.  
  • Hi John,

    we don't have source code for the AD9250-250EBZ-FMC but you can start from the fmcjesdadc1-ebz project and modify it to your needs. 

    In the block design script reduce the number of lanes and converters to 2 each.  You need to set the number of lanes in multiple places unless you apply this patch.

    Based on the FMC connector pinout form the schematic  adapt the constraint and system_top.v file:

    Thank you,

    Laszlo

  • Thank you very much for your response,

    I wanted to tell you that after some adjustments on the FPGA side and the AD9250 board, the reception of samples was finally achieved. I had a query, in the output of the axi_ad9250_core block when reviewing the 32-bit data of each channel (adc_data_a, adc_data_b), I had seen that each data (32 bits) contains two samples of each channel (data_a_high and data_data_a_low for adc_data_a, data_b_high and data_data_b_low for adc_data_b), I had the doubt if it is ok and if they are interleaved samples (t and t + 1). The frequency I am using on the ADC is 200MHz and the ILA block clock frequency is 100MHz.

    Waiting for your support, Regards

  • Hello,

    yes, there are two samples per beat per channel with the following mapping:

     (t)  adc_data_a/b [15:0]

    (t+1) adc_data_a/b [31:16]

    Laszlo