ADRV9002 ZCU102 FPGA reference design support for MIMO and independent


I am evaluating an ADRV9002 NP/W1 B0 silicon evaluation board on a ZCU102 carrier.

I have checked out the hdl_2019_r2 branch and used the ADI make to generate the corresponding Vivado project. The project builds OK.

The ADRV9002 Linux device driver supports operating in two modes:

1) MIMO mode where RX1/RX2 are at the same sample rate and a single DMA component is used to capture synchronous samples from both at the same time.

2) Independent mode where RX1/RX2 operate at different sample rates and there are two separate DMA components to handle the two channels.

I opened the ADI project in Vivado. Based on the HDL block design, it looks like the HDL firmware supports both modes. Is that correct? Or are there separate HDL projects for the two different modes (MIMO vs independent)?

Lastly, if the HDL project does support both modes, is it only the Linux driver device tree compatible setting (adi,adrv9002 vs adi,adrv9002-rxtx2) that determines which mode it operates in? Is there anything else I need to change?

Thank you.