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problem with build the HDL Reference Design

Hello,

I use adrv9361z7035+fmc.
The version for Linux image is hdl_2019_r2 and the version for vivado license is 2019.

For this version I have  Vivado ML Enterprise Edition, Node locked license.

I make the following steps for buil the HDL Reference Design

nicole@nicole-None:~$ export PATH=$PATH:/tools/Xilinx/SDK/2019.1/bin
nicole@nicole-None:~$ export PATH=$PATH:/tools/Xilinx/Vivado/2019.1/bin
nicole@nicole-None:~$ mkdir adi
nicole@nicole-None:~$ cd adi
nicole@nicole-None:~/adi$ git clone github.com/.../hdl.git
Cloning into 'hdl'...
remote: Enumerating objects: 62201, done.
remote: Counting objects: 100% (2975/2975), done.
remote: Compressing objects: 100% (1270/1270), done.
remote: Total 62201 (delta 1894), reused 2527 (delta 1693), pack-reused 59226
Receiving objects: 100% (62201/62201), 16.78 MiB | 2.22 MiB/s, done.
Resolving deltas: 100% (44324/44324), done.
nicole@nicole-None:~/adi$ cd hdl
nicole@nicole-None:~/adi/hdl$ git status
On branch master
Your branch is up to date with 'origin/master'.

nothing to commit, working tree clean
nicole@nicole-None:~/adi/hdl$ git checkout hdl_2019_r2
Branch 'hdl_2019_r2' set up to track remote branch 'hdl_2019_r2' from 'origin'.
Switched to a new branch 'hdl_2019_r2'

icole@nicole-None:~/adi/hdl$ git checkout hdl_2019_r2
Already on 'hdl_2019_r2'
Your branch is up to date with 'origin/hdl_2019_r2'.
nicole@nicole-None:~/adi/hdl$ git status
On branch hdl_2019_r2
Your branch is up to date with 'origin/hdl_2019_r2'.

nothing to commit, working tree clean
nicole@nicole-None:~/adi/hdl$ git fetch
nicole@nicole-None:~/adi/hdl$ git rebase origin/hdl_2019_r2
Current branch hdl_2019_r2 is up to date.

nicole@nicole-None:~/adi/hdl$ make -C projects/adrv9361z7035/ccfmc_lvds

Building adrv9361z7035_ccfmc_lvds project [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds_vivado.log] ... FAILED
For details see /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds_vivado.log

make: *** [../../scripts/project-xilinx.mk:60: adrv9361z7035_ccfmc_lvds.sdk/system_top.hdf] Error 1
make: Leaving directory '/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds'

And in my .log file have this error

ERROR: [Common 17-69] Command failed: Run 'impl_1' failed. Unable to open

I need help please,

Nicole.

Parents
  • Hello Travis,

    This is my log file

    ****** Vivado v2019.1 (64-bit)
      **** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
      **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
        ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
    
    source system_project.tcl
    # source ../../scripts/adi_env.tcl
    ## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
    ## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
    ## if [info exists ::env(ADI_HDL_DIR)] {
    ##   set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
    ## }
    ## if [info exists ::env(ADI_GHDL_DIR)] {
    ##   set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
    ## }
    ## proc get_env_param {name default_value} {
    ##   if [info exists ::env($name)] {
    ##     puts "Getting from environment the parameter: $name=$::env($name) "
    ##     return $::env($name)
    ##   } else {
    ##     return $default_value
    ##   }
    ## }
    # source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
    ## if {![info exists REQUIRED_VIVADO_VERSION]} {
    ##   set REQUIRED_VIVADO_VERSION "2019.1"
    ## }
    ## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
    ##   set IGNORE_VERSION_CHECK 1
    ## } elseif {![info exists IGNORE_VERSION_CHECK]} {
    ##   set IGNORE_VERSION_CHECK 0
    ## }
    ## if {[info exists ::env(ADI_USE_OOC_SYNTHESIS)]} {
    ##   set ADI_USE_OOC_SYNTHESIS 1
    ## } elseif {![info exists ADI_USE_OOC_SYNTHESIS]} {
    ##   set ADI_USE_OOC_SYNTHESIS 0
    ## }
    ## set ADI_USE_INCR_COMP 1
    ## set ADI_POWER_OPTIMIZATION 0
    ## set p_board "not-applicable"
    ## set p_device "none"
    ## set sys_zynq 1
    ## set p_prcfg_init ""
    ## set p_prcfg_list ""
    ## set p_prcfg_status ""
    ## proc adi_project {project_name {mode 0} {parameter_list {}} } {
    ## 
    ##   global ad_hdl_dir
    ##   global ad_ghdl_dir
    ##   global p_board
    ##   global p_device
    ##   global sys_zynq
    ##   global REQUIRED_VIVADO_VERSION
    ##   global IGNORE_VERSION_CHECK
    ##   global ADI_USE_OOC_SYNTHESIS
    ##   global ADI_USE_INCR_COMP
    ## 
    ##   if [regexp "_ac701$" $project_name] {
    ##     set p_device "xc7a200tfbg676-2"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *ac701*] end]
    ##     set sys_zynq 0
    ##   }
    ##   if [regexp "_kc705$" $project_name] {
    ##     set p_device "xc7k325tffg900-2"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *kc705*] end]
    ##     set sys_zynq 0
    ##   }
    ##   if [regexp "_vc707$" $project_name] {
    ##     set p_device "xc7vx485tffg1761-2"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *vc707*] end]
    ##     set sys_zynq 0
    ##   }
    ##   if [regexp "_vcu118$" $project_name] {
    ##     set p_device "xcvu9p-flga2104-2L-e"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *vcu118*] end]
    ##     set sys_zynq 0
    ##   }
    ##   if [regexp "_kcu105$" $project_name] {
    ##     set p_device "xcku040-ffva1156-2-e"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *kcu105*] end]
    ##     set sys_zynq 0
    ##   }
    ##   if [regexp "_zed$" $project_name] {
    ##     set p_device "xc7z020clg484-1"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *zed*] end]
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_coraz7s$" $project_name] {
    ##     set p_device "xc7z007sclg400-1"
    ##     set p_board "not-applicable"
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_microzed$" $project_name] {
    ##     set p_device "xc7z010clg400-1"
    ##     set p_board "not-applicable"
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_zc702$" $project_name] {
    ##     set p_device "xc7z020clg484-1"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *zc702*] end]
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_zc706$" $project_name] {
    ##     set p_device "xc7z045ffg900-2"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *zc706*] end]
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_mitx045$" $project_name] {
    ##     set p_device "xc7z045ffg900-2"
    ##     set p_board "not-applicable"
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_zcu102$" $project_name] {
    ##     set p_device "xczu9eg-ffvb1156-2-e"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *zcu102*] end]
    ##     set sys_zynq 2
    ##   }
    ## 
    ##   set VIVADO_VERSION [version -short]
    ##   if {$IGNORE_VERSION_CHECK} {
    ##     if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
    ##       puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
    ##       puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
    ##       puts -nonewline "got $VIVADO_VERSION.\n"
    ##     }
    ##   } else {
    ##     if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
    ##       puts -nonewline "ERROR: vivado version mismatch; "
    ##       puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
    ##       puts -nonewline "got $VIVADO_VERSION.\n"
    ##       puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
    ##       exit 2
    ##     }
    ##   }
    ## 
    ##   if {$mode == 0} {
    ##     set project_system_dir "./$project_name.srcs/sources_1/bd/system"
    ##     create_project $project_name . -part $p_device -force
    ##   } else {
    ##     set project_system_dir ".srcs/sources_1/bd/system"
    ##     create_project -in_memory -part $p_device
    ##   }
    ## 
    ##   if {$mode == 1} {
    ##     file mkdir $project_name.data
    ##   }
    ## 
    ##   if {$p_board ne "not-applicable"} {
    ##     set_property board_part $p_board [current_project]
    ##   }
    ## 
    ##   set lib_dirs $ad_hdl_dir/library
    ##   if {$ad_hdl_dir ne $ad_ghdl_dir} {
    ##     lappend lib_dirs $ad_ghdl_dir/library
    ##   }
    ## 
    ##   # Set a common IP cache for all projects
    ##   if {$ADI_USE_OOC_SYNTHESIS == 1} {
    ##     if {[file exists $ad_hdl_dir/ipcache] == 0} {
    ##       file mkdir $ad_hdl_dir/ipcache
    ##     }
    ##     config_ip_cache -import_from_project -use_cache_location $ad_hdl_dir/ipcache
    ##   }
    ## 
    ##   set_property ip_repo_paths $lib_dirs [current_fileset]
    ##   update_ip_catalog
    ## 
    ##   ## Load custom message severity definitions
    ##   source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
    ## 
    ##   ## In Vivado there is a limit for the number of warnings and errors which are
    ##   ## displayed by the tool for a particular error or warning; the default value
    ##   ## of this limit is 100.
    ##   ## Overrides the default limit to 2000.
    ##   set_param messaging.defaultLimit 2000
    ## 
    ##   # Set parameters of the top level file
    ##   # Make the same parameters available to system_bd.tcl
    ##   set proj_params [get_property generic [current_fileset]]
    ##   foreach {param value} $parameter_list {
    ##     lappend proj_params $param=$value
    ##     set ad_project_params($param) $value
    ##   }
    ##   set_property generic $proj_params [current_fileset]
    ## 
    ##   create_bd_design "system"
    ##   source system_bd.tcl
    ## 
    ##   save_bd_design
    ##   validate_bd_design
    ## 
    ##   if {$ADI_USE_OOC_SYNTHESIS == 1} {
    ##     set_property synth_checkpoint_mode Hierarchical [get_files  $project_system_dir/system.bd]
    ##   } else {
    ##     set_property synth_checkpoint_mode None [get_files  $project_system_dir/system.bd]
    ##   }
    ##   generate_target {synthesis implementation} [get_files  $project_system_dir/system.bd]
    ##   if {$ADI_USE_OOC_SYNTHESIS == 1} {
    ##     export_ip_user_files -of_objects [get_files  $project_system_dir/system.bd] -no_script -sync -force -quiet
    ##     create_ip_run [get_files  $project_system_dir/system.bd]
    ##   }
    ##   make_wrapper -files [get_files $project_system_dir/system.bd] -top
    ## 
    ##   if {$mode == 0} {
    ##     import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v
    ##   } else {
    ##     write_hwdef -file "$project_name.data/$project_name.hwdef"
    ##   }
    ## 
    ##   if {$ADI_USE_INCR_COMP == 1} {
    ##     if {[file exists ./reference.dcp]} {
    ##       set_property incremental_checkpoint ./reference.dcp [get_runs impl_1]
    ##     }
    ##   }
    ## 
    ## }
    ## proc adi_project_files {project_name project_files} {
    ## 
    ##   foreach pfile $project_files {
    ##     if {[string range $pfile [expr 1 + [string last . $pfile]] end] == "xdc"} {
    ##       add_files -norecurse -fileset constrs_1 $pfile
    ##     } else {
    ##       add_files -norecurse -fileset sources_1 $pfile
    ##     }
    ##   }
    ## 
    ##   # NOTE: top file name is always system_top
    ##   set_property top system_top [current_fileset]
    ## }
    ## proc adi_project_run {project_name} {
    ## 
    ##   global ADI_POWER_OPTIMIZATION
    ##   global ADI_USE_OOC_SYNTHESIS
    ## 
    ##   if {$ADI_USE_OOC_SYNTHESIS == 1} {
    ##     launch_runs -jobs 4 system_*_synth_1 synth_1
    ##   } else {
    ##     launch_runs synth_1
    ##   }
    ##   wait_on_run synth_1
    ##   open_run synth_1
    ##   report_timing_summary -file timing_synth.log
    ## 
    ##   if {![info exists ::env(ADI_NO_BITSTREAM_COMPRESSION)] && ![info exists ADI_NO_BITSTREAM_COMPRESSION]} {
    ##     set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
    ##   }
    ## 
    ##   if {$ADI_POWER_OPTIMIZATION == 1} {
    ##   set_property STEPS.POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
    ##   set_property STEPS.POST_PLACE_POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
    ##   }
    ## 
    ##   launch_runs impl_1 -to_step write_bitstream
    ##   wait_on_run impl_1
    ##   open_run impl_1
    ##   report_timing_summary -warn_on_violation -file timing_impl.log
    ## 
    ##   if {[info exists ::env(ADI_GENERATE_UTILIZATION)]} {
    ##     set csv_file resource_utilization.csv
    ##     if {[ catch {
    ##       xilinx::designutils::report_failfast -csv -file $csv_file -transpose -no_header -ignore_pr -quiet
    ##       set MMCM [llength [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ *MMCM* }]]
    ##       set PLL [llength [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ *PLL* }]]
    ##       set worst_slack_setup [get_property SLACK [get_timing_paths -setup]]
    ##       set worst_slack_hold [get_property SLACK [get_timing_paths -hold]]
    ## 
    ##       set fileRead [open $csv_file r]
    ##       set lines [split [read $fileRead] "\n"]
    ##       set names_line [lindex $lines end-3]
    ##       set values_line [lindex $lines end-2]
    ##       close $fileRead
    ## 
    ##       set fileWrite [open $csv_file w]
    ##       puts $fileWrite "$names_line,MMCM*,PLL*,Worst_Setup_Slack,Worst_Hold_Slack"
    ##       puts $fileWrite "$values_line,$MMCM,$PLL,$worst_slack_setup,$worst_slack_hold"
    ##       close $fileWrite
    ##       } issue ] != 0 } {
    ##         puts "GENERATE_REPORTS: tclapp::xilinx::designutils not installed"
    ##       }
    ## 
    ##       # Define a list of IPs for which to generate report utilization
    ##       set IP_list {
    ##         ad_ip_jesd_204_tpl_adc
    ##         ad_ip_jesd_204_tpl_dac
    ##         axi_jesd204_rx
    ##         axi_jesd204_tx
    ##         jesd204_rx
    ##         jesd204_tx
    ##         axi_adxcvr
    ##         util_adxcvr
    ##         axi_dmac
    ##         util_cpack2
    ##         util_upack2
    ##       }
    ## 
    ##       foreach IP_name $IP_list {
    ## 	set output_file ${IP_name}_resource_utilization.log
    ##         file delete $output_file
    ##         foreach IP_instance [ get_cells -quiet -hierarchical -filter " ORIG_REF_NAME =~ $IP_name || REF_NAME =~ $IP_name " ] {
    ##           report_utilization -hierarchical -hierarchical_depth 1 -cells $IP_instance -file $output_file -append -quiet
    ##           report_property $IP_instance -file $output_file -append -quiet
    ##           set report_file [ open $output_file a ]
    ##           puts $report_file "\n\n\n"
    ##           close $report_file
    ##         }
    ##       }
    ##     } else {
    ##     puts "GENERATE_REPORTS: Resource utilization files won't be generated because ADI_GENERATE_UTILIZATION env var is not set"
    ##   }
    ## 
    ##   if {[info exists ::env(ADI_GENERATE_XPA)]} {
    ##     set csv_file power_analysis.csv
    ##     set Layers "8to11"
    ##     set CapLoad "20"
    ##     set ToggleRate "15.00000"
    ##     set StatProb "0.500000"
    ## 
    ##     set_load $CapLoad [all_outputs]
    ##     set_operating_conditions -board_layers $Layers
    ##     set_switching_activity -default_toggle_rate $ToggleRate
    ##     set_switching_activity -default_static_probability $StatProb
    ##     set_switching_activity -type lut -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type register -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type shift_register -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type lut_ram -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type bram -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type dsp -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type gt_rxdata -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type gt_txdata -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type io_output -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type bram_enable -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type bram_wr_enable -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type io_bidir_enable -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     report_power -file $csv_file
    ## 
    ##     set fileRead [open $csv_file r]
    ##     set filecontent [read $fileRead]
    ##     set input_list [split $filecontent "\n"]
    ## 
    ##     set TextList [lsearch -all -inline $input_list "*Total On-Chip Power (W)*"]
    ##     set on_chip_pwr "[lindex [lindex $TextList 0] 6] W"
    ##     set TextList [lsearch -all -inline $input_list "*Junction Temperature (C)*"]
    ##     set junction_temp "[lindex [lindex $TextList 0] 5] *C"
    ##     close $fileRead
    ## 
    ##     set fileWrite [open $csv_file w]
    ##     puts $fileWrite "On-chip_power,Junction_temp"
    ##     puts $fileWrite "$on_chip_pwr,$junction_temp"
    ##     close $fileWrite
    ##   } else {
    ##     puts "GENERATE_REPORTS: Power analysis files won't be generated because ADI_GENERATE_XPA env var is not set"
    ##   }
    ## 
    ##   # Look for undefined clocks which do not show up in the timing summary
    ##   set timing_check [check_timing -override_defaults no_clock -no_header -return_string]
    ##   if {[regexp { (\d+) register} $timing_check -> num_regs]} {
    ## 
    ##     if {[info exist num_regs]} {
    ##       if {$num_regs > 0} {
    ##         puts "CRITICAL WARNING: There are $num_regs registers with no clocks !!! See no_clock.log for details."
    ##         check_timing -override_defaults no_clock -verbose -file no_clock.log
    ##       }
    ##     }
    ## 
    ##   } else {
    ##     puts "CRITICAL WARNING: The search for undefined clocks failed !!!"
    ##   }
    ## 
    ##   file mkdir $project_name.sdk
    ## 
    ##   set timing_string $[report_timing_summary -return_string]
    ##   if { [string match "*VIOLATED*" $timing_string] == 1 ||
    ##        [string match "*Timing constraints are not met*" $timing_string] == 1} {
    ##     file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top_bad_timing.hdf
    ##     return -code error [format "ERROR: Timing Constraints NOT met!"]
    ##   } else {
    ##     file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top.hdf
    ##   }
    ## }
    ## proc adi_project_synth {project_name prcfg_name hdl_files {xdc_files ""}} {
    ## 
    ##   global p_device
    ## 
    ##   set p_prefix "$project_name.data/$project_name"
    ## 
    ##   if {$prcfg_name eq ""} {
    ## 
    ##     read_verilog .srcs/sources_1/bd/system/hdl/system_wrapper.v
    ##     read_verilog $hdl_files
    ##     read_xdc $xdc_files
    ## 
    ##     synth_design -mode default -top system_top -part $p_device > $p_prefix.synth.rds
    ##     write_checkpoint -force $p_prefix.synth.dcp
    ##     close_project
    ## 
    ##   } else {
    ## 
    ##     create_project -in_memory -part $p_device
    ##     read_verilog $hdl_files
    ##     synth_design -mode out_of_context -top "prcfg" -part $p_device > $p_prefix.${prcfg_name}_synth.rds
    ##     write_checkpoint -force $p_prefix.${prcfg_name}_synth.dcp
    ##     close_project
    ##   }
    ## }
    ## proc adi_project_impl {project_name prcfg_name {xdc_files ""}} {
    ## 
    ##   global p_device
    ##   global p_prcfg_init
    ##   global p_prcfg_list
    ##   global p_prcfg_status
    ## 
    ##   set p_prefix "$project_name.data/$project_name"
    ## 
    ##   if {$prcfg_name eq "default"} {
    ##     set p_prcfg_status 0
    ##     set p_prcfg_list ""
    ##     set p_prcfg_init "$p_prefix.${prcfg_name}_impl.dcp"
    ##     file mkdir $project_name.sdk
    ##   }
    ## 
    ##   if {$prcfg_name eq "default"} {
    ## 
    ##     open_checkpoint $p_prefix.synth.dcp -part $p_device
    ##     read_xdc $xdc_files
    ##     read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp
    ##     set_property HD.RECONFIGURABLE 1 [get_cells i_prcfg]
    ##     opt_design > $p_prefix.${prcfg_name}_opt.rds
    ##     write_debug_probes -force $p_prefix.${prcfg_name}_debug_nets.ltx
    ##     place_design > $p_prefix.${prcfg_name}_place.rds
    ##     route_design > $p_prefix.${prcfg_name}_route.rds
    ## 
    ##   } else {
    ## 
    ##     open_checkpoint $p_prefix.default_impl_bb.dcp -part $p_device
    ##     lock_design -level routing
    ##     read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp
    ##     read_xdc $xdc_files
    ##     opt_design > $p_prefix.${prcfg_name}_opt.rds
    ##     place_design > $p_prefix.${prcfg_name}_place.rds
    ##     route_design > $p_prefix.${prcfg_name}_route.rds
    ##   }
    ## 
    ##   write_checkpoint -force $p_prefix.${prcfg_name}_impl.dcp
    ##   report_utilization -pblocks pb_prcfg -file $p_prefix.${prcfg_name}_utilization.rpt
    ##   report_timing_summary -file $p_prefix.${prcfg_name}_timing_summary.rpt
    ## 
    ##   if [expr [get_property SLACK [get_timing_paths]] < 0] {
    ##     set p_prcfg_status 1
    ##     puts "CRITICAL WARNING: Timing Constraints NOT met ($prcfg_name)!"
    ##   }
    ## 
    ##   write_checkpoint -force -cell i_prcfg $p_prefix.${prcfg_name}_prcfg_impl.dcp
    ##   update_design -cell i_prcfg -black_box
    ##   write_checkpoint -force $p_prefix.${prcfg_name}_impl_bb.dcp
    ##   open_checkpoint $p_prefix.${prcfg_name}_impl.dcp -part $p_device
    ##   write_bitstream -force -bin_file -file $p_prefix.${prcfg_name}.bit
    ##   write_sysdef -hwdef $p_prefix.hwdef -bitfile $p_prefix.${prcfg_name}.bit -file $p_prefix.${prcfg_name}.hdf
    ##   file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.${prcfg_name}.hdf
    ## 
    ##   if {$prcfg_name ne "default"} {
    ##     lappend p_prcfg_list "$p_prefix.${prcfg_name}_impl.dcp"
    ##   }
    ## 
    ##   if {$prcfg_name eq "default"} {
    ##     file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.hdf
    ##   }
    ## }
    ## proc adi_project_verify {project_name} {
    ## 
    ##   # checkpoint for the default design
    ##   global p_prcfg_init
    ##   # list of checkpoints with all the PRs integrated into the default design
    ##   global p_prcfg_list
    ##   global p_prcfg_status
    ## 
    ##   set p_prefix "$project_name.data/$project_name"
    ## 
    ##   pr_verify -full_check -initial $p_prcfg_init \
    ##     -additional $p_prcfg_list \
    ##     -file $p_prefix.prcfg_verify.log
    ## 
    ##   if {$p_prcfg_status == 1} {
    ##     return -code error [format "ERROR: Timing Constraints NOT met!"]
    ##   }
    ## }
    # source $ad_hdl_dir/projects/scripts/adi_board.tcl
    ## set sys_cpu_interconnect_index 0
    ## set sys_hp0_interconnect_index -1
    ## set sys_hp1_interconnect_index -1
    ## set sys_hp2_interconnect_index -1
    ## set sys_hp3_interconnect_index -1
    ## set sys_mem_interconnect_index -1
    ## set sys_mem_clk_index 0
    ## set xcvr_index -1
    ## set xcvr_tx_index 0
    ## set xcvr_rx_index 0
    ## set xcvr_instance NONE
    ## proc ad_ip_instance {i_ip i_name {i_params {}}} {
    ## 
    ##   set cell [create_bd_cell -type ip -vlnv [get_ipdefs -all -filter "VLNV =~ *:${i_ip}:* && \
    ##     design_tool_contexts =~ *IPI* && UPGRADE_VERSIONS == \"\""] ${i_name}]
    ##   if {$i_params != {}} {
    ##     set config {}
    ##     # Add CONFIG. prefix to all config options
    ##     foreach {k v} $i_params {
    ##       lappend config "CONFIG.$k" $v
    ##     }
    ##     set_property -dict $config $cell
    ##   }
    ## }
    ## proc ad_ip_parameter {i_name i_param i_value} {
    ## 
    ##   set_property ${i_param} ${i_value} [get_bd_cells ${i_name}]
    ## }
    ## proc ad_connect_type {p_name} {
    ## 
    ##   set m_name ""
    ## 
    ##   if {$m_name eq ""} {set m_name [get_bd_intf_pins  -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_pins       -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_intf_ports -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_ports      -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_intf_nets  -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_nets       -quiet $p_name]}
    ## 
    ##   return $m_name
    ## }
    ## proc ad_connect {p_name_1 p_name_2} {
    ## 
    ##   ## connect an IPI object to GND or VCC
    ##   ## instantiate xlconstant with the required width module if there isn't any
    ##   ## already
    ##   if {($p_name_2 eq "GND") || ($p_name_2 eq "VCC")} {
    ##     set p_size 1
    ##     set p_msb [get_property left [get_bd_pins $p_name_1]]
    ##     set p_lsb [get_property right [get_bd_pins $p_name_1]]
    ##     if {($p_msb ne "") && ($p_lsb ne "")} {
    ##       set p_size [expr (($p_msb + 1) - $p_lsb)]
    ##     }
    ##     set p_cell_name "$p_name_2\_$p_size"
    ##     if {[get_bd_cells -quiet $p_cell_name] eq ""} {
    ##       if {$p_name_2 eq "VCC"} {
    ##         set p_value [expr (1 << $p_size) - 1]
    ##       } else {
    ##         set p_value 0
    ##       }
    ##       ad_ip_instance xlconstant $p_cell_name
    ##       set_property CONFIG.CONST_WIDTH $p_size [get_bd_cells $p_cell_name]
    ##       set_property CONFIG.CONST_VAL $p_value [get_bd_cells $p_cell_name]
    ##     }
    ##     puts "connect_bd_net $p_cell_name/dout $p_name_1"
    ##     connect_bd_net [get_bd_pins $p_name_1] [get_bd_pins $p_cell_name/dout]
    ##     return
    ##   }
    ## 
    ##   set m_name_1 [ad_connect_type $p_name_1]
    ##   set m_name_2 [ad_connect_type $p_name_2]
    ## 
    ##   if {$m_name_1 eq ""} {
    ##     if {[get_property CLASS $m_name_2] eq "bd_intf_pin"} {
    ##       puts "create_bd_intf_net $p_name_1"
    ##       create_bd_intf_net $p_name_1
    ##     }
    ##     if {[get_property CLASS $m_name_2] eq "bd_pin"} {
    ##       puts "create_bd_net $p_name_1"
    ##       create_bd_net $p_name_1
    ##     }
    ##     set m_name_1 [ad_connect_type $p_name_1]
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_intf_pin"} {
    ##     puts "connect_bd_intf_net $m_name_1 $m_name_2"
    ##     connect_bd_intf_net $m_name_1 $m_name_2
    ##     return
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_pin"} {
    ##     puts "connect_bd_net $m_name_1 $m_name_2"
    ##     connect_bd_net $m_name_1 $m_name_2
    ##     return
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_net"} {
    ##     puts "connect_bd_net -net $m_name_1 $m_name_2"
    ##     connect_bd_net -net $m_name_1 $m_name_2
    ##     return
    ##   }
    ## }
    ## proc ad_disconnect {p_name_1 p_name_2} {
    ## 
    ##   set m_name_1 [ad_connect_type $p_name_1]
    ##   set m_name_2 [ad_connect_type $p_name_2]
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_net"} {
    ##     disconnect_bd_net $m_name_1 $m_name_2
    ##     return
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_port"} {
    ##     delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
    ##       [find_bd_objs -relation connected_to $m_name_1]]
    ##     delete_bd_objs -quiet $m_name_1
    ##     return
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_pin"} {
    ##     delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
    ##       [find_bd_objs -relation connected_to $m_name_1]]
    ##     delete_bd_objs -quiet $m_name_1
    ##     return
    ##   }
    ## }
    ## proc ad_xcvrcon {u_xcvr a_xcvr a_jesd {lane_map {}} {device_clk {}}} {
    ## 
    ##   global xcvr_index
    ##   global xcvr_tx_index
    ##   global xcvr_rx_index
    ##   global xcvr_instance
    ## 
    ##   set no_of_lanes [get_property CONFIG.NUM_OF_LANES [get_bd_cells $a_xcvr]]
    ##   set qpll_enable [get_property CONFIG.QPLL_ENABLE [get_bd_cells $a_xcvr]]
    ##   set tx_or_rx_n [get_property CONFIG.TX_OR_RX_N [get_bd_cells $a_xcvr]]
    ## 
    ##   set jesd204_bd_type [get_property TYPE [get_bd_cells $a_jesd]]
    ## 
    ##   if {$jesd204_bd_type == "hier"} {
    ##     set jesd204_type 0
    ##   } else {
    ##     set jesd204_type 1
    ##   }
    ## 
    ##   if {$xcvr_instance ne $u_xcvr} {
    ##     set xcvr_index [expr ($xcvr_index + 1)]
    ##     set xcvr_tx_index 0
    ##     set xcvr_rx_index 0
    ##     set xcvr_instance $u_xcvr
    ##   }
    ## 
    ##   set txrx "rx"
    ##   set data_dir "I"
    ##   set ctrl_dir "O"
    ##   set index $xcvr_rx_index
    ## 
    ##   if {$tx_or_rx_n == 1} {
    ## 
    ##     set txrx "tx"
    ##     set data_dir "O"
    ##     set ctrl_dir "I"
    ##     set index $xcvr_tx_index
    ##   }
    ## 
    ##   set m_sysref ${txrx}_sysref_${index}
    ##   set m_sync ${txrx}_sync_${index}
    ##   set m_data ${txrx}_data
    ## 
    ##   if {$xcvr_index >= 1} {
    ## 
    ##     set m_sysref ${txrx}_sysref_${xcvr_index}_${index}
    ##     set m_sync ${txrx}_sync_${xcvr_index}_${index}
    ##     set m_data ${txrx}_data_${xcvr_index}
    ##   }
    ## 
    ##   if {$jesd204_type == 0} {
    ##     set num_of_links [get_property CONFIG.NUM_LINKS [get_bd_cells $a_jesd/$txrx]]
    ##   } else {
    ##     set num_of_links 1
    ##   }
    ## 
    ##   create_bd_port -dir I $m_sysref
    ##   create_bd_port -from [expr $num_of_links - 1] -to 0 -dir ${ctrl_dir} $m_sync
    ## 
    ##   if {$device_clk == {}} {
    ##     set device_clk ${u_xcvr}/${txrx}_out_clk_${index}
    ##     set rst_gen [regsub -all "/" ${a_jesd}_rstgen "_"]
    ##     set create_rst_gen 1
    ##   } else {
    ##     set rst_gen ${device_clk}_rstgen
    ##     # Only create one reset gen per clock
    ##     set create_rst_gen [expr {[get_bd_cells -quiet ${rst_gen}] == {}}]
    ##   }
    ## 
    ##   if {${create_rst_gen}} {
    ##     ad_ip_instance proc_sys_reset ${rst_gen}
    ##     ad_connect ${device_clk} ${rst_gen}/slowest_sync_clk
    ##     ad_connect sys_cpu_resetn ${rst_gen}/ext_reset_in
    ##   }
    ## 
    ##   for {set n 0} {$n < $no_of_lanes} {incr n} {
    ## 
    ##     set m [expr ($n + $index)]
    ## 
    ## 
    ##     if {$lane_map != {}} {
    ##       set phys_lane [lindex $lane_map $n]
    ##     } else {
    ##       set phys_lane $m
    ##     }
    ## 
    ##     if {$tx_or_rx_n == 0} {
    ##       ad_connect  ${a_xcvr}/up_es_${n} ${u_xcvr}/up_es_${phys_lane}
    ##       if {$jesd204_type == 0} {
    ##         ad_connect  ${a_jesd}/phy_en_char_align ${u_xcvr}/${txrx}_calign_${phys_lane}
    ##       } else {
    ##         ad_connect  ${a_jesd}/rxencommaalign_out ${u_xcvr}/${txrx}_calign_${phys_lane}
    ##       }
    ##     }
    ## 
    ##     if {(($n%4) == 0) && ($qpll_enable == 1)} {
    ##       ad_connect  ${a_xcvr}/up_cm_${n} ${u_xcvr}/up_cm_${n}
    ##     }
    ##     ad_connect  ${a_xcvr}/up_ch_${n} ${u_xcvr}/up_${txrx}_${phys_lane}
    ##     ad_connect  ${device_clk} ${u_xcvr}/${txrx}_clk_${phys_lane}
    ##     if {$phys_lane != {}} {
    ##       if {$jesd204_type == 0} {
    ##         ad_connect  ${u_xcvr}/${txrx}_${phys_lane} ${a_jesd}/${txrx}_phy${n}
    ##       } else {
    ##         ad_connect  ${u_xcvr}/${txrx}_${phys_lane} ${a_jesd}/gt${n}_${txrx}
    ##       }
    ##     }
    ## 
    ##     create_bd_port -dir ${data_dir} ${m_data}_${m}_p
    ##     create_bd_port -dir ${data_dir} ${m_data}_${m}_n
    ##     ad_connect  ${u_xcvr}/${txrx}_${m}_p ${m_data}_${m}_p
    ##     ad_connect  ${u_xcvr}/${txrx}_${m}_n ${m_data}_${m}_n
    ##   }
    ## 
    ##   if {$jesd204_type == 0} {
    ##     ad_connect  ${a_jesd}/sysref $m_sysref
    ##     ad_connect  ${a_jesd}/sync $m_sync
    ##     ad_connect  ${device_clk} ${a_jesd}/device_clk
    ##   } else {
    ##     ad_connect  ${a_jesd}/${txrx}_sysref $m_sysref
    ##     ad_connect  ${a_jesd}/${txrx}_sync $m_sync
    ##     ad_connect  ${device_clk} ${a_jesd}/${txrx}_core_clk
    ##     ad_connect  ${a_xcvr}/up_status ${a_jesd}/${txrx}_reset_done
    ##     ad_connect  ${rst_gen}/peripheral_reset ${a_jesd}/${txrx}_reset
    ##   }
    ## 
    ##   if {$tx_or_rx_n == 0} {
    ##     set xcvr_rx_index [expr ($xcvr_rx_index + $no_of_lanes)]
    ##   }
    ## 
    ##   if {$tx_or_rx_n == 1} {
    ##     set xcvr_tx_index [expr ($xcvr_tx_index + $no_of_lanes)]
    ##   }
    ## }
    ## proc ad_xcvrpll {m_src m_dst} {
    ## 
    ##   foreach p_dst [get_bd_pins -quiet $m_dst] {
    ##     connect_bd_net [ad_connect_type $m_src] $p_dst
    ##   }
    ## }
    ## proc ad_mem_hp0_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP0")} {return}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}
    ## }
    ## proc ad_mem_hp1_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP1")} {return}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name}
    ## }
    ## proc ad_mem_hp2_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP2")} {return}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name}
    ## }
    ## proc ad_mem_hp3_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP3")} {return}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name}
    ## }
    ## proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
    ## 
    ##   global sys_zynq
    ##   global sys_ddr_addr_seg
    ##   global sys_hp0_interconnect_index
    ##   global sys_hp1_interconnect_index
    ##   global sys_hp2_interconnect_index
    ##   global sys_hp3_interconnect_index
    ##   global sys_mem_interconnect_index
    ##   global sys_mem_clk_index
    ## 
    ##   set p_name_int $p_name
    ##   set p_clk_source [get_bd_pins -filter {DIR == O} -of_objects [get_bd_nets $p_clk]]
    ## 
    ##   if {$p_sel eq "MEM"} {
    ##     if {$sys_mem_interconnect_index < 0} {
    ##       ad_ip_instance smartconnect axi_mem_interconnect
    ##     }
    ##     set m_interconnect_index $sys_mem_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_mem_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs -of_objects [get_bd_cells axi_ddr_cntrl]]
    ##   }
    ## 
    ##   if {($p_sel eq "HP0") && ($sys_zynq == 1)} {
    ##     if {$sys_hp0_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP0
    ##       set_property CONFIG.PCW_USE_S_AXI_HP0 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance smartconnect axi_hp0_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp0_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HP1") && ($sys_zynq == 1)} {
    ##     if {$sys_hp1_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP1
    ##       set_property CONFIG.PCW_USE_S_AXI_HP1 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance smartconnect axi_hp1_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp1_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HP2") && ($sys_zynq == 1)} {
    ##     if {$sys_hp2_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP2
    ##       set_property CONFIG.PCW_USE_S_AXI_HP2 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance smartconnect axi_hp2_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp2_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HP3") && ($sys_zynq == 1)} {
    ##     if {$sys_hp3_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP3
    ##       set_property CONFIG.PCW_USE_S_AXI_HP3 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance smartconnect axi_hp3_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp3_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HP0") && ($sys_zynq == 2)} {
    ##     if {$sys_hp0_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP0_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP2 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance smartconnect axi_hp0_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp0_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_*]
    ##   }
    ## 
    ##   if {($p_sel eq "HP1") && ($sys_zynq == 2)} {
    ##     if {$sys_hp1_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP1_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP3 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance smartconnect axi_hp1_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp1_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_*]
    ##   }
    ## 
    ##   if {($p_sel eq "HP2") && ($sys_zynq == 2)} {
    ##     if {$sys_hp2_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP2_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP4 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance smartconnect axi_hp2_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp2_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_*]
    ##   }
    ## 
    ##   if {($p_sel eq "HP3") && ($sys_zynq == 2)} {
    ##     if {$sys_hp3_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP3_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP5 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance smartconnect axi_hp3_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp3_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP5/HP3_DDR_*]
    ##   }
    ## 
    ##   set i_str "S$m_interconnect_index"
    ##   if {$m_interconnect_index < 10} {
    ##     set i_str "S0$m_interconnect_index"
    ##   }
    ## 
    ##   set m_interconnect_index [expr $m_interconnect_index + 1]
    ## 
    ##   set p_intf_name [lrange [split $p_name_int "/"] end end]
    ##   set p_cell_name [lrange [split $p_name_int "/"] 0 0]
    ##   set p_intf_clock [get_bd_pins -filter "TYPE == clk && (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
    ##     CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
    ##     CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" -quiet -of_objects [get_bd_cells $p_cell_name]]
    ##   if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne "" ||
    ##       $p_intf_clock eq $p_clk_source} {
    ##     set p_intf_clock ""
    ##   }
    ## 
    ##   regsub clk $p_clk resetn p_rst
    ##   if {[get_bd_nets -quiet $p_rst] eq ""} {
    ##     set p_rst sys_cpu_resetn
    ##   }
    ## 
    ##   if {$m_interconnect_index == 0} {
    ##     set_property CONFIG.NUM_MI 1 $m_interconnect_cell
    ##     set_property CONFIG.NUM_SI 1 $m_interconnect_cell
    ##     ad_connect $p_rst $m_interconnect_cell/ARESETN
    ##     ad_connect $p_clk $m_interconnect_cell/ACLK
    ##     ad_connect $m_interconnect_cell/M00_AXI $p_name_int
    ##     if {$p_intf_clock ne ""} {
    ##       ad_connect $p_clk $p_intf_clock
    ##     }
    ##   } else {
    ## 
    ##     set_property CONFIG.NUM_SI $m_interconnect_index $m_interconnect_cell
    ##     if {[lsearch [get_bd_nets -of_object [get_bd_pins $m_interconnect_cell/ACLK*]] [get_bd_nets $p_clk]] == -1 } {
    ##         incr sys_mem_clk_index
    ##         set_property CONFIG.NUM_CLKS [expr $sys_mem_clk_index +1] $m_interconnect_cell
    ##         ad_connect $p_clk $m_interconnect_cell/ACLK$sys_mem_clk_index
    ##     }
    ##     ad_connect $m_interconnect_cell/${i_str}_AXI $p_name_int
    ##     if {$p_intf_clock ne ""} {
    ##       ad_connect $p_clk $p_intf_clock
    ##     }
    ## 
    ##     set mem_mapped [get_bd_addr_segs -of [get_bd_addr_spaces -of  [get_bd_intf_pins -filter {NAME=~ *DLMB*} -of [get_bd_cells /sys_mb]]] -filter {NAME=~ *DDR* || NAME=~ *ddr*}]
    ## 
    ##     if {$mem_mapped eq ""} {
    ##       assign_bd_address $m_addr_seg
    ##     } else {
    ##       assign_bd_address -offset [get_property OFFSET $mem_mapped] \
    ##                         -range  [get_property RANGE $mem_mapped] $m_addr_seg
    ##     }
    ##   }
    ## 
    ##   if {$p_sel eq "MEM"} {set sys_mem_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP0"} {set sys_hp0_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP1"} {set sys_hp1_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP2"} {set sys_hp2_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP3"} {set sys_hp3_interconnect_index $m_interconnect_index}
    ## 
    ## }
    ## proc ad_cpu_interconnect {p_address p_name} {
    ## 
    ##   global sys_zynq
    ##   global sys_cpu_interconnect_index
    ## 
    ##   set i_str "M$sys_cpu_interconnect_index"
    ##   if {$sys_cpu_interconnect_index < 10} {
    ##     set i_str "M0$sys_cpu_interconnect_index"
    ##   }
    ## 
    ##   if {$sys_cpu_interconnect_index == 0} {
    ##     ad_ip_instance axi_interconnect axi_cpu_interconnect
    ##     if {$sys_zynq == 2} {
    ##       ad_connect sys_cpu_clk sys_ps8/maxihpm0_lpd_aclk
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
    ##       ad_connect axi_cpu_interconnect/S00_AXI sys_ps8/M_AXI_HPM0_LPD
    ##     }
    ##     if {$sys_zynq == 1} {
    ##       ad_connect sys_cpu_clk sys_ps7/M_AXI_GP0_ACLK
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
    ##       ad_connect axi_cpu_interconnect/S00_AXI sys_ps7/M_AXI_GP0
    ##     }
    ##     if {$sys_zynq == 0} {
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
    ##       ad_connect axi_cpu_interconnect/S00_AXI sys_mb/M_AXI_DP
    ##     }
    ##   }
    ## 
    ##   if {$sys_zynq == 2} {
    ##     set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps8/Data]
    ##   }
    ##   if {$sys_zynq == 1} {
    ##     set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps7/Data]
    ##   }
    ##   if {$sys_zynq == 0} {
    ##     set sys_addr_cntrl_space [get_bd_addr_spaces sys_mb/Data]
    ##   }
    ## 
    ##   set sys_cpu_interconnect_index [expr $sys_cpu_interconnect_index + 1]
    ## 
    ## 
    ##   set p_cell [get_bd_cells $p_name]
    ##   set p_intf [get_bd_intf_pins -filter "MODE == Slave && VLNV == xilinx.com:interface:aximm_rtl:1.0"\
    ##     -of_objects $p_cell]
    ## 
    ##   set p_hier_cell $p_cell
    ##   set p_hier_intf $p_intf
    ## 
    ##   while {$p_hier_intf != "" && [get_property TYPE $p_hier_cell] == "hier"} {
    ##     set p_hier_intf [find_bd_objs -boundary_type lower \
    ##       -relation connected_to $p_hier_intf]
    ##     if {$p_hier_intf != {}} {
    ##       set p_hier_cell [get_bd_cells -of_objects $p_hier_intf]
    ##     } else {
    ##       set p_hier_cell {}
    ##     }
    ##   }
    ## 
    ##   set p_intf_clock ""
    ##   set p_intf_reset ""
    ## 
    ##   if {$p_hier_cell != {}} {
    ##     set p_intf_name [lrange [split $p_hier_intf "/"] end end]
    ## 
    ##     set p_intf_clock [get_bd_pins -filter "TYPE == clk && \
    ##       (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
    ##       CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || \
    ##       CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
    ##       CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" \
    ##       -quiet -of_objects $p_hier_cell]
    ##     set p_intf_reset [get_bd_pins -filter "TYPE == rst && \
    ##       (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
    ##        CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* ||
    ##        CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
    ##        CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" \
    ##        -quiet -of_objects $p_hier_cell]
    ## 
    ##     if {($p_intf_clock ne "") && ($p_intf_reset eq "")} {
    ##       set p_intf_reset [get_property CONFIG.ASSOCIATED_RESET [get_bd_pins ${p_intf_clock}]]
    ##       if {$p_intf_reset ne ""} {
    ##         set p_intf_reset [get_bd_pins -filter "NAME == $p_intf_reset" -of_objects $p_hier_cell]
    ##       }
    ##     }
    ## 
    ##     # Trace back up
    ##     set p_hier_cell2 $p_hier_cell
    ## 
    ##     while {$p_intf_clock != {} && $p_hier_cell2 != $p_cell && $p_hier_cell2 != {}} {
    ##       puts $p_intf_clock
    ##       puts $p_hier_cell2
    ##       set p_intf_clock [find_bd_objs -boundary_type upper \
    ##         -relation connected_to $p_intf_clock]
    ##       if {$p_intf_clock != {}} {
    ##         set p_intf_clock [get_bd_pins [get_property PATH $p_intf_clock]]
    ##         set p_hier_cell2 [get_bd_cells -of_objects $p_intf_clock]
    ##       }
    ##     }
    ## 
    ##     set p_hier_cell2 $p_hier_cell
    ## 
    ##     while {$p_intf_reset != {} && $p_hier_cell2 != $p_cell && $p_hier_cell2 != {}} {
    ##       set p_intf_reset [find_bd_objs -boundary_type upper \
    ##         -relation connected_to $p_intf_reset]
    ##       if {$p_intf_reset != {}} {
    ##         set p_intf_reset [get_bd_pins [get_property PATH $p_intf_reset]]
    ##         set p_hier_cell2 [get_bd_cells -of_objects $p_intf_reset]
    ##       }
    ##     }
    ##   }
    ## 
    ## 
    ##   if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne ""} {
    ##     set p_intf_clock ""
    ##   }
    ##   if {$p_intf_reset ne ""} {
    ##     if {[find_bd_objs -quiet -relation connected_to $p_intf_reset] ne ""} {
    ##       set p_intf_reset ""
    ##     }
    ##   }
    ## 
    ##   set_property CONFIG.NUM_MI $sys_cpu_interconnect_index [get_bd_cells axi_cpu_interconnect]
    ## 
    ##   ad_connect sys_cpu_clk axi_cpu_interconnect/${i_str}_ACLK
    ##   if {$p_intf_clock ne ""} {
    ##     ad_connect sys_cpu_clk ${p_intf_clock}
    ##   }
    ##   ad_connect sys_cpu_resetn axi_cpu_interconnect/${i_str}_ARESETN
    ##   if {$p_intf_reset ne ""} {
    ##     ad_connect sys_cpu_resetn ${p_intf_reset}
    ##   }
    ##   ad_connect axi_cpu_interconnect/${i_str}_AXI ${p_intf}
    ## 
    ##   set p_seg [get_bd_addr_segs -of_objects $p_hier_cell]
    ##   set p_index 0
    ##   foreach p_seg_name $p_seg {
    ##     if {$p_index == 0} {
    ##       set p_seg_range [get_property range $p_seg_name]
    ##       if {$p_seg_range < 0x1000} {
    ##         set p_seg_range 0x1000
    ##       }
    ##       if {$sys_zynq == 2} {
    ##         if {($p_address >= 0x40000000) && ($p_address <= 0x4fffffff)} {
    ##           set p_address [expr ($p_address + 0x40000000)]
    ##         }
    ##         if {($p_address >= 0x70000000) && ($p_address <= 0x7fffffff)} {
    ##           set p_address [expr ($p_address + 0x20000000)]
    ##         }
    ##       }
    ##       create_bd_addr_seg -range $p_seg_range \
    ##         -offset $p_address $sys_addr_cntrl_space \
    ##         $p_seg_name "SEG_data_${p_name}"
    ##     } else {
    ##       assign_bd_address $p_seg_name
    ##     }
    ##     incr p_index
    ##   }
    ## }
    ## proc ad_cpu_interrupt {p_ps_index p_mb_index p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {$sys_zynq == 0} {set p_index_int $p_mb_index}
    ##   if {$sys_zynq >= 1} {set p_index_int $p_ps_index}
    ## 
    ##   set p_index [regsub -all {[^0-9]} $p_index_int ""]
    ##   set m_index [expr ($p_index - 8)]
    ## 
    ##   if {($sys_zynq == 2) && ($p_index <= 7)} {
    ##     set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_0/In$p_index]]
    ##     set p_pin [get_bd_pins sys_concat_intc_0/In$p_index]
    ## 
    ##     puts "disconnect_bd_net $p_net $p_pin"
    ##     disconnect_bd_net $p_net $p_pin
    ##     ad_connect sys_concat_intc_0/In$p_index $p_name
    ##   }
    ## 
    ##   if {($sys_zynq == 2) && ($p_index >= 8)} {
    ##     set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_1/In$m_index]]
    ##     set p_pin [get_bd_pins sys_concat_intc_1/In$m_index]
    ## 
    ##     puts "disconnect_bd_net $p_net $p_pin"
    ##     disconnect_bd_net $p_net $p_pin
    ##     ad_connect sys_concat_intc_1/In$m_index $p_name
    ##   }
    ## 
    ##   if {$sys_zynq <= 1} {
    ## 
    ##     set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc/In$p_index]]
    ##     set p_pin [get_bd_pins sys_concat_intc/In$p_index]
    ## 
    ##     puts "disconnect_bd_net $p_net $p_pin"
    ##     disconnect_bd_net $p_net $p_pin
    ##     ad_connect sys_concat_intc/In$p_index $p_name
    ##   }
    ## }
    ## proc stringtohex {str blocksize} {
    ##   binary scan $str H* hex
    ##   return [format %0-[expr $blocksize * 2]s $hex]
    ## }
    ## proc checksum8bit {hex} {
    ## 
    ##   set chks 0
    ##   for {set i 0} {$i < [string length $hex]} {incr i} {
    ##     if { ($i+1) % 2 == 0} {
    ##       set chks [expr $chks + "0x[string range $hex $i-1 $i]"]
    ##     }
    ##   }
    ##   return [format %0.2x [expr 255 - [expr "0x[string range [format %0.2x $chks] [expr [string length [format %0.2x $chks]] -2] [expr [string length [format %0.2x $chks]] -1]]"] +1]]
    ## }
    ## proc hexstr_flip {str} {
    ## 
    ##   set fstr {}
    ##   for {set i 0} {$i < [string length $str]} {incr i} {
    ##     if { ($i+1) % 8 == 0} {
    ##       set line [string range $str [expr $i - 7] $i]
    ##       set fline {}
    ##       for {set j 0} {$j < [string length $line]} {incr j} {
    ##         if { ($j+1) % 2 == 0} {
    ##           append fline [string reverse [append byte [string index $line $j]]]
    ##         } else {
    ##           set byte [string index $line $j]
    ##         }
    ##       }
    ##       append fstr [string reverse $fline]
    ##     }
    ##   }
    ##   return $fstr
    ## }
    ## proc sysid_gen_sys_init_file {{custom_string {}}} {
    ## 
    ##   # git sha
    ##   if {[catch {exec git rev-parse HEAD} gitsha_string] != 0} {
    ##     set gitsha_string 0
    ##   }
    ##   set gitsha_hex [hexstr_flip [stringtohex $gitsha_string 44]]
    ## 
    ##   #git clean
    ##   set git_clean_string "f"
    ##   if {$gitsha_string != 0} {
    ##     if {[catch {exec git status .} gitstat_string] == 0} {
    ##       if [expr [string match *modified $gitstat_string] == 0] {
    ##         set git_clean_string "t"
    ##       }
    ##     }
    ##   }
    ##   set git_clean_hex [hexstr_flip [stringtohex $git_clean_string 4]]
    ## 
    ##   # vadj check
    ##   set vadj_check_string "vadj"
    ##   set vadj_check_hex [hexstr_flip [stringtohex $vadj_check_string 4]]
    ## 
    ##   # time and date
    ##   set thetime [clock seconds]
    ##   set timedate_hex [hexstr_flip [stringtohex $thetime 12]]
    ## 
    ##   # merge components
    ##   set verh_hex {}
    ##   set verh_size 448
    ## 
    ##   append verh_hex $gitsha_hex $git_clean_hex $vadj_check_hex $timedate_hex
    ##   append verh_hex "00000000" [checksum8bit $verh_hex] "000000"
    ##   set verh_hex [format %0-[expr [expr $verh_size] * 8]s $verh_hex]
    ## 
    ##   # common header
    ##   # size in lines
    ##   set table_size 16
    ##   set comh_size [expr 8 * $table_size]
    ## 
    ##   # set version
    ##   set comh_ver_hex "00000001"
    ## 
    ##   set boardname [lindex [split [current_project] _] [expr [llength [split [current_project] _]] - 1]]
    ## 
    ##   # board name
    ##   set boardname_hex [hexstr_flip [stringtohex $boardname 32]]
    ##   
    ##   # project name
    ##   set projname_hex [hexstr_flip [stringtohex [string trimright [string trimright [current_project] $boardname] _] 32]]
    ## 
    ##   # custom string
    ##   set custom_hex [hexstr_flip [stringtohex $custom_string 64]]
    ## 
    ##   # pr offset
    ##   # not used
    ##   set pr_offset "00000000"
    ## 
    ##   # init - generate header
    ##   set comh_hex {}
    ##   append comh_hex $comh_ver_hex
    ## 
    ##   # offset for internal use area
    ##   set offset $table_size
    ##   append comh_hex [format %08s [format %0.2x $offset]]
    ## 
    ##   # offset for projname_hex
    ##   set offset [expr $table_size + $verh_size]
    ##   append comh_hex [format %08s [format %0.2x $offset]]
    ## 
    ##   # offset for boardname_hex
    ##   set offset [expr $offset + [expr [string length $projname_hex] / 8]]
    ##   append comh_hex [format %08s [format %0.2x $offset]]
    ## 
    ##   # offset for custom_hex
    ##   set offset [expr $offset + [expr [string length $boardname_hex] / 8]]
    ##   append comh_hex [format %08s [format %0.2x $offset]]
    ## 
    ##   # offset for pr custom string
    ##   set offset $pr_offset
    ##   append comh_hex [format %08s $offset]
    ## 
    ##   # pad header to match size and add checksum
    ##   set comh_hex [format %0-[expr [expr $table_size - 2] * 8]s $comh_hex]
    ##   append comh_hex "00000000" [checksum8bit $comh_hex] "000000"
    ## 
    ##   # creating file
    ##   set sys_mem_hex [format %0-[expr 512 * 8]s [concat $comh_hex$verh_hex$projname_hex$boardname_hex$custom_hex]]
    ## 
    ##   set sys_mem_file [open "mem_init_sys.txt" "w"]
    ## 
    ##   # writting 32 bits to each line
    ##   for {set i 0} {$i < [string length $sys_mem_hex]} {incr i} {
    ##     if { ($i+1) % 8 == 0} {
    ##       puts $sys_mem_file [string index $sys_mem_hex $i]
    ##     } else {
    ##       puts -nonewline $sys_mem_file [string index $sys_mem_hex $i]
    ##     }
    ##   }
    ##   close $sys_mem_file
    ## }
    ## proc sysid_gen_pr_init_file {custom_string} {
    ## 
    ##   set custom_hex [stringtohex $custom_string 64]
    ## 
    ##   # creating file
    ##   set pr_mem_file [open "mem_init_pr.txt" "w"]
    ## 
    ##   # writting 32 bits to each line
    ##   for {set i 0} {$i < [string length $custom_hex]} {incr i} {
    ##     if { ($i+1) % 8 == 0} {
    ##       puts $pr_mem_file [string index $custom_hex $i]
    ##     } else {
    ##       puts -nonewline $pr_mem_file [string index $custom_hex $i]
    ##     }
    ##   }
    ##   close $pr_mem_file
    ## }
    # set p_device "xc7z035ifbg676-2L"
    # adi_project adrv9361z7035_ccfmc_lvds
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nicole/adi/hdl/library'.
    WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/nicole/adi/ghdl/library'; Can't find the specified path.
    If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
    ## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
    ## set_msg_config -id {BD 41-1343} -new_severity WARNING
    ## set_msg_config -id {BD 41-1306} -new_severity WARNING
    ## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
    ## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
    ## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
    ## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
    ## set_msg_config -id {Synth 8-3331} -new_severity INFO
    ## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
    ## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
    ## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
    Wrote  : </home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/system.bd> 
    ## source ../common/adrv9361z7035_bd.tcl
    ### create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
    ### create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
    ### create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
    ### create_bd_port -dir O spi0_csn_2_o
    ### create_bd_port -dir O spi0_csn_1_o
    ### create_bd_port -dir O spi0_csn_0_o
    ### create_bd_port -dir I spi0_csn_i
    ### create_bd_port -dir I spi0_clk_i
    ### create_bd_port -dir O spi0_clk_o
    ### create_bd_port -dir I spi0_sdo_i
    ### create_bd_port -dir O spi0_sdo_o
    ### create_bd_port -dir I spi0_sdi_i
    ### create_bd_port -dir O spi1_csn_2_o
    ### create_bd_port -dir O spi1_csn_1_o
    ### create_bd_port -dir O spi1_csn_0_o
    ### create_bd_port -dir I spi1_csn_i
    ### create_bd_port -dir I spi1_clk_i
    ### create_bd_port -dir O spi1_clk_o
    ### create_bd_port -dir I spi1_sdo_i
    ### create_bd_port -dir O spi1_sdo_o
    ### create_bd_port -dir I spi1_sdi_i
    ### create_bd_port -dir I -from 63 -to 0 gpio_i
    ### create_bd_port -dir O -from 63 -to 0 gpio_o
    ### create_bd_port -dir O -from 63 -to 0 gpio_t
    ### set otg_vbusoc      [create_bd_port -dir I otg_vbusoc]
    ### ad_ip_instance processing_system7 sys_ps7
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK0_VOLTAGE "LVCMOS 1.8V"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK1_VOLTAGE "LVCMOS 1.8V"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_PACKAGE_NAME fbg676
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_PERIPHERAL_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_ENET0_IO "MIO 16 .. 27"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_IO "MIO 52 .. 53"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_PERIPHERAL_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET_RESET_SELECT "Separate reset pins"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_RESET_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_RESET_IO "MIO 8"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_RESET_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_RESET_IO "MIO 51"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_PERIPHERAL_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_CD_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_CD_IO "MIO 50"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ 50
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_PERIPHERAL_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_PERIPHERAL_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_IO "MIO 7"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_PERIPHERAL_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_PARTNO "MT41K256M16 RE-125"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH "32 Bit"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF 0
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 -0.053
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 -0.059
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 0.065
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 0.066
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 0.264
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 0.265
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 0.330
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 0.330
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE 0
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK1_PORT 1
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST1_PORT 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK2_PORT 1
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST2_PORT 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 100.0
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 200.0
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 200.0
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_USE_FABRIC_INTERRUPT 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_INTR 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE 1
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 64
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_MODE REVERSE
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_PERIPHERAL_ENABLE 1
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_SPI0_IO EMIO
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_PERIPHERAL_ENABLE 1
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_SPI1_IO EMIO
    ### ad_ip_instance axi_iic axi_iic_main
    ### ad_ip_parameter axi_iic_main CONFIG.USE_BOARD_FLOW true
    ### ad_ip_parameter axi_iic_main CONFIG.IIC_BOARD_INTERFACE Custom
    ### ad_ip_instance xlconcat sys_concat_intc
    ### ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16
    ### ad_ip_instance proc_sys_reset sys_rstgen
    ### ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
    ### ad_ip_instance util_vector_logic sys_logic_inv
    ### ad_ip_parameter sys_logic_inv CONFIG.C_SIZE 1
    ### ad_ip_parameter sys_logic_inv CONFIG.C_OPERATION not
    ### ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0
    create_bd_net sys_cpu_clk
    connect_bd_net -net /sys_cpu_clk /sys_ps7/FCLK_CLK0
    ### ad_connect sys_200m_clk sys_ps7/FCLK_CLK1
    create_bd_net sys_200m_clk
    connect_bd_net -net /sys_200m_clk /sys_ps7/FCLK_CLK1
    ### ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
    create_bd_net sys_cpu_reset
    connect_bd_net -net /sys_cpu_reset /sys_rstgen/peripheral_reset
    ### ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
    create_bd_net sys_cpu_resetn
    connect_bd_net -net /sys_cpu_resetn /sys_rstgen/peripheral_aresetn
    ### ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
    connect_bd_net -net /sys_cpu_clk /sys_rstgen/slowest_sync_clk
    ### ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
    connect_bd_net /sys_rstgen/ext_reset_in /sys_ps7/FCLK_RESET0_N
    ### ad_connect ddr sys_ps7/DDR
    connect_bd_intf_net /ddr /sys_ps7/DDR
    ### ad_connect gpio_i sys_ps7/GPIO_I
    connect_bd_net /gpio_i /sys_ps7/GPIO_I
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/GPIO_I is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0
    ### ad_connect gpio_o sys_ps7/GPIO_O
    connect_bd_net /gpio_o /sys_ps7/GPIO_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/GPIO_O is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0
    ### ad_connect gpio_t sys_ps7/GPIO_T
    connect_bd_net /gpio_t /sys_ps7/GPIO_T
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/GPIO_T is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0
    ### ad_connect fixed_io sys_ps7/FIXED_IO
    connect_bd_intf_net /fixed_io /sys_ps7/FIXED_IO
    ### ad_connect iic_main axi_iic_main/iic
    connect_bd_intf_net /iic_main /axi_iic_main/IIC
    ### ad_connect sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT
    connect_bd_net /sys_logic_inv/Res /sys_ps7/USB0_VBUS_PWRFAULT
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/USB0_VBUS_PWRFAULT is being overridden by the user. This pin will not be connected as a part of interface connection USBIND_0
    ### ad_connect sys_logic_inv/Op1 otg_vbusoc
    connect_bd_net /sys_logic_inv/Op1 /otg_vbusoc
    ### ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O
    connect_bd_net /spi0_csn_2_o /sys_ps7/SPI0_SS2_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS2_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    ### ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O
    connect_bd_net /spi0_csn_1_o /sys_ps7/SPI0_SS1_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS1_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    ### ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O
    connect_bd_net /spi0_csn_0_o /sys_ps7/SPI0_SS_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    ### ad_connect spi0_csn_i sys_ps7/SPI0_SS_I
    connect_bd_net /spi0_csn_i /sys_ps7/SPI0_SS_I
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    ### ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I
    connect_bd_net /spi0_clk_i /sys_ps7/SPI0_SCLK_I
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SCLK_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    ### ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O
    connect_bd_net /spi0_clk_o /sys_ps7/SPI0_SCLK_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SCLK_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    ### ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I
    connect_bd_net /spi0_sdo_i /sys_ps7/SPI0_MOSI_I
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_MOSI_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    ### ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O
    connect_bd_net /spi0_sdo_o /sys_ps7/SPI0_MOSI_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_MOSI_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    ### ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I
    connect_bd_net /spi0_sdi_i /sys_ps7/SPI0_MISO_I
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_MISO_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    ### ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O
    connect_bd_net /spi1_csn_2_o /sys_ps7/SPI1_SS2_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS2_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    ### ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O
    connect_bd_net /spi1_csn_1_o /sys_ps7/SPI1_SS1_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS1_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    ### ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O
    connect_bd_net /spi1_csn_0_o /sys_ps7/SPI1_SS_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    ### ad_connect spi1_csn_i sys_ps7/SPI1_SS_I
    connect_bd_net /spi1_csn_i /sys_ps7/SPI1_SS_I
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    ### ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I
    connect_bd_net /spi1_clk_i /sys_ps7/SPI1_SCLK_I
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SCLK_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    ### ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O
    connect_bd_net /spi1_clk_o /sys_ps7/SPI1_SCLK_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SCLK_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    ### ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I
    connect_bd_net /spi1_sdo_i /sys_ps7/SPI1_MOSI_I
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_MOSI_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    ### ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O
    connect_bd_net /spi1_sdo_o /sys_ps7/SPI1_MOSI_O
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_MOSI_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    ### ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I
    connect_bd_net /spi1_sdi_i /sys_ps7/SPI1_MISO_I
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_MISO_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
    ### ad_ip_instance axi_sysid axi_sysid_0
    ### ad_ip_instance sysid_rom rom_sys_0
    ### ad_connect  axi_sysid_0/rom_addr   	rom_sys_0/rom_addr
    connect_bd_net /axi_sysid_0/rom_addr /rom_sys_0/rom_addr
    ### ad_connect  axi_sysid_0/sys_rom_data   	rom_sys_0/rom_data
    connect_bd_net /axi_sysid_0/sys_rom_data /rom_sys_0/rom_data
    ### ad_connect  sys_cpu_clk                 rom_sys_0/clk
    connect_bd_net -net /sys_cpu_clk /rom_sys_0/clk
    ### ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P
    connect_bd_net /sys_concat_intc/dout /sys_ps7/IRQ_F2P
    ### ad_connect sys_concat_intc/In15 GND
    connect_bd_net GND_1/dout sys_concat_intc/In15
    ### ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
    connect_bd_net /sys_concat_intc/In14 /axi_iic_main/iic2intc_irpt
    ### ad_connect sys_concat_intc/In13 GND
    connect_bd_net GND_1/dout sys_concat_intc/In13
    ### ad_connect sys_concat_intc/In12 GND
    connect_bd_net GND_1/dout sys_concat_intc/In12
    ### ad_connect sys_concat_intc/In11 GND
    connect_bd_net GND_1/dout sys_concat_intc/In11
    ### ad_connect sys_concat_intc/In10 GND
    connect_bd_net GND_1/dout sys_concat_intc/In10
    ### ad_connect sys_concat_intc/In9  GND
    connect_bd_net GND_1/dout sys_concat_intc/In9
    ### ad_connect sys_concat_intc/In8  GND
    connect_bd_net GND_1/dout sys_concat_intc/In8
    ### ad_connect sys_concat_intc/In7  GND
    connect_bd_net GND_1/dout sys_concat_intc/In7
    ### ad_connect sys_concat_intc/In6  GND
    connect_bd_net GND_1/dout sys_concat_intc/In6
    ### ad_connect sys_concat_intc/In5  GND
    connect_bd_net GND_1/dout sys_concat_intc/In5
    ### ad_connect sys_concat_intc/In4  GND
    connect_bd_net GND_1/dout sys_concat_intc/In4
    ### ad_connect sys_concat_intc/In3  GND
    connect_bd_net GND_1/dout sys_concat_intc/In3
    ### ad_connect sys_concat_intc/In2  GND
    connect_bd_net GND_1/dout sys_concat_intc/In2
    ### ad_connect sys_concat_intc/In1  GND
    connect_bd_net GND_1/dout sys_concat_intc/In1
    ### ad_connect sys_concat_intc/In0  GND
    connect_bd_net GND_1/dout sys_concat_intc/In0
    ### ad_cpu_interconnect 0x45000000 axi_sysid_0
    connect_bd_net -net /sys_cpu_clk /sys_ps7/M_AXI_GP0_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/ACLK
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/S00_ACLK
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/S00_ARESETN
    connect_bd_intf_net /axi_cpu_interconnect/S00_AXI /sys_ps7/M_AXI_GP0
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M00_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_sysid_0/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M00_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_sysid_0/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M00_AXI /axi_sysid_0/s_axi
    ### ad_cpu_interconnect 0x41600000 axi_iic_main
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M01_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_iic_main/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M01_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_iic_main/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M01_AXI /axi_iic_main/S_AXI
    ### create_bd_port -dir O enable
    ### create_bd_port -dir O txnrx
    ### create_bd_port -dir I up_enable
    ### create_bd_port -dir I up_txnrx
    ### create_bd_port -dir O tdd_sync_o
    ### create_bd_port -dir I tdd_sync_i
    ### create_bd_port -dir O tdd_sync_t
    ### create_bd_port -dir I gps_pps
    ### ad_ip_instance axi_ad9361 axi_ad9361
    ### ad_ip_parameter axi_ad9361 CONFIG.ID 0
    ### ad_ip_parameter axi_ad9361 CONFIG.DAC_IODELAY_ENABLE 1
    ### ad_connect sys_200m_clk axi_ad9361/delay_clk
    connect_bd_net -net /sys_200m_clk /axi_ad9361/delay_clk
    ### ad_connect axi_ad9361/l_clk axi_ad9361/clk
    connect_bd_net /axi_ad9361/l_clk /axi_ad9361/clk
    ### ad_connect enable axi_ad9361/enable
    connect_bd_net /enable /axi_ad9361/enable
    ### ad_connect txnrx axi_ad9361/txnrx
    connect_bd_net /txnrx /axi_ad9361/txnrx
    ### ad_connect up_enable axi_ad9361/up_enable
    connect_bd_net /up_enable /axi_ad9361/up_enable
    ### ad_connect up_txnrx axi_ad9361/up_txnrx
    connect_bd_net /up_txnrx /axi_ad9361/up_txnrx
    ### ad_ip_instance util_tdd_sync util_ad9361_tdd_sync
    ### ad_ip_parameter util_ad9361_tdd_sync CONFIG.TDD_SYNC_PERIOD 10000000
    ### ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk
    connect_bd_net -net /sys_cpu_clk /util_ad9361_tdd_sync/clk
    ### ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn
    connect_bd_net -net /sys_cpu_resetn /util_ad9361_tdd_sync/rstn
    ### ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync
    connect_bd_net /util_ad9361_tdd_sync/sync_out /axi_ad9361/tdd_sync
    ### ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr
    connect_bd_net /util_ad9361_tdd_sync/sync_mode /axi_ad9361/tdd_sync_cntr
    ### ad_connect tdd_sync_t axi_ad9361/tdd_sync_cntr
    connect_bd_net /tdd_sync_t /axi_ad9361/tdd_sync_cntr
    ### ad_connect tdd_sync_o util_ad9361_tdd_sync/sync_out
    connect_bd_net /tdd_sync_o /util_ad9361_tdd_sync/sync_out
    ### ad_connect tdd_sync_i util_ad9361_tdd_sync/sync_in
    connect_bd_net /tdd_sync_i /util_ad9361_tdd_sync/sync_in
    ### ad_connect gps_pps axi_ad9361/gps_pps
    connect_bd_net /gps_pps /axi_ad9361/gps_pps
    ### ad_ip_instance xlconcat util_ad9361_divclk_sel_concat
    WARNING: [BD 41-1753] The name 'util_ad9361_divclk_sel_concat' you have specified is long. The Windows OS has path length limitations. It is recommended you use shorter names(less than 25 characters) to reduce the likelihood of issues when/if running on windows OS.
    ### ad_ip_parameter util_ad9361_divclk_sel_concat CONFIG.NUM_PORTS 2
    ### ad_connect axi_ad9361/adc_r1_mode util_ad9361_divclk_sel_concat/In0
    connect_bd_net /axi_ad9361/adc_r1_mode /util_ad9361_divclk_sel_concat/In0
    ### ad_connect axi_ad9361/dac_r1_mode util_ad9361_divclk_sel_concat/In1
    connect_bd_net /axi_ad9361/dac_r1_mode /util_ad9361_divclk_sel_concat/In1
    ### ad_ip_instance util_reduced_logic util_ad9361_divclk_sel
    ### ad_ip_parameter util_ad9361_divclk_sel CONFIG.C_SIZE 2
    ### ad_connect util_ad9361_divclk_sel_concat/dout util_ad9361_divclk_sel/Op1
    connect_bd_net /util_ad9361_divclk_sel_concat/dout /util_ad9361_divclk_sel/Op1
    ### ad_ip_instance util_clkdiv util_ad9361_divclk
    ### ad_connect util_ad9361_divclk_sel/Res util_ad9361_divclk/clk_sel
    connect_bd_net /util_ad9361_divclk_sel/Res /util_ad9361_divclk/clk_sel
    ### ad_connect axi_ad9361/l_clk util_ad9361_divclk/clk
    connect_bd_net /axi_ad9361/l_clk /util_ad9361_divclk/clk
    ### ad_ip_instance proc_sys_reset util_ad9361_divclk_reset
    ### ad_connect sys_rstgen/peripheral_aresetn util_ad9361_divclk_reset/ext_reset_in
    connect_bd_net /sys_rstgen/peripheral_aresetn /util_ad9361_divclk_reset/ext_reset_in
    ### ad_connect util_ad9361_divclk/clk_out util_ad9361_divclk_reset/slowest_sync_clk
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_divclk_reset/slowest_sync_clk
    ### ad_ip_instance util_wfifo util_ad9361_adc_fifo
    ### ad_ip_parameter util_ad9361_adc_fifo CONFIG.NUM_OF_CHANNELS 4
    ### ad_ip_parameter util_ad9361_adc_fifo CONFIG.DIN_ADDRESS_WIDTH 4
    ### ad_ip_parameter util_ad9361_adc_fifo CONFIG.DIN_DATA_WIDTH 16
    ### ad_ip_parameter util_ad9361_adc_fifo CONFIG.DOUT_DATA_WIDTH 16
    ### ad_connect axi_ad9361/l_clk util_ad9361_adc_fifo/din_clk
    connect_bd_net /axi_ad9361/l_clk /util_ad9361_adc_fifo/din_clk
    ### ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst
    connect_bd_net /axi_ad9361/rst /util_ad9361_adc_fifo/din_rst
    ### ad_connect util_ad9361_divclk/clk_out util_ad9361_adc_fifo/dout_clk
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_adc_fifo/dout_clk
    ### ad_connect util_ad9361_divclk_reset/peripheral_aresetn util_ad9361_adc_fifo/dout_rstn
    connect_bd_net /util_ad9361_divclk_reset/peripheral_aresetn /util_ad9361_adc_fifo/dout_rstn
    ### ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0
    connect_bd_net /axi_ad9361/adc_enable_i0 /util_ad9361_adc_fifo/din_enable_0
    ### ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0
    connect_bd_net /axi_ad9361/adc_valid_i0 /util_ad9361_adc_fifo/din_valid_0
    ### ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0
    connect_bd_net /axi_ad9361/adc_data_i0 /util_ad9361_adc_fifo/din_data_0
    ### ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1
    connect_bd_net /axi_ad9361/adc_enable_q0 /util_ad9361_adc_fifo/din_enable_1
    ### ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1
    connect_bd_net /axi_ad9361/adc_valid_q0 /util_ad9361_adc_fifo/din_valid_1
    ### ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1
    connect_bd_net /axi_ad9361/adc_data_q0 /util_ad9361_adc_fifo/din_data_1
    ### ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2
    connect_bd_net /axi_ad9361/adc_enable_i1 /util_ad9361_adc_fifo/din_enable_2
    ### ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2
    connect_bd_net /axi_ad9361/adc_valid_i1 /util_ad9361_adc_fifo/din_valid_2
    ### ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2
    connect_bd_net /axi_ad9361/adc_data_i1 /util_ad9361_adc_fifo/din_data_2
    ### ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3
    connect_bd_net /axi_ad9361/adc_enable_q1 /util_ad9361_adc_fifo/din_enable_3
    ### ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3
    connect_bd_net /axi_ad9361/adc_valid_q1 /util_ad9361_adc_fifo/din_valid_3
    ### ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3
    connect_bd_net /axi_ad9361/adc_data_q1 /util_ad9361_adc_fifo/din_data_3
    ### ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
    connect_bd_net /util_ad9361_adc_fifo/din_ovf /axi_ad9361/adc_dovf
    ### ad_ip_instance util_cpack2 util_ad9361_adc_pack { \
    ###   NUM_OF_CHANNELS 4 \
    ###   SAMPLE_DATA_WIDTH 16 \
    ### }
    ### ad_connect util_ad9361_divclk/clk_out util_ad9361_adc_pack/clk
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_adc_pack/clk
    ### ad_connect util_ad9361_divclk_reset/peripheral_reset util_ad9361_adc_pack/reset
    connect_bd_net /util_ad9361_divclk_reset/peripheral_reset /util_ad9361_adc_pack/reset
    ### ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/fifo_wr_en
    connect_bd_net /util_ad9361_adc_fifo/dout_valid_0 /util_ad9361_adc_pack/fifo_wr_en
    ### ad_connect util_ad9361_adc_pack/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
    connect_bd_net /util_ad9361_adc_pack/fifo_wr_overflow /util_ad9361_adc_fifo/dout_ovf
    ### for {set i 0} {$i < 4} {incr i} {
    ###   ad_connect util_ad9361_adc_fifo/dout_enable_${i} util_ad9361_adc_pack/enable_${i}
    ###   ad_connect util_ad9361_adc_fifo/dout_data_${i} util_ad9361_adc_pack/fifo_wr_data_${i}
    ### }
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_0 /util_ad9361_adc_pack/enable_0
    connect_bd_net /util_ad9361_adc_fifo/dout_data_0 /util_ad9361_adc_pack/fifo_wr_data_0
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_1 /util_ad9361_adc_pack/enable_1
    connect_bd_net /util_ad9361_adc_fifo/dout_data_1 /util_ad9361_adc_pack/fifo_wr_data_1
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_2 /util_ad9361_adc_pack/enable_2
    connect_bd_net /util_ad9361_adc_fifo/dout_data_2 /util_ad9361_adc_pack/fifo_wr_data_2
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_3 /util_ad9361_adc_pack/enable_3
    connect_bd_net /util_ad9361_adc_fifo/dout_data_3 /util_ad9361_adc_pack/fifo_wr_data_3
    ### ad_ip_instance axi_dmac axi_ad9361_adc_dma
    ### ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_SRC 2
    ### ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_DEST 0
    ### ad_ip_parameter axi_ad9361_adc_dma CONFIG.CYCLIC 0
    ### ad_ip_parameter axi_ad9361_adc_dma CONFIG.SYNC_TRANSFER_START 1
    ### ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_SRC 0
    ### ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_DEST 0
    ### ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_2D_TRANSFER 0
    ### ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 64
    ### ad_connect util_ad9361_divclk/clk_out axi_ad9361_adc_dma/fifo_wr_clk
    connect_bd_net /util_ad9361_divclk/clk_out /axi_ad9361_adc_dma/fifo_wr_clk
    ### ad_connect util_ad9361_adc_pack/packed_fifo_wr axi_ad9361_adc_dma/fifo_wr
    connect_bd_intf_net /util_ad9361_adc_pack/packed_fifo_wr /axi_ad9361_adc_dma/fifo_wr
    ### ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_adc_dma/m_dest_axi_aresetn
    ### ad_ip_instance util_rfifo axi_ad9361_dac_fifo
    ### ad_ip_parameter axi_ad9361_dac_fifo CONFIG.DIN_DATA_WIDTH 16
    ### ad_ip_parameter axi_ad9361_dac_fifo CONFIG.DOUT_DATA_WIDTH 16
    ### ad_ip_parameter axi_ad9361_dac_fifo CONFIG.DIN_ADDRESS_WIDTH 4
    ### ad_connect axi_ad9361/l_clk axi_ad9361_dac_fifo/dout_clk
    connect_bd_net /axi_ad9361/l_clk /axi_ad9361_dac_fifo/dout_clk
    ### ad_connect axi_ad9361/rst axi_ad9361_dac_fifo/dout_rst
    connect_bd_net /axi_ad9361/rst /axi_ad9361_dac_fifo/dout_rst
    ### ad_connect util_ad9361_divclk/clk_out axi_ad9361_dac_fifo/din_clk
    connect_bd_net /util_ad9361_divclk/clk_out /axi_ad9361_dac_fifo/din_clk
    ### ad_connect util_ad9361_divclk_reset/peripheral_aresetn axi_ad9361_dac_fifo/din_rstn
    connect_bd_net /util_ad9361_divclk_reset/peripheral_aresetn /axi_ad9361_dac_fifo/din_rstn
    ### ad_connect axi_ad9361_dac_fifo/dout_enable_0 axi_ad9361/dac_enable_i0
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_0 /axi_ad9361/dac_enable_i0
    ### ad_connect axi_ad9361_dac_fifo/dout_valid_0 axi_ad9361/dac_valid_i0
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_0 /axi_ad9361/dac_valid_i0
    ### ad_connect axi_ad9361_dac_fifo/dout_data_0 axi_ad9361/dac_data_i0
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_0 /axi_ad9361/dac_data_i0
    ### ad_connect axi_ad9361_dac_fifo/dout_enable_1 axi_ad9361/dac_enable_q0
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_1 /axi_ad9361/dac_enable_q0
    ### ad_connect axi_ad9361_dac_fifo/dout_valid_1 axi_ad9361/dac_valid_q0
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_1 /axi_ad9361/dac_valid_q0
    ### ad_connect axi_ad9361_dac_fifo/dout_data_1 axi_ad9361/dac_data_q0
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_1 /axi_ad9361/dac_data_q0
    ### ad_connect axi_ad9361_dac_fifo/dout_enable_2 axi_ad9361/dac_enable_i1
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_2 /axi_ad9361/dac_enable_i1
    ### ad_connect axi_ad9361_dac_fifo/dout_valid_2 axi_ad9361/dac_valid_i1
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_2 /axi_ad9361/dac_valid_i1
    ### ad_connect axi_ad9361_dac_fifo/dout_data_2 axi_ad9361/dac_data_i1
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_2 /axi_ad9361/dac_data_i1
    ### ad_connect axi_ad9361_dac_fifo/dout_enable_3 axi_ad9361/dac_enable_q1
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_3 /axi_ad9361/dac_enable_q1
    ### ad_connect axi_ad9361_dac_fifo/dout_valid_3 axi_ad9361/dac_valid_q1
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_3 /axi_ad9361/dac_valid_q1
    ### ad_connect axi_ad9361_dac_fifo/dout_data_3 axi_ad9361/dac_data_q1
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_3 /axi_ad9361/dac_data_q1
    ### ad_connect axi_ad9361_dac_fifo/dout_unf axi_ad9361/dac_dunf
    connect_bd_net /axi_ad9361_dac_fifo/dout_unf /axi_ad9361/dac_dunf
    ### ad_ip_instance util_upack2 util_ad9361_dac_upack { \
    ###   NUM_OF_CHANNELS 4 \
    ###   SAMPLE_DATA_WIDTH 16 \
    ### }
    ### ad_connect util_ad9361_divclk/clk_out util_ad9361_dac_upack/clk
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_dac_upack/clk
    ### ad_connect util_ad9361_divclk_reset/peripheral_reset util_ad9361_dac_upack/reset
    connect_bd_net /util_ad9361_divclk_reset/peripheral_reset /util_ad9361_dac_upack/reset
    ### ad_connect util_ad9361_dac_upack/fifo_rd_en axi_ad9361_dac_fifo/din_valid_0
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_en /axi_ad9361_dac_fifo/din_valid_0
    ### ad_connect util_ad9361_dac_upack/fifo_rd_underflow axi_ad9361_dac_fifo/din_unf
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_underflow /axi_ad9361_dac_fifo/din_unf
    ### for {set i 0} {$i < 4} {incr i} {
    ###   ad_connect util_ad9361_dac_upack/enable_$i axi_ad9361_dac_fifo/din_enable_$i
    ###   ad_connect util_ad9361_dac_upack/fifo_rd_valid axi_ad9361_dac_fifo/din_valid_in_$i
    ###   ad_connect util_ad9361_dac_upack/fifo_rd_data_$i axi_ad9361_dac_fifo/din_data_$i
    ### }
    connect_bd_net /util_ad9361_dac_upack/enable_0 /axi_ad9361_dac_fifo/din_enable_0
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_0
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_0 /axi_ad9361_dac_fifo/din_data_0
    connect_bd_net /util_ad9361_dac_upack/enable_1 /axi_ad9361_dac_fifo/din_enable_1
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_1
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_1 /axi_ad9361_dac_fifo/din_data_1
    connect_bd_net /util_ad9361_dac_upack/enable_2 /axi_ad9361_dac_fifo/din_enable_2
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_2
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_2 /axi_ad9361_dac_fifo/din_data_2
    connect_bd_net /util_ad9361_dac_upack/enable_3 /axi_ad9361_dac_fifo/din_enable_3
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_valid /axi_ad9361_dac_fifo/din_valid_in_3
    connect_bd_net /util_ad9361_dac_upack/fifo_rd_data_3 /axi_ad9361_dac_fifo/din_data_3
    ### ad_ip_instance axi_dmac axi_ad9361_dac_dma
    ### ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_SRC 0
    ### ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_DEST 1
    ### ad_ip_parameter axi_ad9361_dac_dma CONFIG.CYCLIC 1
    ### ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 0
    ### ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_DEST 0
    ### ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0
    ### ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 64
    ### ad_connect util_ad9361_divclk/clk_out axi_ad9361_dac_dma/m_axis_aclk
    connect_bd_net /util_ad9361_divclk/clk_out /axi_ad9361_dac_dma/m_axis_aclk
    ### ad_connect axi_ad9361_dac_dma/m_axis util_ad9361_dac_upack/s_axis
    connect_bd_intf_net /axi_ad9361_dac_dma/m_axis /util_ad9361_dac_upack/s_axis
    ### ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_dac_dma/m_src_axi_aresetn
    ### ad_cpu_interconnect 0x79020000 axi_ad9361
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M02_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_ad9361/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M02_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M02_AXI /axi_ad9361/s_axi
    ### ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M03_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_adc_dma/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M03_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_adc_dma/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M03_AXI /axi_ad9361_adc_dma/s_axi
    ### ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M04_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_dac_dma/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M04_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_dac_dma/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M04_AXI /axi_ad9361_dac_dma/s_axi
    ### ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    connect_bd_net -net /sys_cpu_resetn /axi_hp1_interconnect/aresetn
    connect_bd_net -net /sys_cpu_clk /axi_hp1_interconnect/aclk
    connect_bd_intf_net /axi_hp1_interconnect/M00_AXI /sys_ps7/S_AXI_HP1
    connect_bd_net -net /sys_cpu_clk /sys_ps7/S_AXI_HP1_ACLK
    ### ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi
    connect_bd_intf_net /axi_hp1_interconnect/S00_AXI /axi_ad9361_adc_dma/m_dest_axi
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_adc_dma/m_dest_axi_aclk
    WARNING: [BD 5-230] No cells matched 'get_bd_cells /sys_mb'
    WARNING: [BD 5-232] No interface pins matched 'get_bd_intf_pins -filter {NAME=~ *DLMB*} -of {}'
    Slave segment </sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM> is being mapped into address space </axi_ad9361_adc_dma/m_dest_axi> at <0x0000_0000 [ 1G ]>
    ### ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    connect_bd_net -net /sys_cpu_resetn /axi_hp2_interconnect/aresetn
    connect_bd_net -net /sys_cpu_clk /axi_hp2_interconnect/aclk
    connect_bd_intf_net /axi_hp2_interconnect/M00_AXI /sys_ps7/S_AXI_HP2
    connect_bd_net -net /sys_cpu_clk /sys_ps7/S_AXI_HP2_ACLK
    ### ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi
    connect_bd_intf_net /axi_hp2_interconnect/S00_AXI /axi_ad9361_dac_dma/m_src_axi
    connect_bd_net -net /sys_cpu_clk /axi_ad9361_dac_dma/m_src_axi_aclk
    WARNING: [BD 5-230] No cells matched 'get_bd_cells /sys_mb'
    WARNING: [BD 5-232] No interface pins matched 'get_bd_intf_pins -filter {NAME=~ *DLMB*} -of {}'
    Slave segment </sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM> is being mapped into address space </axi_ad9361_dac_dma/m_src_axi> at <0x0000_0000 [ 1G ]>
    ### ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In13
    connect_bd_net /sys_concat_intc/In13 /axi_ad9361_adc_dma/irq
    ### ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In12
    connect_bd_net /sys_concat_intc/In12 /axi_ad9361_dac_dma/irq
    ### ad_cpu_interrupt ps-11 mb-11 axi_ad9361/gps_pps_irq
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In11
    connect_bd_net /sys_concat_intc/In11 /axi_ad9361/gps_pps_irq
    ### set_property CONFIG.MODE_1R1T 0 [get_bd_cells axi_ad9361]
    ### set_property CONFIG.CMOS_OR_LVDS_N 0  [get_bd_cells axi_ad9361]
    ### set_property CONFIG.ADC_DATAPATH_DISABLE 0  [get_bd_cells axi_ad9361]
    ### set_property CONFIG.DAC_DATAPATH_DISABLE 0  [get_bd_cells axi_ad9361]
    ### set_property CONFIG.ADC_DATAFORMAT_DISABLE 0  [get_bd_cells axi_ad9361]
    ### set_property CONFIG.ADC_DCFILTER_DISABLE 0  [get_bd_cells axi_ad9361]
    ### set_property CONFIG.ADC_IQCORRECTION_DISABLE 0  [get_bd_cells axi_ad9361]
    ### set_property CONFIG.ADC_USERPORTS_DISABLE 0 [get_bd_cells axi_ad9361]
    ### set_property CONFIG.DAC_DDS_DISABLE 0 [get_bd_cells axi_ad9361]
    ### set_property CONFIG.DAC_IQCORRECTION_DISABLE 0  [get_bd_cells axi_ad9361]
    ### set_property CONFIG.DAC_USERPORTS_DISABLE 0 [get_bd_cells axi_ad9361]
    ### set_property CONFIG.TDD_DISABLE 0 [get_bd_cells axi_ad9361]
    ### proc cfg_ad9361_interface {cmos_or_lvds} {
    ### 
    ###   if {$cmos_or_lvds eq "LVDS"} {
    ### 
    ###     set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361]
    ### 
    ###     create_bd_port -dir I rx_clk_in_p
    ###     create_bd_port -dir I rx_clk_in_n
    ###     create_bd_port -dir I rx_frame_in_p
    ###     create_bd_port -dir I rx_frame_in_n
    ###     create_bd_port -dir I -from 5 -to 0 rx_data_in_p
    ###     create_bd_port -dir I -from 5 -to 0 rx_data_in_n
    ### 
    ###     create_bd_port -dir O tx_clk_out_p
    ###     create_bd_port -dir O tx_clk_out_n
    ###     create_bd_port -dir O tx_frame_out_p
    ###     create_bd_port -dir O tx_frame_out_n
    ###     create_bd_port -dir O -from 5 -to 0 tx_data_out_p
    ###     create_bd_port -dir O -from 5 -to 0 tx_data_out_n
    ### 
    ###     ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p
    ###     ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n
    ###     ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p
    ###     ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n
    ###     ad_connect rx_data_in_p axi_ad9361/rx_data_in_p
    ###     ad_connect rx_data_in_n axi_ad9361/rx_data_in_n
    ###     ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p
    ###     ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n
    ###     ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p
    ###     ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n
    ###     ad_connect tx_data_out_p axi_ad9361/tx_data_out_p
    ###     ad_connect tx_data_out_n axi_ad9361/tx_data_out_n
    ### 
    ###     return
    ###   }
    ### 
    ###   if {$cmos_or_lvds eq "CMOS"} {
    ### 
    ###     set_property CONFIG.CMOS_OR_LVDS_N 1 [get_bd_cells axi_ad9361]
    ### 
    ###     create_bd_port -dir I rx_clk_in
    ###     create_bd_port -dir I rx_frame_in
    ###     create_bd_port -dir I -from 11 -to 0 rx_data_in
    ###     create_bd_port -dir O tx_clk_out
    ###     create_bd_port -dir O tx_frame_out
    ###     create_bd_port -dir O -from 11 -to 0 tx_data_out
    ### 
    ###     ad_connect rx_clk_in axi_ad9361/rx_clk_in
    ###     ad_connect rx_frame_in axi_ad9361/rx_frame_in
    ###     ad_connect rx_data_in axi_ad9361/rx_data_in
    ###     ad_connect tx_clk_out axi_ad9361/tx_clk_out
    ###     ad_connect tx_frame_out axi_ad9361/tx_frame_out
    ###     ad_connect tx_data_out axi_ad9361/tx_data_out
    ### 
    ###     return
    ###   }
    ### 
    ### }
    ## source ../common/ccfmc_bd.tcl
    ### create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 eth1_mdio
    ### create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 eth1_rgmii
    ### create_bd_port -dir I -type intr eth1_intn
    ### create_bd_port -dir O hdmi_out_clk
    ### create_bd_port -dir O hdmi_hsync
    ### create_bd_port -dir O hdmi_vsync
    ### create_bd_port -dir O hdmi_data_e
    ### create_bd_port -dir O -from 15 -to 0 hdmi_data
    ### create_bd_port -dir O -type clk i2s_mclk
    ### create_bd_intf_port -mode Master -vlnv analog.com:interface:i2s_rtl:1.0 i2s
    ### create_bd_port -dir O spdif
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_USE_DMA0  1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_USE_DMA1  1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_USE_DMA2  1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_GRP_MDIO_ENABLE 1
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_instance gmii_to_rgmii sys_rgmii
    ### ad_ip_parameter sys_rgmii CONFIG.SupportLevel Include_Shared_Logic_in_Core
    ### ad_ip_instance proc_sys_reset sys_rgmii_rstgen
    ### ad_ip_parameter sys_rgmii_rstgen CONFIG.C_EXT_RST_WIDTH 1
    ### ad_ip_instance axi_clkgen axi_hdmi_clkgen
    ### ad_ip_instance axi_hdmi_tx axi_hdmi_core
    ### ad_ip_parameter axi_hdmi_core CONFIG.OUT_CLK_POLARITY 1
    ### ad_ip_parameter axi_hdmi_core CONFIG.INTERFACE 16_BIT
    ### ad_ip_instance axi_dmac axi_hdmi_dma
    ### ad_ip_parameter axi_hdmi_dma CONFIG.DMA_TYPE_SRC 0
    ### ad_ip_parameter axi_hdmi_dma CONFIG.DMA_TYPE_DEST 1
    ### ad_ip_parameter axi_hdmi_dma CONFIG.CYCLIC true
    ### ad_ip_parameter axi_hdmi_dma CONFIG.SYNC_TRANSFER_START 0
    WARNING: [BD 41-721] Attempt to set value '0' on disabled parameter 'SYNC_TRANSFER_START' of cell '/axi_hdmi_dma' is ignored
    ### ad_ip_parameter axi_hdmi_dma CONFIG.AXI_SLICE_SRC 0
    ### ad_ip_parameter axi_hdmi_dma CONFIG.AXI_SLICE_DEST 0
    ### ad_ip_parameter axi_hdmi_dma CONFIG.DMA_2D_TRANSFER true
    ### ad_ip_parameter axi_hdmi_dma CONFIG.DMA_DATA_WIDTH_SRC 64
    ### ad_ip_instance clk_wiz sys_audio_clkgen
    ### ad_ip_parameter sys_audio_clkgen CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 12.288
    ### ad_ip_parameter sys_audio_clkgen CONFIG.USE_LOCKED false
    ### ad_ip_parameter sys_audio_clkgen CONFIG.USE_RESET true
    ### ad_ip_parameter sys_audio_clkgen CONFIG.RESET_TYPE ACTIVE_LOW
    ### ad_ip_parameter sys_audio_clkgen CONFIG.USE_PHASE_ALIGNMENT false
    ### ad_ip_parameter sys_audio_clkgen CONFIG.PRIM_SOURCE No_buffer
    ### ad_ip_instance axi_spdif_tx axi_spdif_tx_core
    ### ad_ip_parameter axi_spdif_tx_core CONFIG.DMA_TYPE 1
    ### ad_ip_parameter axi_spdif_tx_core CONFIG.S_AXI_ADDRESS_WIDTH 16
    ### ad_ip_instance axi_i2s_adi axi_i2s_adi
    ### ad_ip_parameter axi_i2s_adi CONFIG.DMA_TYPE 1
    ### ad_ip_parameter axi_i2s_adi CONFIG.S_AXI_ADDRESS_WIDTH 16
    ### ad_connect  sys_200m_clk axi_hdmi_clkgen/clk
    connect_bd_net -net /sys_200m_clk /axi_hdmi_clkgen/clk
    ### ad_connect  sys_ps7/MDIO_ETHERNET_1 sys_rgmii/MDIO_GEM
    connect_bd_intf_net /sys_ps7/MDIO_ETHERNET_1 /sys_rgmii/MDIO_GEM
    ### ad_connect  sys_ps7/GMII_ETHERNET_1 sys_rgmii/GMII
    connect_bd_intf_net /sys_ps7/GMII_ETHERNET_1 /sys_rgmii/GMII
    ### ad_connect  sys_rgmii/MDIO_PHY eth1_mdio
    connect_bd_intf_net /sys_rgmii/MDIO_PHY /eth1_mdio
    ### ad_connect  sys_rgmii/RGMII eth1_rgmii
    connect_bd_intf_net /sys_rgmii/RGMII /eth1_rgmii
    ### ad_connect  sys_ps7/ENET1_EXT_INTIN eth1_intn
    connect_bd_net /sys_ps7/ENET1_EXT_INTIN /eth1_intn
    ### ad_connect  sys_200m_clk sys_rgmii_rstgen/slowest_sync_clk
    connect_bd_net -net /sys_200m_clk /sys_rgmii_rstgen/slowest_sync_clk
    ### ad_connect  sys_200m_clk sys_rgmii/clkin
    connect_bd_net -net /sys_200m_clk /sys_rgmii/clkin
    ### ad_connect  sys_rgmii_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
    connect_bd_net /sys_rgmii_rstgen/ext_reset_in /sys_ps7/FCLK_RESET0_N
    ### ad_connect  sys_rgmii_rstgen/peripheral_reset sys_rgmii/tx_reset
    connect_bd_net /sys_rgmii_rstgen/peripheral_reset /sys_rgmii/tx_reset
    ### ad_connect  sys_rgmii_rstgen/peripheral_reset sys_rgmii/rx_reset
    connect_bd_net /sys_rgmii_rstgen/peripheral_reset /sys_rgmii/rx_reset
    ### ad_connect  sys_cpu_clk axi_hdmi_core/vdma_clk
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_core/vdma_clk
    ### ad_connect  axi_hdmi_core/hdmi_clk axi_hdmi_clkgen/clk_0
    connect_bd_net /axi_hdmi_core/hdmi_clk /axi_hdmi_clkgen/clk_0
    ### ad_connect  axi_hdmi_core/hdmi_out_clk hdmi_out_clk
    connect_bd_net /axi_hdmi_core/hdmi_out_clk /hdmi_out_clk
    ### ad_connect  axi_hdmi_core/hdmi_16_hsync hdmi_hsync
    connect_bd_net /axi_hdmi_core/hdmi_16_hsync /hdmi_hsync
    ### ad_connect  axi_hdmi_core/hdmi_16_vsync hdmi_vsync
    connect_bd_net /axi_hdmi_core/hdmi_16_vsync /hdmi_vsync
    ### ad_connect  axi_hdmi_core/hdmi_16_data_e hdmi_data_e
    connect_bd_net /axi_hdmi_core/hdmi_16_data_e /hdmi_data_e
    ### ad_connect  axi_hdmi_core/hdmi_16_data hdmi_data
    connect_bd_net /axi_hdmi_core/hdmi_16_data /hdmi_data
    ### ad_connect  axi_hdmi_dma/m_axis axi_hdmi_core/s_axis
    connect_bd_intf_net /axi_hdmi_dma/m_axis /axi_hdmi_core/s_axis
    ### ad_connect  sys_cpu_resetn axi_hdmi_dma/s_axi_aresetn
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_dma/s_axi_aresetn
    ### ad_connect  sys_cpu_resetn axi_hdmi_dma/m_src_axi_aresetn
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_dma/m_src_axi_aresetn
    ### ad_connect  sys_cpu_clk axi_hdmi_dma/s_axi_aclk
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_dma/s_axi_aclk
    ### ad_connect  sys_cpu_clk axi_hdmi_dma/m_src_axi_aclk
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_dma/m_src_axi_aclk
    ### ad_connect  sys_cpu_clk axi_hdmi_dma/m_axis_aclk
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_dma/m_axis_aclk
    ### ad_connect  sys_cpu_clk axi_spdif_tx_core/DMA_REQ_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_spdif_tx_core/dma_req_aclk
    ### ad_connect  sys_cpu_clk sys_ps7/DMA0_ACLK
    connect_bd_net -net /sys_cpu_clk /sys_ps7/DMA0_ACLK
    ### ad_connect  sys_cpu_resetn axi_spdif_tx_core/DMA_REQ_RSTN
    connect_bd_net -net /sys_cpu_resetn /axi_spdif_tx_core/dma_req_rstn
    ### ad_connect  sys_ps7/DMA0_REQ axi_spdif_tx_core/DMA_REQ
    connect_bd_intf_net /sys_ps7/DMA0_REQ /axi_spdif_tx_core/dma_req
    ### ad_connect  sys_ps7/DMA0_ACK axi_spdif_tx_core/DMA_ACK
    connect_bd_intf_net /sys_ps7/DMA0_ACK /axi_spdif_tx_core/dma_ack
    ### ad_connect  sys_200m_clk sys_audio_clkgen/clk_in1
    connect_bd_net -net /sys_200m_clk /sys_audio_clkgen/clk_in1
    ### ad_connect  sys_cpu_resetn sys_audio_clkgen/resetn
    connect_bd_net -net /sys_cpu_resetn /sys_audio_clkgen/resetn
    ### ad_connect  sys_audio_clkgen/clk_out1 axi_spdif_tx_core/spdif_data_clk
    connect_bd_net /sys_audio_clkgen/clk_out1 /axi_spdif_tx_core/spdif_data_clk
    ### ad_connect  spdif axi_spdif_tx_core/spdif_tx_o
    connect_bd_net /spdif /axi_spdif_tx_core/spdif_tx_o
    ### ad_connect  sys_cpu_clk axi_i2s_adi/DMA_REQ_RX_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_i2s_adi/dma_req_rx_aclk
    ### ad_connect  sys_cpu_clk axi_i2s_adi/DMA_REQ_TX_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_i2s_adi/dma_req_tx_aclk
    ### ad_connect  sys_cpu_clk sys_ps7/DMA1_ACLK
    connect_bd_net -net /sys_cpu_clk /sys_ps7/DMA1_ACLK
    ### ad_connect  sys_cpu_clk sys_ps7/DMA2_ACLK
    connect_bd_net -net /sys_cpu_clk /sys_ps7/DMA2_ACLK
    ### ad_connect  sys_cpu_resetn axi_i2s_adi/DMA_REQ_RX_RSTN
    connect_bd_net -net /sys_cpu_resetn /axi_i2s_adi/dma_req_rx_rstn
    ### ad_connect  sys_cpu_resetn axi_i2s_adi/DMA_REQ_TX_RSTN
    connect_bd_net -net /sys_cpu_resetn /axi_i2s_adi/dma_req_tx_rstn
    ### ad_connect  sys_ps7/DMA1_REQ axi_i2s_adi/DMA_REQ_TX
    connect_bd_intf_net /sys_ps7/DMA1_REQ /axi_i2s_adi/dma_req_tx
    ### ad_connect  sys_ps7/DMA1_ACK axi_i2s_adi/DMA_ACK_TX
    connect_bd_intf_net /sys_ps7/DMA1_ACK /axi_i2s_adi/dma_ack_tx
    ### ad_connect  sys_ps7/DMA2_REQ axi_i2s_adi/DMA_REQ_RX
    connect_bd_intf_net /sys_ps7/DMA2_REQ /axi_i2s_adi/dma_req_rx
    ### ad_connect  sys_ps7/DMA2_ACK axi_i2s_adi/DMA_ACK_RX
    connect_bd_intf_net /sys_ps7/DMA2_ACK /axi_i2s_adi/dma_ack_rx
    ### ad_connect  sys_audio_clkgen/clk_out1 i2s_mclk
    connect_bd_net /sys_audio_clkgen/clk_out1 /i2s_mclk
    ### ad_connect  sys_audio_clkgen/clk_out1 axi_i2s_adi/DATA_CLK_I
    connect_bd_net /sys_audio_clkgen/clk_out1 /axi_i2s_adi/data_clk_i
    ### ad_connect  i2s axi_i2s_adi/I2S
    connect_bd_intf_net /i2s /axi_i2s_adi/i2s
    ### ad_cpu_interrupt ps-15 mb-15 axi_hdmi_dma/irq
    disconnect_bd_net /GND_1_dout /sys_concat_intc/In15
    connect_bd_net /sys_concat_intc/In15 /axi_hdmi_dma/irq
    ### ad_cpu_interconnect 0x79000000 axi_hdmi_clkgen
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M05_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_clkgen/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M05_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_clkgen/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M05_AXI /axi_hdmi_clkgen/s_axi
    ### ad_cpu_interconnect 0x43000000 axi_hdmi_dma
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M06_ACLK
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M06_ARESETN
    connect_bd_intf_net /axi_cpu_interconnect/M06_AXI /axi_hdmi_dma/s_axi
    ### ad_cpu_interconnect 0x70e00000 axi_hdmi_core
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M07_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_hdmi_core/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M07_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_hdmi_core/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M07_AXI /axi_hdmi_core/s_axi
    ### ad_cpu_interconnect 0x75c00000 axi_spdif_tx_core
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M08_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_spdif_tx_core/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M08_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_spdif_tx_core/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M08_AXI /axi_spdif_tx_core/s_axi
    ### ad_cpu_interconnect 0x77600000 axi_i2s_adi
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M09_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_i2s_adi/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M09_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_i2s_adi/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M09_AXI /axi_i2s_adi/s_axi
    ### ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    connect_bd_net -net /sys_cpu_resetn /axi_hp0_interconnect/aresetn
    connect_bd_net -net /sys_cpu_clk /axi_hp0_interconnect/aclk
    connect_bd_intf_net /axi_hp0_interconnect/M00_AXI /sys_ps7/S_AXI_HP0
    connect_bd_net -net /sys_cpu_clk /sys_ps7/S_AXI_HP0_ACLK
    ### ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/m_src_axi
    connect_bd_intf_net /axi_hp0_interconnect/S00_AXI /axi_hdmi_dma/m_src_axi
    WARNING: [BD 5-230] No cells matched 'get_bd_cells /sys_mb'
    WARNING: [BD 5-232] No interface pins matched 'get_bd_intf_pins -filter {NAME=~ *DLMB*} -of {}'
    Slave segment </sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM> is being mapped into address space </axi_hdmi_dma/m_src_axi> at <0x0000_0000 [ 1G ]>
    ### ad_ip_instance axi_xcvrlb axi_pz_xcvrlb
    ### ad_ip_parameter axi_pz_xcvrlb CONFIG.NUM_OF_LANES 2
    ### create_bd_port -dir I gt_ref_clk_0
    ### create_bd_port -dir I -from 1 -to 0 gt_rx_p
    ### create_bd_port -dir I -from 1 -to 0 gt_rx_n
    ### create_bd_port -dir O -from 1 -to 0 gt_tx_p
    ### create_bd_port -dir O -from 1 -to 0 gt_tx_n
    ### ad_cpu_interconnect 0x44A60000 axi_pz_xcvrlb
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M10_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_pz_xcvrlb/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M10_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_pz_xcvrlb/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M10_AXI /axi_pz_xcvrlb/s_axi
    ### ad_connect  axi_pz_xcvrlb/ref_clk gt_ref_clk_0
    connect_bd_net /axi_pz_xcvrlb/ref_clk /gt_ref_clk_0
    ### ad_connect  axi_pz_xcvrlb/rx_p gt_rx_p
    connect_bd_net /axi_pz_xcvrlb/rx_p /gt_rx_p
    ### ad_connect  axi_pz_xcvrlb/rx_n gt_rx_n
    connect_bd_net /axi_pz_xcvrlb/rx_n /gt_rx_n
    ### ad_connect  axi_pz_xcvrlb/tx_p gt_tx_p
    connect_bd_net /axi_pz_xcvrlb/tx_p /gt_tx_p
    ### ad_connect  axi_pz_xcvrlb/tx_n gt_tx_n
    connect_bd_net /axi_pz_xcvrlb/tx_n /gt_tx_n
    ### ad_ip_instance axi_gpreg axi_gpreg
    ### ad_ip_parameter axi_gpreg CONFIG.NUM_OF_CLK_MONS 3
    ### ad_ip_parameter axi_gpreg CONFIG.NUM_OF_IO 2
    ### ad_ip_parameter axi_gpreg CONFIG.BUF_ENABLE_0 1
    ### ad_ip_parameter axi_gpreg CONFIG.BUF_ENABLE_1 1
    ### ad_ip_parameter axi_gpreg CONFIG.BUF_ENABLE_2 1
    ### create_bd_port -dir I -from 31 -to 0 gp_in_0
    ### create_bd_port -dir I -from 31 -to 0 gp_in_1
    ### create_bd_port -dir O -from 31 -to 0 gp_out_0
    ### create_bd_port -dir O -from 31 -to 0 gp_out_1
    ### create_bd_port -dir I clk_0
    ### create_bd_port -dir I clk_1
    ### create_bd_port -dir I gt_ref_clk_1
    ### ad_connect  clk_0 axi_gpreg/d_clk_0
    connect_bd_net /clk_0 /axi_gpreg/d_clk_0
    ### ad_connect  clk_1 axi_gpreg/d_clk_1
    connect_bd_net /clk_1 /axi_gpreg/d_clk_1
    ### ad_connect  gt_ref_clk_1 axi_gpreg/d_clk_2
    connect_bd_net /gt_ref_clk_1 /axi_gpreg/d_clk_2
    ### ad_connect  gp_in_0 axi_gpreg/up_gp_in_0
    connect_bd_net /gp_in_0 /axi_gpreg/up_gp_in_0
    ### ad_connect  gp_in_1 axi_gpreg/up_gp_in_1
    connect_bd_net /gp_in_1 /axi_gpreg/up_gp_in_1
    ### ad_connect  gp_out_0 axi_gpreg/up_gp_out_0
    connect_bd_net /gp_out_0 /axi_gpreg/up_gp_out_0
    ### ad_connect  gp_out_1 axi_gpreg/up_gp_out_1
    connect_bd_net /gp_out_1 /axi_gpreg/up_gp_out_1
    ### ad_cpu_interconnect 0x41200000 axi_gpreg
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M11_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_gpreg/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M11_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_gpreg/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M11_AXI /axi_gpreg/s_axi
    WARNING: [BD 5-230] No cells matched 'get_bd_cells ila_adc'
    ### delete_bd_objs [get_bd_cells ila_adc]
    ## cfg_ad9361_interface LVDS
    connect_bd_net /rx_clk_in_p /axi_ad9361/rx_clk_in_p
    connect_bd_net /rx_clk_in_n /axi_ad9361/rx_clk_in_n
    connect_bd_net /rx_frame_in_p /axi_ad9361/rx_frame_in_p
    connect_bd_net /rx_frame_in_n /axi_ad9361/rx_frame_in_n
    connect_bd_net /rx_data_in_p /axi_ad9361/rx_data_in_p
    connect_bd_net /rx_data_in_n /axi_ad9361/rx_data_in_n
    connect_bd_net /tx_clk_out_p /axi_ad9361/tx_clk_out_p
    connect_bd_net /tx_clk_out_n /axi_ad9361/tx_clk_out_n
    connect_bd_net /tx_frame_out_p /axi_ad9361/tx_frame_out_p
    connect_bd_net /tx_frame_out_n /axi_ad9361/tx_frame_out_n
    connect_bd_net /tx_data_out_p /axi_ad9361/tx_data_out_p
    connect_bd_net /tx_data_out_n /axi_ad9361/tx_data_out_n
    ## create_bd_port -dir O sys_cpu_clk_out
    ## ad_connect  sys_cpu_clk sys_cpu_clk_out
    connect_bd_net -net /sys_cpu_clk /sys_cpu_clk_out
    ## ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 29
    ## ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
    ## ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
    ## ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
    ## sysid_gen_sys_init_file
    Wrote  : </home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/system.bd> 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [#UNDEF] When using EMIO pins for SPI_0 tie SSIN High in the PL bitstream
    WARNING: [#UNDEF] When using EMIO pins for SPI_1 tie SSIN High in the PL bitstream
    WARNING: [BD 41-927] Following properties on pin /axi_sysid_0/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /rom_sys_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/delay_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK1 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/l_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_tdd_sync/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_divclk/clk_out have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	POLARITY=ACTIVE_HIGH 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_pack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/din_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_rst have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	POLARITY=ACTIVE_HIGH 
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_ad9361_0_l_clk 
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_dac_upack/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_util_ad9361_divclk_0_clk_out 
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_hdmi_clkgen_0_clk_0 
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/hdmi_out_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_axi_hdmi_core_0_hdmi_out_clk 
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/vdma_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_hdmi_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/spdif_data_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1 
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_spdif_tx_core/dma_req_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/data_clk_i have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_audio_clkgen_0_clk_out1 
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_tx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/dma_req_rx_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_i2s_adi/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_pz_xcvrlb/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    WARNING: [BD 41-927] Following properties on pin /axi_gpreg/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    	CLK_DOMAIN=system_sys_ps7_0_FCLK_CLK0 
    validate_bd_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1874.375 ; gain = 79.188 ; free physical = 120 ; free virtual = 2653
    INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run.
    Wrote  : </home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/system.bd> 
    VHDL Output written to : /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v
    VHDL Output written to : /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/sim/system.v
    VHDL Output written to : /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/hdl/system_wrapper.v
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_ps7 .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_iic_main .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_concat_intc .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_rstgen .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_logic_inv .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_sysid_0 .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block rom_sys_0 .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block GND_1 .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/xbar .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361 .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_tdd_sync .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk_sel_concat .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk_sel .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_divclk_reset .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_adc_fifo .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_adc_pack .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361_adc_dma .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361_dac_fifo .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_dac_upack .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361_dac_dma .
    Exporting to file /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/hw_handoff/system_axi_hp1_interconnect_0.hwh
    Generated Block Design Tcl file /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/hw_handoff/system_axi_hp1_interconnect_0_bd.tcl
    Generated Hardware Definition File /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/synth/system_axi_hp1_interconnect_0.hwdef
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hp1_interconnect .
    Exporting to file /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/hw_handoff/system_axi_hp2_interconnect_0.hwh
    Generated Block Design Tcl file /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/hw_handoff/system_axi_hp2_interconnect_0_bd.tcl
    Generated Hardware Definition File /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/synth/system_axi_hp2_interconnect_0.hwdef
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hp2_interconnect .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_rgmii .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_rgmii_rstgen .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hdmi_clkgen .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hdmi_core .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hdmi_dma .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_audio_clkgen .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_spdif_tx_core .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_i2s_adi .
    Exporting to file /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/hw_handoff/system_axi_hp0_interconnect_0.hwh
    Generated Block Design Tcl file /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/hw_handoff/system_axi_hp0_interconnect_0_bd.tcl
    Generated Hardware Definition File /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/synth/system_axi_hp0_interconnect_0.hwdef
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hp0_interconnect .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_pz_xcvrlb .
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpreg .
    WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_auto_pc_0/system_auto_pc_0_ooc.xdc'
    INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/s00_couplers/auto_pc .
    Exporting to file /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/hw_handoff/system.hwh
    Generated Block Design Tcl file /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl
    Generated Hardware Definition File /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.hwdef
    generate_target: Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2159.312 ; gain = 284.938 ; free physical = 112 ; free virtual = 2579
    # adi_project_files adrv9361z7035_ccfmc_lvds [list \
    #   "$ad_hdl_dir/library/common/ad_iobuf.v" \
    #   "$ad_hdl_dir/library/common/ad_adl5904_rst.v" \
    #   "../common/adrv9361z7035_constr.xdc" \
    #   "../common/adrv9361z7035_constr_lvds.xdc" \
    #   "../common/ccfmc_constr.xdc" \
    #   "system_top.v" ]
    # adi_project_run adrv9361z7035_ccfmc_lvds
    [Wed Oct 27 11:57:56 2021] Launched synth_1...
    Run output will be captured here: /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.runs/synth_1/runme.log
    [Wed Oct 27 11:57:56 2021] Waiting for synth_1 to finish...
    
    *** Running vivado
        with args -log system_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_top.tcl
    
    
    ****** Vivado v2019.1 (64-bit)
      **** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
      **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
        ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
    
    source system_top.tcl -notrace
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nicole/adi/hdl/library'.
    WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/nicole/adi/ghdl/library'; Can't find the specified path.
    If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
    Command: synth_design -top system_top -part xc7z035ifbg676-2L
    Starting synth_design
    Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035i'
    INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035i'
    INFO: [Device 21-403] Loading part xc7z035ifbg676-2L
    INFO: Launching helper process for spawning children vivado processes
    INFO: Helper process launched with PID 7238 
    ---------------------------------------------------------------------------------
    Starting RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1876.051 ; gain = 159.719 ; free physical = 101 ; free virtual = 1824
    ---------------------------------------------------------------------------------
    WARNING: [Synth 8-2048] function gpo_bit_used does not always return a value [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:1139]
    INFO: [Synth 8-6157] synthesizing module 'system_top' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/system_top.v:38]
    INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:32871]
    	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
    	Parameter DIFF_TERM bound to: FALSE - type: string 
    	Parameter DQS_BIAS bound to: FALSE - type: string 
    	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
    	Parameter IBUF_LOW_PWR bound to: TRUE - type: string 
    	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
    	Parameter IOSTANDARD bound to: DEFAULT - type: string 
    INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (1#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:32871]
    INFO: [Synth 8-6157] synthesizing module 'IBUFDS_GTE2' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:33009]
    	Parameter CLKCM_CFG bound to: TRUE - type: string 
    	Parameter CLKRCV_TRST bound to: TRUE - type: string 
    	Parameter CLKSWING_CFG bound to: 2'b11 
    INFO: [Synth 8-6155] done synthesizing module 'IBUFDS_GTE2' (2#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:33009]
    INFO: [Synth 8-6157] synthesizing module 'ad_iobuf' [/home/nicole/adi/hdl/library/common/ad_iobuf.v:38]
    	Parameter DATA_WIDTH bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_iobuf' (3#1) [/home/nicole/adi/hdl/library/common/ad_iobuf.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_iobuf__parameterized0' [/home/nicole/adi/hdl/library/common/ad_iobuf.v:38]
    	Parameter DATA_WIDTH bound to: 21 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_iobuf__parameterized0' (3#1) [/home/nicole/adi/hdl/library/common/ad_iobuf.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_iobuf__parameterized1' [/home/nicole/adi/hdl/library/common/ad_iobuf.v:38]
    	Parameter DATA_WIDTH bound to: 5 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_iobuf__parameterized1' (3#1) [/home/nicole/adi/hdl/library/common/ad_iobuf.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_iobuf__parameterized2' [/home/nicole/adi/hdl/library/common/ad_iobuf.v:38]
    	Parameter DATA_WIDTH bound to: 2 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_iobuf__parameterized2' (3#1) [/home/nicole/adi/hdl/library/common/ad_iobuf.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_iobuf__parameterized3' [/home/nicole/adi/hdl/library/common/ad_iobuf.v:38]
    	Parameter DATA_WIDTH bound to: 15 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_iobuf__parameterized3' (3#1) [/home/nicole/adi/hdl/library/common/ad_iobuf.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_adl5904_rst' [/home/nicole/adi/hdl/library/common/ad_adl5904_rst.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'ad_adl5904_rst' (4#1) [/home/nicole/adi/hdl/library/common/ad_adl5904_rst.v:38]
    INFO: [Synth 8-6157] synthesizing module 'system_wrapper' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/imports/hdl/system_wrapper.v:12]
    INFO: [Synth 8-6157] synthesizing module 'IOBUF' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:36115]
    	Parameter DRIVE bound to: 12 - type: integer 
    	Parameter IBUF_LOW_PWR bound to: TRUE - type: string 
    	Parameter IOSTANDARD bound to: DEFAULT - type: string 
    	Parameter SLEW bound to: SLOW - type: string 
    INFO: [Synth 8-6155] done synthesizing module 'IOBUF' (5#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:36115]
    INFO: [Synth 8-6157] synthesizing module 'system' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:2056]
    INFO: [Synth 8-6157] synthesizing module 'system_GND_1_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_GND_1_0/synth/system_GND_1_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'xlconstant_v1_1_6_xlconstant' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66e7/hdl/xlconstant_v1_1_vl_rfs.v:23]
    	Parameter CONST_VAL bound to: 0 - type: integer 
    	Parameter CONST_WIDTH bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'xlconstant_v1_1_6_xlconstant' (6#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66e7/hdl/xlconstant_v1_1_vl_rfs.v:23]
    INFO: [Synth 8-6155] done synthesizing module 'system_GND_1_0' (7#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_GND_1_0/synth/system_GND_1_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'system_axi_ad9361_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/synth/system_axi_ad9361_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'axi_ad9361' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361.v:38]
    	Parameter ID bound to: 0 - type: integer 
    	Parameter MODE_1R1T bound to: 0 - type: integer 
    	Parameter FPGA_TECHNOLOGY bound to: 1 - type: integer 
    	Parameter FPGA_FAMILY bound to: 4 - type: integer 
    	Parameter SPEED_GRADE bound to: 21 - type: integer 
    	Parameter DEV_PACKAGE bound to: 4 - type: integer 
    	Parameter TDD_DISABLE bound to: 0 - type: integer 
    	Parameter PPS_RECEIVER_ENABLE bound to: 0 - type: integer 
    	Parameter CMOS_OR_LVDS_N bound to: 0 - type: integer 
    	Parameter ADC_INIT_DELAY bound to: 29 - type: integer 
    	Parameter ADC_DATAPATH_DISABLE bound to: 0 - type: integer 
    	Parameter ADC_USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter ADC_DATAFORMAT_DISABLE bound to: 0 - type: integer 
    	Parameter ADC_DCFILTER_DISABLE bound to: 0 - type: integer 
    	Parameter ADC_IQCORRECTION_DISABLE bound to: 0 - type: integer 
    	Parameter DAC_INIT_DELAY bound to: 0 - type: integer 
    	Parameter DAC_CLK_EDGE_SEL bound to: 0 - type: integer 
    	Parameter DAC_IODELAY_ENABLE bound to: 1 - type: integer 
    	Parameter DAC_DATAPATH_DISABLE bound to: 0 - type: integer 
    	Parameter DAC_DDS_DISABLE bound to: 0 - type: integer 
    	Parameter DAC_DDS_TYPE bound to: 1 - type: integer 
    	Parameter DAC_DDS_CORDIC_DW bound to: 14 - type: integer 
    	Parameter DAC_DDS_CORDIC_PHASE_DW bound to: 13 - type: integer 
    	Parameter DAC_USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter DAC_IQCORRECTION_DISABLE bound to: 0 - type: integer 
    	Parameter IO_DELAY_GROUP bound to: dev_if_delay_group - type: string 
    	Parameter MIMO_ENABLE bound to: 0 - type: integer 
    	Parameter USE_SSI_CLK bound to: 1 - type: integer 
    	Parameter DELAY_REFCLK_FREQUENCY bound to: 200 - type: integer 
    	Parameter RX_NODPA bound to: 0 - type: integer 
    	Parameter ADC_USERPORTS_DISABLE_INT bound to: 0 - type: integer 
    	Parameter ADC_DATAFORMAT_DISABLE_INT bound to: 0 - type: integer 
    	Parameter ADC_DCFILTER_DISABLE_INT bound to: 0 - type: integer 
    	Parameter ADC_IQCORRECTION_DISABLE_INT bound to: 0 - type: integer 
    	Parameter DAC_DDS_DISABLE_INT bound to: 0 - type: integer 
    	Parameter DAC_USERPORTS_DISABLE_INT bound to: 0 - type: integer 
    	Parameter DAC_DELAYCNTRL_DISABLE_INT bound to: 0 - type: integer 
    	Parameter DAC_IQCORRECTION_DISABLE_INT bound to: 0 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_ad9361_lvds_if' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/xilinx/axi_ad9361_lvds_if.v:38]
    	Parameter FPGA_TECHNOLOGY bound to: 1 - type: integer 
    	Parameter DAC_IODELAY_ENABLE bound to: 1 - type: integer 
    	Parameter IO_DELAY_GROUP bound to: dev_if_delay_group - type: string 
    	Parameter CLK_DESKEW bound to: 0 - type: integer 
    	Parameter USE_SSI_CLK bound to: 1 - type: integer 
    	Parameter DELAY_REFCLK_FREQUENCY bound to: 200 - type: integer 
    	Parameter RX_NODPA bound to: 0 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'ad_data_in' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_data_in.v:38]
    	Parameter SINGLE_ENDED bound to: 0 - type: integer 
    	Parameter FPGA_TECHNOLOGY bound to: 1 - type: integer 
    	Parameter IODELAY_ENABLE bound to: 1 - type: integer 
    	Parameter IODELAY_CTRL bound to: 0 - type: integer 
    	Parameter IODELAY_GROUP bound to: dev_if_delay_group - type: string 
    	Parameter REFCLK_FREQUENCY bound to: 200 - type: integer 
    	Parameter NONE bound to: -1 - type: integer 
    	Parameter SEVEN_SERIES bound to: 1 - type: integer 
    	Parameter ULTRASCALE bound to: 2 - type: integer 
    	Parameter ULTRASCALE_PLUS bound to: 3 - type: integer 
    	Parameter IODELAY_CTRL_ENABLED bound to: 0 - type: integer 
    	Parameter IODELAY_CTRL_SIM_DEVICE bound to: 7SERIES - type: string 
    	Parameter IODELAY_FPGA_TECHNOLOGY bound to: 1 - type: integer 
    	Parameter IODELAY_SIM_DEVICE bound to: 7SERIES - type: string 
    INFO: [Synth 8-6157] synthesizing module 'IDELAYE2' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:34946]
    	Parameter CINVCTRL_SEL bound to: FALSE - type: string 
    	Parameter DELAY_SRC bound to: IDATAIN - type: string 
    	Parameter HIGH_PERFORMANCE_MODE bound to: FALSE - type: string 
    	Parameter IDELAY_TYPE bound to: VAR_LOAD - type: string 
    	Parameter IDELAY_VALUE bound to: 0 - type: integer 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_DATAIN_INVERTED bound to: 1'b0 
    	Parameter IS_IDATAIN_INVERTED bound to: 1'b0 
    	Parameter PIPE_SEL bound to: FALSE - type: string 
    	Parameter REFCLK_FREQUENCY bound to: 200.000000 - type: float 
    	Parameter SIGNAL_PATTERN bound to: DATA - type: string 
    	Parameter SIM_DELAY_D bound to: 0 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'IDELAYE2' (8#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:34946]
    INFO: [Synth 8-6157] synthesizing module 'IDDR' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:34811]
    	Parameter DDR_CLK_EDGE bound to: SAME_EDGE - type: string 
    	Parameter INIT_Q1 bound to: 1'b0 
    	Parameter INIT_Q2 bound to: 1'b0 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter SRTYPE bound to: SYNC - type: string 
    INFO: [Synth 8-6155] done synthesizing module 'IDDR' (9#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:34811]
    INFO: [Synth 8-6155] done synthesizing module 'ad_data_in' (10#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_data_in.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_data_out' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_data_out.v:38]
    	Parameter FPGA_TECHNOLOGY bound to: 1 - type: integer 
    	Parameter SINGLE_ENDED bound to: 0 - type: integer 
    	Parameter IODELAY_ENABLE bound to: 1 - type: integer 
    	Parameter IODELAY_CTRL bound to: 0 - type: integer 
    	Parameter IODELAY_GROUP bound to: dev_if_delay_group - type: string 
    	Parameter REFCLK_FREQUENCY bound to: 200 - type: integer 
    	Parameter NONE bound to: -1 - type: integer 
    	Parameter SEVEN_SERIES bound to: 1 - type: integer 
    	Parameter ULTRASCALE bound to: 2 - type: integer 
    	Parameter ULTRASCALE_PLUS bound to: 3 - type: integer 
    	Parameter IODELAY_CTRL_ENABLED bound to: 0 - type: integer 
    	Parameter IODELAY_CTRL_SIM_DEVICE bound to: 7SERIES - type: string 
    	Parameter IODELAY_FPGA_TECHNOLOGY bound to: 1 - type: integer 
    	Parameter IODELAY_SIM_DEVICE bound to: 7SERIES - type: string 
    INFO: [Synth 8-6157] synthesizing module 'ODDR' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:49468]
    	Parameter DDR_CLK_EDGE bound to: SAME_EDGE - type: string 
    	Parameter INIT bound to: 1'b0 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D1_INVERTED bound to: 1'b0 
    	Parameter IS_D2_INVERTED bound to: 1'b0 
    	Parameter SRTYPE bound to: SYNC - type: string 
    INFO: [Synth 8-6155] done synthesizing module 'ODDR' (11#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:49468]
    INFO: [Synth 8-6157] synthesizing module 'ODELAYE2' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:49540]
    	Parameter CINVCTRL_SEL bound to: FALSE - type: string 
    	Parameter DELAY_SRC bound to: ODATAIN - type: string 
    	Parameter HIGH_PERFORMANCE_MODE bound to: FALSE - type: string 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_ODATAIN_INVERTED bound to: 1'b0 
    	Parameter ODELAY_TYPE bound to: VAR_LOAD - type: string 
    	Parameter ODELAY_VALUE bound to: 0 - type: integer 
    	Parameter PIPE_SEL bound to: FALSE - type: string 
    	Parameter REFCLK_FREQUENCY bound to: 200.000000 - type: float 
    	Parameter SIGNAL_PATTERN bound to: DATA - type: string 
    	Parameter SIM_DELAY_D bound to: 0 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ODELAYE2' (12#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:49540]
    INFO: [Synth 8-6157] synthesizing module 'OBUFDS' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:46012]
    	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
    	Parameter IOSTANDARD bound to: DEFAULT - type: string 
    	Parameter SLEW bound to: SLOW - type: string 
    INFO: [Synth 8-6155] done synthesizing module 'OBUFDS' (13#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:46012]
    INFO: [Synth 8-6155] done synthesizing module 'ad_data_out' (14#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_data_out.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_data_clk' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_data_clk.v:38]
    	Parameter SINGLE_ENDED bound to: 0 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'IBUFGDS' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:33335]
    	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
    	Parameter DIFF_TERM bound to: FALSE - type: string 
    	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
    	Parameter IBUF_LOW_PWR bound to: TRUE - type: string 
    	Parameter IOSTANDARD bound to: DEFAULT - type: string 
    INFO: [Synth 8-6155] done synthesizing module 'IBUFGDS' (15#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:33335]
    INFO: [Synth 8-6157] synthesizing module 'BUFG' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1075]
    INFO: [Synth 8-6155] done synthesizing module 'BUFG' (16#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1075]
    INFO: [Synth 8-6155] done synthesizing module 'ad_data_clk' (17#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_data_clk.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_data_in__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_data_in.v:38]
    	Parameter SINGLE_ENDED bound to: 0 - type: integer 
    	Parameter FPGA_TECHNOLOGY bound to: 1 - type: integer 
    	Parameter IODELAY_ENABLE bound to: 1 - type: integer 
    	Parameter IODELAY_CTRL bound to: 1 - type: integer 
    	Parameter IODELAY_GROUP bound to: dev_if_delay_group - type: string 
    	Parameter REFCLK_FREQUENCY bound to: 200 - type: integer 
    	Parameter NONE bound to: -1 - type: integer 
    	Parameter SEVEN_SERIES bound to: 1 - type: integer 
    	Parameter ULTRASCALE bound to: 2 - type: integer 
    	Parameter ULTRASCALE_PLUS bound to: 3 - type: integer 
    	Parameter IODELAY_CTRL_ENABLED bound to: 1 - type: integer 
    	Parameter IODELAY_CTRL_SIM_DEVICE bound to: 7SERIES - type: string 
    	Parameter IODELAY_FPGA_TECHNOLOGY bound to: 1 - type: integer 
    	Parameter IODELAY_SIM_DEVICE bound to: 7SERIES - type: string 
    INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:34933]
    	Parameter SIM_DEVICE bound to: 7SERIES - type: string 
    INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (18#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:34933]
    INFO: [Synth 8-6155] done synthesizing module 'ad_data_in__parameterized0' (18#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_data_in.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_data_out__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_data_out.v:38]
    	Parameter FPGA_TECHNOLOGY bound to: 1 - type: integer 
    	Parameter SINGLE_ENDED bound to: 1 - type: integer 
    	Parameter IODELAY_ENABLE bound to: 1 - type: integer 
    	Parameter IODELAY_CTRL bound to: 0 - type: integer 
    	Parameter IODELAY_GROUP bound to: dev_if_delay_group - type: string 
    	Parameter REFCLK_FREQUENCY bound to: 200 - type: integer 
    	Parameter NONE bound to: -1 - type: integer 
    	Parameter SEVEN_SERIES bound to: 1 - type: integer 
    	Parameter ULTRASCALE bound to: 2 - type: integer 
    	Parameter ULTRASCALE_PLUS bound to: 3 - type: integer 
    	Parameter IODELAY_CTRL_ENABLED bound to: 0 - type: integer 
    	Parameter IODELAY_CTRL_SIM_DEVICE bound to: 7SERIES - type: string 
    	Parameter IODELAY_FPGA_TECHNOLOGY bound to: 1 - type: integer 
    	Parameter IODELAY_SIM_DEVICE bound to: 7SERIES - type: string 
    INFO: [Synth 8-6157] synthesizing module 'OBUF' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:45998]
    	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
    	Parameter DRIVE bound to: 12 - type: integer 
    	Parameter IOSTANDARD bound to: DEFAULT - type: string 
    	Parameter SLEW bound to: SLOW - type: string 
    INFO: [Synth 8-6155] done synthesizing module 'OBUF' (19#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:45998]
    INFO: [Synth 8-6155] done synthesizing module 'ad_data_out__parameterized0' (19#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_data_out.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_ad9361_lvds_if' (20#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/xilinx/axi_ad9361_lvds_if.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_ad9361_tdd_if' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_tdd_if.v:38]
    	Parameter LEVEL_OR_PULSE_N bound to: 1 - type: integer 
    	Parameter PULSE_MODE bound to: 0 - type: integer 
    	Parameter LEVEL_MODE bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_ad9361_tdd_if' (21#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_tdd_if.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_ad9361_tdd' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_tdd.v:38]
    INFO: [Synth 8-6157] synthesizing module 'up_tdd_cntrl' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_tdd_cntrl.v:37]
    	Parameter ID bound to: 0 - type: integer 
    	Parameter BASE_ADDRESS bound to: 6'b100000 
    	Parameter PCORE_VERSION bound to: 65633 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'up_xfer_cntrl' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_cntrl.v:38]
    	Parameter DATA_WIDTH bound to: 15 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_xfer_cntrl' (22#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_cntrl.v:38]
    INFO: [Synth 8-6157] synthesizing module 'up_xfer_cntrl__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_cntrl.v:38]
    	Parameter DATA_WIDTH bound to: 624 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_xfer_cntrl__parameterized0' (22#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_cntrl.v:38]
    INFO: [Synth 8-6157] synthesizing module 'up_xfer_status' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_status.v:38]
    	Parameter DATA_WIDTH bound to: 8 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_xfer_status' (23#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_status.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'up_tdd_cntrl' (24#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_tdd_cntrl.v:37]
    INFO: [Synth 8-6157] synthesizing module 'ad_tdd_control' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_tdd_control.v:38]
    	Parameter TX_DATA_PATH_DELAY bound to: 0 - type: integer 
    	Parameter CONTROL_PATH_DELAY bound to: 0 - type: integer 
    	Parameter ON bound to: 1'b1 
    	Parameter OFF bound to: 1'b0 
    INFO: [Synth 8-6157] synthesizing module 'ad_addsub' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_addsub.v:42]
    	Parameter A_DATA_WIDTH bound to: 24 - type: integer 
    	Parameter B_DATA_VALUE bound to: 0 - type: integer 
    	Parameter ADD_OR_SUB_N bound to: 0 - type: integer 
    	Parameter ADDER bound to: 1 - type: integer 
    	Parameter SUBSTRACTER bound to: 0 - type: integer 
    WARNING: [Synth 8-3936] Found unconnected internal register 'out_d2_reg' and it is trimmed from '25' to '24' bits. [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_addsub.v:98]
    INFO: [Synth 8-6155] done synthesizing module 'ad_addsub' (25#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_addsub.v:42]
    INFO: [Synth 8-6155] done synthesizing module 'ad_tdd_control' (26#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_tdd_control.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_ad9361_tdd' (27#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_tdd.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_ad9361_rx' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_rx.v:39]
    	Parameter ID bound to: 0 - type: integer 
    	Parameter FPGA_TECHNOLOGY bound to: 1 - type: integer 
    	Parameter FPGA_FAMILY bound to: 4 - type: integer 
    	Parameter SPEED_GRADE bound to: 21 - type: integer 
    	Parameter DEV_PACKAGE bound to: 4 - type: integer 
    	Parameter MODE_1R1T bound to: 0 - type: integer 
    	Parameter CMOS_OR_LVDS_N bound to: 0 - type: integer 
    	Parameter PPS_RECEIVER_ENABLE bound to: 0 - type: integer 
    	Parameter INIT_DELAY bound to: 29 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter DATAFORMAT_DISABLE bound to: 0 - type: integer 
    	Parameter DCFILTER_DISABLE bound to: 0 - type: integer 
    	Parameter IQCORRECTION_DISABLE bound to: 0 - type: integer 
    	Parameter CONFIG bound to: 0 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_ad9361_rx_channel' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_rx_channel.v:38]
    	Parameter Q_OR_I_N bound to: 0 - type: integer 
    	Parameter CHANNEL_ID bound to: 0 - type: integer 
    	Parameter DISABLE bound to: 0 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter DATAFORMAT_DISABLE bound to: 0 - type: integer 
    	Parameter DCFILTER_DISABLE bound to: 0 - type: integer 
    	Parameter IQCORRECTION_DISABLE bound to: 0 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_ad9361_rx_pnmon' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_rx_pnmon.v:39]
    	Parameter Q_OR_I_N bound to: 0 - type: integer 
    	Parameter PRBS_SEL bound to: 0 - type: integer 
    	Parameter PRBS_P09 bound to: 0 - type: integer 
    	Parameter PRBS_P11 bound to: 1 - type: integer 
    	Parameter PRBS_P15 bound to: 2 - type: integer 
    	Parameter PRBS_P20 bound to: 3 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'ad_pnmon' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_pnmon.v:39]
    	Parameter DATA_WIDTH bound to: 24 - type: integer 
    	Parameter OOS_THRESHOLD bound to: 16 - type: integer 
    	Parameter ALLOW_ZERO_MASKING bound to: 0 - type: integer 
    	Parameter CNT_W bound to: 4 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_pnmon' (28#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_pnmon.v:39]
    INFO: [Synth 8-6155] done synthesizing module 'axi_ad9361_rx_pnmon' (29#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_rx_pnmon.v:39]
    INFO: [Synth 8-6157] synthesizing module 'ad_datafmt' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_datafmt.v:39]
    	Parameter DATA_WIDTH bound to: 12 - type: integer 
    	Parameter OCTETS_PER_SAMPLE bound to: 2 - type: integer 
    	Parameter DISABLE bound to: 0 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_datafmt' (30#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_datafmt.v:39]
    INFO: [Synth 8-6157] synthesizing module 'ad_dcfilter' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_dcfilter.v:39]
    	Parameter DISABLE bound to: 0 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'DSP48E1' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:12404]
    	Parameter ACASCREG bound to: 1 - type: integer 
    	Parameter ADREG bound to: 1 - type: integer 
    	Parameter ALUMODEREG bound to: 0 - type: integer 
    	Parameter AREG bound to: 1 - type: integer 
    	Parameter AUTORESET_PATDET bound to: NO_RESET - type: string 
    	Parameter A_INPUT bound to: DIRECT - type: string 
    	Parameter BCASCREG bound to: 1 - type: integer 
    	Parameter BREG bound to: 1 - type: integer 
    	Parameter B_INPUT bound to: DIRECT - type: string 
    	Parameter CARRYINREG bound to: 0 - type: integer 
    	Parameter CARRYINSELREG bound to: 0 - type: integer 
    	Parameter CREG bound to: 1 - type: integer 
    	Parameter DREG bound to: 0 - type: integer 
    	Parameter INMODEREG bound to: 0 - type: integer 
    	Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 
    	Parameter IS_CARRYIN_INVERTED bound to: 1'b0 
    	Parameter IS_CLK_INVERTED bound to: 1'b0 
    	Parameter IS_INMODE_INVERTED bound to: 5'b00000 
    	Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 
    	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
    	Parameter MREG bound to: 1 - type: integer 
    	Parameter OPMODEREG bound to: 0 - type: integer 
    	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
    	Parameter PREG bound to: 1 - type: integer 
    	Parameter SEL_MASK bound to: MASK - type: string 
    	Parameter SEL_PATTERN bound to: PATTERN - type: string 
    	Parameter USE_DPORT bound to: TRUE - type: string 
    	Parameter USE_MULT bound to: MULTIPLY - type: string 
    	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
    	Parameter USE_SIMD bound to: ONE48 - type: string 
    INFO: [Synth 8-6155] done synthesizing module 'DSP48E1' (31#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:12404]
    INFO: [Synth 8-6155] done synthesizing module 'ad_dcfilter' (32#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_dcfilter.v:39]
    INFO: [Synth 8-6157] synthesizing module 'ad_iqcor' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_iqcor.v:43]
    	Parameter Q_OR_I_N bound to: 0 - type: integer 
    	Parameter SCALE_ONLY bound to: 0 - type: integer 
    	Parameter DISABLE bound to: 0 - type: integer 
    	Parameter CR bound to: 16 - type: integer 
    	Parameter DPW bound to: 1 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'ad_mul' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_mul.v:38]
    	Parameter A_DATA_WIDTH bound to: 17 - type: integer 
    	Parameter B_DATA_WIDTH bound to: 17 - type: integer 
    	Parameter DELAY_DATA_WIDTH bound to: 16 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'MULT_MACRO' [/tools/Xilinx/Vivado/2019.1/data/verilog/src/unimacro/MULT_MACRO.v:24]
    	Parameter DEVICE bound to: VIRTEX5 - type: string 
    	Parameter LATENCY bound to: 3 - type: integer 
    	Parameter STYLE bound to: DSP - type: string 
    	Parameter WIDTH_A bound to: 17 - type: integer 
    	Parameter WIDTH_B bound to: 17 - type: integer 
    	Parameter MODEL_TYPE bound to: 0 - type: integer 
    	Parameter VERBOSITY bound to: 0 - type: integer 
    	Parameter AREG_IN bound to: 1 - type: integer 
    	Parameter BREG_IN bound to: 1 - type: integer 
    	Parameter MREG_IN bound to: 1 - type: integer 
    	Parameter PREG_IN bound to: 1 - type: integer 
    	Parameter A1REG_IN bound to: 1 - type: integer 
    	Parameter A0REG_IN bound to: 0 - type: integer 
    	Parameter B1REG_IN bound to: 1 - type: integer 
    	Parameter B0REG_IN bound to: 0 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'DSP48E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:12287]
    	Parameter ACASCREG bound to: 1 - type: integer 
    	Parameter ALUMODEREG bound to: 1 - type: integer 
    	Parameter AREG bound to: 1 - type: integer 
    	Parameter AUTORESET_PATTERN_DETECT bound to: FALSE - type: string 
    	Parameter AUTORESET_PATTERN_DETECT_OPTINV bound to: MATCH - type: string 
    	Parameter A_INPUT bound to: DIRECT - type: string 
    	Parameter BCASCREG bound to: 1 - type: integer 
    	Parameter BREG bound to: 1 - type: integer 
    	Parameter B_INPUT bound to: DIRECT - type: string 
    	Parameter CARRYINREG bound to: 1 - type: integer 
    	Parameter CARRYINSELREG bound to: 1 - type: integer 
    	Parameter CREG bound to: 1 - type: integer 
    	Parameter MASK bound to: 48'b001111111111111111111111111111111111111111111111 
    	Parameter MREG bound to: 1 - type: integer 
    	Parameter MULTCARRYINREG bound to: 1 - type: integer 
    	Parameter OPMODEREG bound to: 1 - type: integer 
    	Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 
    	Parameter PREG bound to: 1 - type: integer 
    	Parameter SEL_MASK bound to: MASK - type: string 
    	Parameter SEL_PATTERN bound to: PATTERN - type: string 
    	Parameter SEL_ROUNDING_MASK bound to: SEL_MASK - type: string 
    	Parameter SIM_MODE bound to: SAFE - type: string 
    	Parameter USE_MULT bound to: MULT_S - type: string 
    	Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string 
    	Parameter USE_SIMD bound to: ONE48 - type: string 
    INFO: [Synth 8-6155] done synthesizing module 'DSP48E' (33#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:12287]
    INFO: [Synth 8-6155] done synthesizing module 'MULT_MACRO' (34#1) [/tools/Xilinx/Vivado/2019.1/data/verilog/src/unimacro/MULT_MACRO.v:24]
    INFO: [Synth 8-6155] done synthesizing module 'ad_mul' (35#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_mul.v:38]
    WARNING: [Synth 8-693] zero replication count - replication ignored [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_iqcor.v:138]
    INFO: [Synth 8-6157] synthesizing module 'ad_mul__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_mul.v:38]
    	Parameter A_DATA_WIDTH bound to: 17 - type: integer 
    	Parameter B_DATA_WIDTH bound to: 17 - type: integer 
    	Parameter DELAY_DATA_WIDTH bound to: 17 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_mul__parameterized0' (35#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_mul.v:38]
    WARNING: [Synth 8-693] zero replication count - replication ignored [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_iqcor.v:127]
    WARNING: [Synth 8-3936] Found unconnected internal register 'g_loop[0].p1_data_p_reg' and it is trimmed from '34' to '30' bits. [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_iqcor.v:175]
    INFO: [Synth 8-6155] done synthesizing module 'ad_iqcor' (36#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_iqcor.v:43]
    INFO: [Synth 8-6157] synthesizing module 'up_adc_channel' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_adc_channel.v:38]
    	Parameter COMMON_ID bound to: 6'b000001 
    	Parameter CHANNEL_ID bound to: 0 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter DATAFORMAT_DISABLE bound to: 0 - type: integer 
    	Parameter DCFILTER_DISABLE bound to: 0 - type: integer 
    	Parameter IQCORRECTION_DISABLE bound to: 0 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'up_xfer_cntrl__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_cntrl.v:38]
    	Parameter DATA_WIDTH bound to: 78 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_xfer_cntrl__parameterized1' (36#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_cntrl.v:38]
    INFO: [Synth 8-6157] synthesizing module 'up_xfer_status__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_status.v:38]
    	Parameter DATA_WIDTH bound to: 3 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_xfer_status__parameterized0' (36#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_status.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'up_adc_channel' (37#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_adc_channel.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_ad9361_rx_channel' (38#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_rx_channel.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_ad9361_rx_channel__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_rx_channel.v:38]
    	Parameter Q_OR_I_N bound to: 1 - type: integer 
    	Parameter CHANNEL_ID bound to: 1 - type: integer 
    	Parameter DISABLE bound to: 0 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter DATAFORMAT_DISABLE bound to: 0 - type: integer 
    	Parameter DCFILTER_DISABLE bound to: 0 - type: integer 
    	Parameter IQCORRECTION_DISABLE bound to: 0 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_ad9361_rx_pnmon__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_rx_pnmon.v:39]
    	Parameter Q_OR_I_N bound to: 1 - type: integer 
    	Parameter PRBS_SEL bound to: 1 - type: integer 
    	Parameter PRBS_P09 bound to: 0 - type: integer 
    	Parameter PRBS_P11 bound to: 1 - type: integer 
    	Parameter PRBS_P15 bound to: 2 - type: integer 
    	Parameter PRBS_P20 bound to: 3 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_ad9361_rx_pnmon__parameterized0' (38#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_rx_pnmon.v:39]
    INFO: [Synth 8-6157] synthesizing module 'ad_iqcor__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_iqcor.v:43]
    	Parameter Q_OR_I_N bound to: 1 - type: integer 
    	Parameter SCALE_ONLY bound to: 0 - type: integer 
    	Parameter DISABLE bound to: 0 - type: integer 
    	Parameter CR bound to: 16 - type: integer 
    	Parameter DPW bound to: 1 - type: integer 
    WARNING: [Synth 8-693] zero replication count - replication ignored [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_iqcor.v:138]
    WARNING: [Synth 8-693] zero replication count - replication ignored [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_iqcor.v:127]
    WARNING: [Synth 8-3936] Found unconnected internal register 'g_loop[0].p1_data_p_reg' and it is trimmed from '34' to '30' bits. [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_iqcor.v:175]
    INFO: [Synth 8-6155] done synthesizing module 'ad_iqcor__parameterized0' (38#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_iqcor.v:43]
    INFO: [Synth 8-6157] synthesizing module 'up_adc_channel__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_adc_channel.v:38]
    	Parameter COMMON_ID bound to: 6'b000001 
    	Parameter CHANNEL_ID bound to: 1 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter DATAFORMAT_DISABLE bound to: 0 - type: integer 
    	Parameter DCFILTER_DISABLE bound to: 0 - type: integer 
    	Parameter IQCORRECTION_DISABLE bound to: 0 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_adc_channel__parameterized0' (38#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_adc_channel.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_ad9361_rx_channel__parameterized0' (38#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_rx_channel.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_ad9361_rx_channel__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_rx_channel.v:38]
    	Parameter Q_OR_I_N bound to: 0 - type: integer 
    	Parameter CHANNEL_ID bound to: 2 - type: integer 
    	Parameter DISABLE bound to: 0 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter DATAFORMAT_DISABLE bound to: 0 - type: integer 
    	Parameter DCFILTER_DISABLE bound to: 0 - type: integer 
    	Parameter IQCORRECTION_DISABLE bound to: 0 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_ad9361_rx_pnmon__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_rx_pnmon.v:39]
    	Parameter Q_OR_I_N bound to: 0 - type: integer 
    	Parameter PRBS_SEL bound to: 2 - type: integer 
    	Parameter PRBS_P09 bound to: 0 - type: integer 
    	Parameter PRBS_P11 bound to: 1 - type: integer 
    	Parameter PRBS_P15 bound to: 2 - type: integer 
    	Parameter PRBS_P20 bound to: 3 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_ad9361_rx_pnmon__parameterized1' (38#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_rx_pnmon.v:39]
    INFO: [Synth 8-6157] synthesizing module 'up_adc_channel__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_adc_channel.v:38]
    	Parameter COMMON_ID bound to: 6'b000001 
    	Parameter CHANNEL_ID bound to: 2 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter DATAFORMAT_DISABLE bound to: 0 - type: integer 
    	Parameter DCFILTER_DISABLE bound to: 0 - type: integer 
    	Parameter IQCORRECTION_DISABLE bound to: 0 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_adc_channel__parameterized1' (38#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_adc_channel.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_ad9361_rx_channel__parameterized1' (38#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_rx_channel.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_ad9361_rx_channel__parameterized2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_rx_channel.v:38]
    	Parameter Q_OR_I_N bound to: 1 - type: integer 
    	Parameter CHANNEL_ID bound to: 3 - type: integer 
    	Parameter DISABLE bound to: 0 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter DATAFORMAT_DISABLE bound to: 0 - type: integer 
    	Parameter DCFILTER_DISABLE bound to: 0 - type: integer 
    	Parameter IQCORRECTION_DISABLE bound to: 0 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_ad9361_rx_pnmon__parameterized2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_rx_pnmon.v:39]
    	Parameter Q_OR_I_N bound to: 1 - type: integer 
    	Parameter PRBS_SEL bound to: 3 - type: integer 
    	Parameter PRBS_P09 bound to: 0 - type: integer 
    	Parameter PRBS_P11 bound to: 1 - type: integer 
    	Parameter PRBS_P15 bound to: 2 - type: integer 
    	Parameter PRBS_P20 bound to: 3 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_ad9361_rx_pnmon__parameterized2' (38#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_rx_pnmon.v:39]
    INFO: [Synth 8-6157] synthesizing module 'up_adc_channel__parameterized2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_adc_channel.v:38]
    	Parameter COMMON_ID bound to: 6'b000001 
    	Parameter CHANNEL_ID bound to: 3 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter DATAFORMAT_DISABLE bound to: 0 - type: integer 
    	Parameter DCFILTER_DISABLE bound to: 0 - type: integer 
    	Parameter IQCORRECTION_DISABLE bound to: 0 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_adc_channel__parameterized2' (38#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_adc_channel.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_ad9361_rx_channel__parameterized2' (38#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_rx_channel.v:38]
    INFO: [Synth 8-6157] synthesizing module 'up_adc_common' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_adc_common.v:38]
    	Parameter ID bound to: 0 - type: integer 
    	Parameter FPGA_TECHNOLOGY bound to: 1 - type: integer 
    	Parameter FPGA_FAMILY bound to: 4 - type: integer 
    	Parameter SPEED_GRADE bound to: 21 - type: integer 
    	Parameter DEV_PACKAGE bound to: 4 - type: integer 
    	Parameter CONFIG bound to: 0 - type: integer 
    	Parameter COMMON_ID bound to: 6'b000000 
    	Parameter DRP_DISABLE bound to: 1 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter GPIO_DISABLE bound to: 0 - type: integer 
    	Parameter START_CODE_DISABLE bound to: 0 - type: integer 
    	Parameter VERSION bound to: 655714 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'ad_rst' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_rst.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'ad_rst' (39#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_rst.v:38]
    INFO: [Synth 8-6157] synthesizing module 'up_xfer_cntrl__parameterized2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_cntrl.v:38]
    	Parameter DATA_WIDTH bound to: 44 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_xfer_cntrl__parameterized2' (39#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_cntrl.v:38]
    INFO: [Synth 8-6157] synthesizing module 'up_clock_mon' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_clock_mon.v:38]
    	Parameter TOTAL_WIDTH bound to: 32 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_clock_mon' (40#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_clock_mon.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'up_adc_common' (41#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_adc_common.v:38]
    INFO: [Synth 8-6157] synthesizing module 'up_delay_cntrl' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_delay_cntrl.v:38]
    	Parameter DISABLE bound to: 0 - type: integer 
    	Parameter INIT_DELAY bound to: 29 - type: integer 
    	Parameter DATA_WIDTH bound to: 13 - type: integer 
    	Parameter DRP_WIDTH bound to: 5 - type: integer 
    	Parameter BASE_ADDRESS bound to: 6'b000010 
    INFO: [Synth 8-6155] done synthesizing module 'up_delay_cntrl' (42#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_delay_cntrl.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_ad9361_rx' (43#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_rx.v:39]
    INFO: [Synth 8-6157] synthesizing module 'axi_ad9361_tx' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_tx.v:38]
    	Parameter ID bound to: 0 - type: integer 
    	Parameter FPGA_TECHNOLOGY bound to: 1 - type: integer 
    	Parameter FPGA_FAMILY bound to: 4 - type: integer 
    	Parameter SPEED_GRADE bound to: 21 - type: integer 
    	Parameter DEV_PACKAGE bound to: 4 - type: integer 
    	Parameter MODE_1R1T bound to: 0 - type: integer 
    	Parameter CLK_EDGE_SEL bound to: 0 - type: integer 
    	Parameter CMOS_OR_LVDS_N bound to: 0 - type: integer 
    	Parameter PPS_RECEIVER_ENABLE bound to: 0 - type: integer 
    	Parameter INIT_DELAY bound to: 0 - type: integer 
    	Parameter DAC_DDS_DISABLE bound to: 0 - type: integer 
    	Parameter DAC_DDS_TYPE bound to: 1 - type: integer 
    	Parameter DAC_DDS_CORDIC_DW bound to: 14 - type: integer 
    	Parameter DAC_DDS_CORDIC_PHASE_DW bound to: 13 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter DELAYCNTRL_DISABLE bound to: 0 - type: integer 
    	Parameter IQCORRECTION_DISABLE bound to: 0 - type: integer 
    	Parameter CONFIG bound to: 0 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_ad9361_tx_channel' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_tx_channel.v:38]
    	Parameter Q_OR_I_N bound to: 0 - type: integer 
    	Parameter CHANNEL_ID bound to: 0 - type: integer 
    	Parameter DISABLE bound to: 0 - type: integer 
    	Parameter DAC_DDS_DISABLE bound to: 0 - type: integer 
    	Parameter DAC_DDS_TYPE bound to: 1 - type: integer 
    	Parameter DAC_DDS_CORDIC_DW bound to: 14 - type: integer 
    	Parameter DAC_DDS_CORDIC_PHASE_DW bound to: 13 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter IQCORRECTION_DISABLE bound to: 0 - type: integer 
    	Parameter PRBS_SEL bound to: 0 - type: integer 
    	Parameter PRBS_P09 bound to: 0 - type: integer 
    	Parameter PRBS_P11 bound to: 1 - type: integer 
    	Parameter PRBS_P15 bound to: 2 - type: integer 
    	Parameter PRBS_P20 bound to: 3 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'ad_dds' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds.v:39]
    	Parameter DISABLE bound to: 0 - type: integer 
    	Parameter DDS_DW bound to: 12 - type: integer 
    	Parameter PHASE_DW bound to: 16 - type: integer 
    	Parameter DDS_TYPE bound to: 1 - type: integer 
    	Parameter CORDIC_DW bound to: 14 - type: integer 
    	Parameter CORDIC_PHASE_DW bound to: 13 - type: integer 
    	Parameter CLK_RATIO bound to: 1 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'ad_dds_2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_2.v:38]
    	Parameter DDS_DW bound to: 12 - type: integer 
    	Parameter PHASE_DW bound to: 16 - type: integer 
    	Parameter DDS_TYPE bound to: 1 - type: integer 
    	Parameter CORDIC_DW bound to: 14 - type: integer 
    	Parameter CORDIC_PHASE_DW bound to: 13 - type: integer 
    	Parameter CORDIC bound to: 1 - type: integer 
    	Parameter POLYNOMIAL bound to: 2 - type: integer 
    	Parameter DDS_D_DW bound to: 14 - type: integer 
    	Parameter DDS_P_DW bound to: 13 - type: integer 
    	Parameter C_T_WIDTH bound to: 2 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'ad_dds_1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_1.v:38]
    	Parameter DDS_TYPE bound to: 1 - type: integer 
    	Parameter DDS_D_DW bound to: 14 - type: integer 
    	Parameter DDS_P_DW bound to: 13 - type: integer 
    	Parameter DDS_CORDIC_TYPE bound to: 1 - type: integer 
    	Parameter DDS_POLINOMIAL_TYPE bound to: 2 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'ad_dds_sine_cordic' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_sine_cordic.v:38]
    	Parameter PHASE_DW bound to: 13 - type: integer 
    	Parameter CORDIC_DW bound to: 14 - type: integer 
    	Parameter DELAY_DW bound to: 1 - type: integer 
    	Parameter LUT_FSCALE bound to: 8192 - type: integer 
    	Parameter X_FSCALE bound to: 16384 - type: integer 
    	Parameter APROX_DW_GAIN_ERR bound to: 4 - type: integer 
    	Parameter X_VALUE bound to: 14'b01001101101011 
    INFO: [Synth 8-6157] synthesizing module 'ad_dds_cordic_pipe' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    	Parameter P_DW bound to: 13 - type: integer 
    	Parameter D_DW bound to: 14 - type: integer 
    	Parameter DELAY_DW bound to: 1 - type: integer 
    	Parameter SHIFT bound to: 0 - type: integer 
    INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:54]
    INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:55]
    INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:56]
    INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:57]
    INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:58]
    INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:59]
    INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:60]
    INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:61]
    WARNING: [Synth 8-693] zero replication count - replication ignored [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:77]
    WARNING: [Synth 8-693] zero replication count - replication ignored [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:78]
    INFO: [Synth 8-6155] done synthesizing module 'ad_dds_cordic_pipe' (44#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_dds_cordic_pipe__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    	Parameter P_DW bound to: 13 - type: integer 
    	Parameter D_DW bound to: 14 - type: integer 
    	Parameter DELAY_DW bound to: 1 - type: integer 
    	Parameter SHIFT bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_dds_cordic_pipe__parameterized0' (44#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_dds_cordic_pipe__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    	Parameter P_DW bound to: 13 - type: integer 
    	Parameter D_DW bound to: 14 - type: integer 
    	Parameter DELAY_DW bound to: 1 - type: integer 
    	Parameter SHIFT bound to: 2 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_dds_cordic_pipe__parameterized1' (44#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_dds_cordic_pipe__parameterized2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    	Parameter P_DW bound to: 13 - type: integer 
    	Parameter D_DW bound to: 14 - type: integer 
    	Parameter DELAY_DW bound to: 1 - type: integer 
    	Parameter SHIFT bound to: 3 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_dds_cordic_pipe__parameterized2' (44#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_dds_cordic_pipe__parameterized3' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    	Parameter P_DW bound to: 13 - type: integer 
    	Parameter D_DW bound to: 14 - type: integer 
    	Parameter DELAY_DW bound to: 1 - type: integer 
    	Parameter SHIFT bound to: 4 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_dds_cordic_pipe__parameterized3' (44#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_dds_cordic_pipe__parameterized4' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    	Parameter P_DW bound to: 13 - type: integer 
    	Parameter D_DW bound to: 14 - type: integer 
    	Parameter DELAY_DW bound to: 1 - type: integer 
    	Parameter SHIFT bound to: 5 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_dds_cordic_pipe__parameterized4' (44#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_dds_cordic_pipe__parameterized5' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    	Parameter P_DW bound to: 13 - type: integer 
    	Parameter D_DW bound to: 14 - type: integer 
    	Parameter DELAY_DW bound to: 1 - type: integer 
    	Parameter SHIFT bound to: 6 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_dds_cordic_pipe__parameterized5' (44#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_dds_cordic_pipe__parameterized6' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    	Parameter P_DW bound to: 13 - type: integer 
    	Parameter D_DW bound to: 14 - type: integer 
    	Parameter DELAY_DW bound to: 1 - type: integer 
    	Parameter SHIFT bound to: 7 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_dds_cordic_pipe__parameterized6' (44#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_dds_cordic_pipe__parameterized7' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    	Parameter P_DW bound to: 13 - type: integer 
    	Parameter D_DW bound to: 14 - type: integer 
    	Parameter DELAY_DW bound to: 1 - type: integer 
    	Parameter SHIFT bound to: 8 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_dds_cordic_pipe__parameterized7' (44#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_dds_cordic_pipe__parameterized8' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    	Parameter P_DW bound to: 13 - type: integer 
    	Parameter D_DW bound to: 14 - type: integer 
    	Parameter DELAY_DW bound to: 1 - type: integer 
    	Parameter SHIFT bound to: 9 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_dds_cordic_pipe__parameterized8' (44#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_dds_cordic_pipe__parameterized9' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    	Parameter P_DW bound to: 13 - type: integer 
    	Parameter D_DW bound to: 14 - type: integer 
    	Parameter DELAY_DW bound to: 1 - type: integer 
    	Parameter SHIFT bound to: 10 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_dds_cordic_pipe__parameterized9' (44#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_dds_cordic_pipe__parameterized10' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    	Parameter P_DW bound to: 13 - type: integer 
    	Parameter D_DW bound to: 14 - type: integer 
    	Parameter DELAY_DW bound to: 1 - type: integer 
    	Parameter SHIFT bound to: 11 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_dds_cordic_pipe__parameterized10' (44#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_cordic_pipe.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'ad_dds_sine_cordic' (45#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_sine_cordic.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_mul__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_mul.v:38]
    	Parameter A_DATA_WIDTH bound to: 15 - type: integer 
    	Parameter B_DATA_WIDTH bound to: 17 - type: integer 
    	Parameter DELAY_DATA_WIDTH bound to: 1 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'MULT_MACRO__parameterized0' [/tools/Xilinx/Vivado/2019.1/data/verilog/src/unimacro/MULT_MACRO.v:24]
    	Parameter DEVICE bound to: VIRTEX5 - type: string 
    	Parameter LATENCY bound to: 3 - type: integer 
    	Parameter STYLE bound to: DSP - type: string 
    	Parameter WIDTH_A bound to: 15 - type: integer 
    	Parameter WIDTH_B bound to: 17 - type: integer 
    	Parameter MODEL_TYPE bound to: 0 - type: integer 
    	Parameter VERBOSITY bound to: 0 - type: integer 
    	Parameter AREG_IN bound to: 1 - type: integer 
    	Parameter BREG_IN bound to: 1 - type: integer 
    	Parameter MREG_IN bound to: 1 - type: integer 
    	Parameter PREG_IN bound to: 1 - type: integer 
    	Parameter A1REG_IN bound to: 1 - type: integer 
    	Parameter A0REG_IN bound to: 0 - type: integer 
    	Parameter B1REG_IN bound to: 1 - type: integer 
    	Parameter B0REG_IN bound to: 0 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'MULT_MACRO__parameterized0' (45#1) [/tools/Xilinx/Vivado/2019.1/data/verilog/src/unimacro/MULT_MACRO.v:24]
    INFO: [Synth 8-6155] done synthesizing module 'ad_mul__parameterized1' (45#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_mul.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'ad_dds_1' (46#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_1.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'ad_dds_2' (47#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds_2.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'ad_dds' (48#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_dds.v:39]
    INFO: [Synth 8-6157] synthesizing module 'up_dac_channel' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_dac_channel.v:38]
    	Parameter COMMON_ID bound to: 6'b010001 
    	Parameter CHANNEL_ID bound to: 0 - type: integer 
    	Parameter DDS_DISABLE bound to: 0 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter IQCORRECTION_DISABLE bound to: 0 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'up_xfer_cntrl__parameterized3' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_cntrl.v:38]
    	Parameter DATA_WIDTH bound to: 167 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_xfer_cntrl__parameterized3' (48#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_cntrl.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'up_dac_channel' (49#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_dac_channel.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_ad9361_tx_channel' (50#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_tx_channel.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_ad9361_tx_channel__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_tx_channel.v:38]
    	Parameter Q_OR_I_N bound to: 1 - type: integer 
    	Parameter CHANNEL_ID bound to: 1 - type: integer 
    	Parameter DISABLE bound to: 0 - type: integer 
    	Parameter DAC_DDS_DISABLE bound to: 0 - type: integer 
    	Parameter DAC_DDS_TYPE bound to: 1 - type: integer 
    	Parameter DAC_DDS_CORDIC_DW bound to: 14 - type: integer 
    	Parameter DAC_DDS_CORDIC_PHASE_DW bound to: 13 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter IQCORRECTION_DISABLE bound to: 0 - type: integer 
    	Parameter PRBS_SEL bound to: 1 - type: integer 
    	Parameter PRBS_P09 bound to: 0 - type: integer 
    	Parameter PRBS_P11 bound to: 1 - type: integer 
    	Parameter PRBS_P15 bound to: 2 - type: integer 
    	Parameter PRBS_P20 bound to: 3 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'up_dac_channel__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_dac_channel.v:38]
    	Parameter COMMON_ID bound to: 6'b010001 
    	Parameter CHANNEL_ID bound to: 1 - type: integer 
    	Parameter DDS_DISABLE bound to: 0 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter IQCORRECTION_DISABLE bound to: 0 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_dac_channel__parameterized0' (50#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_dac_channel.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_ad9361_tx_channel__parameterized0' (50#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_tx_channel.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_ad9361_tx_channel__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_tx_channel.v:38]
    	Parameter Q_OR_I_N bound to: 0 - type: integer 
    	Parameter CHANNEL_ID bound to: 2 - type: integer 
    	Parameter DISABLE bound to: 0 - type: integer 
    	Parameter DAC_DDS_DISABLE bound to: 0 - type: integer 
    	Parameter DAC_DDS_TYPE bound to: 1 - type: integer 
    	Parameter DAC_DDS_CORDIC_DW bound to: 14 - type: integer 
    	Parameter DAC_DDS_CORDIC_PHASE_DW bound to: 13 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter IQCORRECTION_DISABLE bound to: 0 - type: integer 
    	Parameter PRBS_SEL bound to: 2 - type: integer 
    	Parameter PRBS_P09 bound to: 0 - type: integer 
    	Parameter PRBS_P11 bound to: 1 - type: integer 
    	Parameter PRBS_P15 bound to: 2 - type: integer 
    	Parameter PRBS_P20 bound to: 3 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'up_dac_channel__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_dac_channel.v:38]
    	Parameter COMMON_ID bound to: 6'b010001 
    	Parameter CHANNEL_ID bound to: 2 - type: integer 
    	Parameter DDS_DISABLE bound to: 0 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter IQCORRECTION_DISABLE bound to: 0 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_dac_channel__parameterized1' (50#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_dac_channel.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_ad9361_tx_channel__parameterized1' (50#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_tx_channel.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_ad9361_tx_channel__parameterized2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_tx_channel.v:38]
    	Parameter Q_OR_I_N bound to: 1 - type: integer 
    	Parameter CHANNEL_ID bound to: 3 - type: integer 
    	Parameter DISABLE bound to: 0 - type: integer 
    	Parameter DAC_DDS_DISABLE bound to: 0 - type: integer 
    	Parameter DAC_DDS_TYPE bound to: 1 - type: integer 
    	Parameter DAC_DDS_CORDIC_DW bound to: 14 - type: integer 
    	Parameter DAC_DDS_CORDIC_PHASE_DW bound to: 13 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter IQCORRECTION_DISABLE bound to: 0 - type: integer 
    	Parameter PRBS_SEL bound to: 3 - type: integer 
    	Parameter PRBS_P09 bound to: 0 - type: integer 
    	Parameter PRBS_P11 bound to: 1 - type: integer 
    	Parameter PRBS_P15 bound to: 2 - type: integer 
    	Parameter PRBS_P20 bound to: 3 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'up_dac_channel__parameterized2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_dac_channel.v:38]
    	Parameter COMMON_ID bound to: 6'b010001 
    	Parameter CHANNEL_ID bound to: 3 - type: integer 
    	Parameter DDS_DISABLE bound to: 0 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter IQCORRECTION_DISABLE bound to: 0 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_dac_channel__parameterized2' (50#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_dac_channel.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_ad9361_tx_channel__parameterized2' (50#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_tx_channel.v:38]
    INFO: [Synth 8-6157] synthesizing module 'up_dac_common' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_dac_common.v:38]
    	Parameter ID bound to: 0 - type: integer 
    	Parameter FPGA_TECHNOLOGY bound to: 1 - type: integer 
    	Parameter FPGA_FAMILY bound to: 4 - type: integer 
    	Parameter SPEED_GRADE bound to: 21 - type: integer 
    	Parameter DEV_PACKAGE bound to: 4 - type: integer 
    	Parameter CONFIG bound to: 0 - type: integer 
    	Parameter CLK_EDGE_SEL bound to: 0 - type: integer 
    	Parameter COMMON_ID bound to: 6'b010000 
    	Parameter DRP_DISABLE bound to: 1 - type: integer 
    	Parameter USERPORTS_DISABLE bound to: 0 - type: integer 
    	Parameter GPIO_DISABLE bound to: 0 - type: integer 
    	Parameter VERSION bound to: 590178 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'up_xfer_cntrl__parameterized4' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_cntrl.v:38]
    	Parameter DATA_WIDTH bound to: 30 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_xfer_cntrl__parameterized4' (50#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_cntrl.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'up_dac_common' (51#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_dac_common.v:38]
    WARNING: [Synth 8-7023] instance 'i_up_dac_common' of module 'up_dac_common' has 43 connections declared, but only 42 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_tx.v:372]
    INFO: [Synth 8-6157] synthesizing module 'up_delay_cntrl__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_delay_cntrl.v:38]
    	Parameter DISABLE bound to: 0 - type: integer 
    	Parameter INIT_DELAY bound to: 0 - type: integer 
    	Parameter DATA_WIDTH bound to: 16 - type: integer 
    	Parameter DRP_WIDTH bound to: 5 - type: integer 
    	Parameter BASE_ADDRESS bound to: 6'b010010 
    INFO: [Synth 8-6155] done synthesizing module 'up_delay_cntrl__parameterized0' (51#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_delay_cntrl.v:38]
    INFO: [Synth 8-4471] merging register 'dac_valid_q0_int_reg' into 'dac_valid_i0_int_reg' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_tx.v:188]
    WARNING: [Synth 8-6014] Unused sequential element dac_valid_q0_int_reg was removed.  [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_tx.v:188]
    INFO: [Synth 8-4471] merging register 'dac_valid_q1_int_reg' into 'dac_valid_i1_int_reg' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_tx.v:190]
    WARNING: [Synth 8-6014] Unused sequential element dac_valid_q1_int_reg was removed.  [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_tx.v:190]
    INFO: [Synth 8-6155] done synthesizing module 'axi_ad9361_tx' (52#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361_tx.v:38]
    INFO: [Synth 8-6157] synthesizing module 'up_axi' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_axi.v:38]
    	Parameter AXI_ADDRESS_WIDTH bound to: 16 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_axi' (53#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_axi.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_ad9361' (54#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/25a2/axi_ad9361.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'system_axi_ad9361_0' (55#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/synth/system_axi_ad9361_0.v:57]
    WARNING: [Synth 8-7023] instance 'axi_ad9361' of module 'system_axi_ad9361_0' has 79 connections declared, but only 76 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:2928]
    INFO: [Synth 8-6157] synthesizing module 'system_axi_ad9361_adc_dma_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_adc_dma_0/synth/system_axi_ad9361_adc_dma_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac.v:38]
    	Parameter ID bound to: 0 - type: integer 
    	Parameter DMA_DATA_WIDTH_SRC bound to: 64 - type: integer 
    	Parameter DMA_DATA_WIDTH_DEST bound to: 64 - type: integer 
    	Parameter DMA_LENGTH_WIDTH bound to: 24 - type: integer 
    	Parameter DMA_2D_TRANSFER bound to: 1'b0 
    	Parameter ASYNC_CLK_REQ_SRC bound to: 1'b1 
    	Parameter ASYNC_CLK_SRC_DEST bound to: 1'b1 
    	Parameter ASYNC_CLK_DEST_REQ bound to: 1'b0 
    	Parameter AXI_SLICE_DEST bound to: 1'b0 
    	Parameter AXI_SLICE_SRC bound to: 1'b0 
    	Parameter SYNC_TRANSFER_START bound to: 1'b1 
    	Parameter CYCLIC bound to: 1'b0 
    	Parameter DMA_AXI_PROTOCOL_DEST bound to: 1 - type: integer 
    	Parameter DMA_AXI_PROTOCOL_SRC bound to: 1 - type: integer 
    	Parameter DMA_TYPE_DEST bound to: 0 - type: integer 
    	Parameter DMA_TYPE_SRC bound to: 2 - type: integer 
    	Parameter DMA_AXI_ADDR_WIDTH bound to: 30 - type: integer 
    	Parameter MAX_BYTES_PER_BURST bound to: 128 - type: integer 
    	Parameter FIFO_SIZE bound to: 8 - type: integer 
    	Parameter AXI_ID_WIDTH_SRC bound to: 1 - type: integer 
    	Parameter AXI_ID_WIDTH_DEST bound to: 1 - type: integer 
    	Parameter DMA_AXIS_ID_W bound to: 8 - type: integer 
    	Parameter DMA_AXIS_DEST_W bound to: 4 - type: integer 
    	Parameter DISABLE_DEBUG_REGISTERS bound to: 1'b0 
    	Parameter ENABLE_DIAGNOSTICS_IF bound to: 1'b0 
    	Parameter ALLOW_ASYM_MEM bound to: 1 - type: integer 
    	Parameter DMA_TYPE_AXI_MM bound to: 0 - type: integer 
    	Parameter DMA_TYPE_AXI_STREAM bound to: 1 - type: integer 
    	Parameter DMA_TYPE_FIFO bound to: 2 - type: integer 
    	Parameter HAS_DEST_ADDR bound to: 1'b1 
    	Parameter HAS_SRC_ADDR bound to: 1'b0 
    	Parameter BYTES_PER_BEAT_WIDTH_DEST bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter DBG_ID_PADDING bound to: 4 - type: integer 
    	Parameter BEATS_PER_BURST_LIMIT_DEST bound to: 16 - type: integer 
    	Parameter BYTES_PER_BURST_LIMIT_DEST bound to: 128 - type: integer 
    	Parameter BEATS_PER_BURST_LIMIT_SRC bound to: 1024 - type: integer 
    	Parameter BYTES_PER_BURST_LIMIT_SRC bound to: 8192 - type: integer 
    	Parameter BYTES_PER_BURST_LIMIT bound to: 128 - type: integer 
    	Parameter REAL_MAX_BYTES_PER_BURST bound to: 128 - type: integer 
    	Parameter DMA_LENGTH_ALIGN_SRC bound to: 3 - type: integer 
    	Parameter DMA_LENGTH_ALIGN_DEST bound to: 0 - type: integer 
    	Parameter DMA_LENGTH_ALIGN bound to: 3 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac_regmap' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_regmap.v:38]
    	Parameter ID bound to: 0 - type: integer 
    	Parameter DISABLE_DEBUG_REGISTERS bound to: 1'b0 
    	Parameter BYTES_PER_BEAT_WIDTH_DEST bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    	Parameter DMA_TYPE_DEST bound to: 0 - type: integer 
    	Parameter DMA_TYPE_SRC bound to: 2 - type: integer 
    	Parameter DMA_AXI_ADDR_WIDTH bound to: 30 - type: integer 
    	Parameter DMA_LENGTH_WIDTH bound to: 24 - type: integer 
    	Parameter DMA_LENGTH_ALIGN bound to: 3 - type: integer 
    	Parameter DMA_CYCLIC bound to: 1'b0 
    	Parameter HAS_DEST_ADDR bound to: 1'b1 
    	Parameter HAS_SRC_ADDR bound to: 1'b0 
    	Parameter DMA_2D_TRANSFER bound to: 1'b0 
    	Parameter SYNC_TRANSFER_START bound to: 1'b1 
    	Parameter PCORE_VERSION bound to: 263009 - type: integer 
    INFO: [Synth 8-155] case statement is not full and has no default [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_regmap.v:180]
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac_regmap_request' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_regmap_request.v:38]
    	Parameter DISABLE_DEBUG_REGISTERS bound to: 1'b0 
    	Parameter BYTES_PER_BEAT_WIDTH_DEST bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    	Parameter DMA_AXI_ADDR_WIDTH bound to: 30 - type: integer 
    	Parameter DMA_LENGTH_WIDTH bound to: 24 - type: integer 
    	Parameter DMA_LENGTH_ALIGN bound to: 3 - type: integer 
    	Parameter DMA_CYCLIC bound to: 1'b0 
    	Parameter HAS_DEST_ADDR bound to: 1'b1 
    	Parameter HAS_SRC_ADDR bound to: 1'b0 
    	Parameter DMA_2D_TRANSFER bound to: 1'b0 
    	Parameter SYNC_TRANSFER_START bound to: 1'b1 
    	Parameter MEASURED_LENGTH_WIDTH bound to: 24 - type: integer 
    INFO: [Synth 8-155] case statement is not full and has no default [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_regmap_request.v:148]
    INFO: [Synth 8-6157] synthesizing module 'util_axis_fifo' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/util_axis_fifo.v:38]
    	Parameter DATA_WIDTH bound to: 26 - type: integer 
    	Parameter ASYNC_CLK bound to: 0 - type: integer 
    	Parameter ADDRESS_WIDTH bound to: 2 - type: integer 
    	Parameter S_AXIS_REGISTERED bound to: 1 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'fifo_address_sync' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/address_sync.v:38]
    	Parameter ADDRESS_WIDTH bound to: 2 - type: integer 
    	Parameter MAX_ROOM bound to: 3'b100 
    INFO: [Synth 8-6155] done synthesizing module 'fifo_address_sync' (56#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/address_sync.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'util_axis_fifo' (57#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/util_axis_fifo.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac_regmap_request' (58#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_regmap_request.v:38]
    INFO: [Synth 8-6157] synthesizing module 'up_axi__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_axi.v:38]
    	Parameter AXI_ADDRESS_WIDTH bound to: 11 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_axi__parameterized0' (58#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_axi.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac_regmap' (59#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_regmap.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac_transfer' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_transfer.v:38]
    	Parameter DMA_DATA_WIDTH_SRC bound to: 64 - type: integer 
    	Parameter DMA_DATA_WIDTH_DEST bound to: 64 - type: integer 
    	Parameter DMA_LENGTH_WIDTH bound to: 24 - type: integer 
    	Parameter DMA_LENGTH_ALIGN bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_DEST bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter DMA_TYPE_DEST bound to: 0 - type: integer 
    	Parameter DMA_TYPE_SRC bound to: 2 - type: integer 
    	Parameter DMA_AXI_ADDR_WIDTH bound to: 30 - type: integer 
    	Parameter DMA_2D_TRANSFER bound to: 1'b0 
    	Parameter ASYNC_CLK_REQ_SRC bound to: 1'b1 
    	Parameter ASYNC_CLK_SRC_DEST bound to: 1'b1 
    	Parameter ASYNC_CLK_DEST_REQ bound to: 1'b0 
    	Parameter AXI_SLICE_DEST bound to: 1'b0 
    	Parameter AXI_SLICE_SRC bound to: 1'b0 
    	Parameter MAX_BYTES_PER_BURST bound to: 128 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    	Parameter FIFO_SIZE bound to: 8 - type: integer 
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter AXI_LENGTH_WIDTH_SRC bound to: 4 - type: integer 
    	Parameter AXI_LENGTH_WIDTH_DEST bound to: 4 - type: integer 
    	Parameter ENABLE_DIAGNOSTICS_IF bound to: 1'b0 
    	Parameter ALLOW_ASYM_MEM bound to: 1 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac_reset_manager' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_reset_manager.v:38]
    	Parameter ASYNC_CLK_REQ_SRC bound to: 1'b1 
    	Parameter ASYNC_CLK_SRC_DEST bound to: 1'b1 
    	Parameter ASYNC_CLK_DEST_REQ bound to: 1'b0 
    	Parameter STATE_DO_RESET bound to: 3'b000 
    	Parameter STATE_RESET bound to: 3'b001 
    	Parameter STATE_DISABLED bound to: 3'b010 
    	Parameter STATE_STARTUP bound to: 3'b011 
    	Parameter STATE_ENABLED bound to: 3'b100 
    	Parameter STATE_SHUTDOWN bound to: 3'b101 
    	Parameter GEN_ASYNC_RESET bound to: 3'b111 
    INFO: [Synth 8-155] case statement is not full and has no default [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_reset_manager.v:156]
    INFO: [Synth 8-6157] synthesizing module 'sync_bits' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cb53/sync_bits.v:46]
    	Parameter NUM_OF_BITS bound to: 1 - type: integer 
    	Parameter ASYNC_CLK bound to: 1'b0 
    INFO: [Synth 8-6155] done synthesizing module 'sync_bits' (60#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cb53/sync_bits.v:46]
    INFO: [Synth 8-6157] synthesizing module 'sync_bits__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cb53/sync_bits.v:46]
    	Parameter NUM_OF_BITS bound to: 1 - type: integer 
    	Parameter ASYNC_CLK bound to: 1'b1 
    INFO: [Synth 8-6155] done synthesizing module 'sync_bits__parameterized0' (60#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cb53/sync_bits.v:46]
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac_reset_manager' (61#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_reset_manager.v:38]
    INFO: [Synth 8-6157] synthesizing module 'dmac_request_arb' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/request_arb.v:38]
    	Parameter DMA_DATA_WIDTH_SRC bound to: 64 - type: integer 
    	Parameter DMA_DATA_WIDTH_DEST bound to: 64 - type: integer 
    	Parameter DMA_LENGTH_WIDTH bound to: 24 - type: integer 
    	Parameter DMA_LENGTH_ALIGN bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_DEST bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter DMA_TYPE_DEST bound to: 0 - type: integer 
    	Parameter DMA_TYPE_SRC bound to: 2 - type: integer 
    	Parameter DMA_AXI_ADDR_WIDTH bound to: 30 - type: integer 
    	Parameter ASYNC_CLK_REQ_SRC bound to: 1'b1 
    	Parameter ASYNC_CLK_SRC_DEST bound to: 1'b1 
    	Parameter ASYNC_CLK_DEST_REQ bound to: 1'b0 
    	Parameter AXI_SLICE_DEST bound to: 1'b0 
    	Parameter AXI_SLICE_SRC bound to: 1'b0 
    	Parameter MAX_BYTES_PER_BURST bound to: 128 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    	Parameter FIFO_SIZE bound to: 8 - type: integer 
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter AXI_LENGTH_WIDTH_SRC bound to: 4 - type: integer 
    	Parameter AXI_LENGTH_WIDTH_DEST bound to: 4 - type: integer 
    	Parameter ENABLE_DIAGNOSTICS_IF bound to: 1'b0 
    	Parameter ALLOW_ASYM_MEM bound to: 1 - type: integer 
    	Parameter DMA_TYPE_MM_AXI bound to: 0 - type: integer 
    	Parameter DMA_TYPE_STREAM_AXI bound to: 1 - type: integer 
    	Parameter DMA_TYPE_FIFO bound to: 2 - type: integer 
    	Parameter DMA_ADDRESS_WIDTH_DEST bound to: 27 - type: integer 
    	Parameter DMA_ADDRESS_WIDTH_SRC bound to: 27 - type: integer 
    	Parameter BEATS_PER_BURST_WIDTH_SRC bound to: 4 - type: integer 
    	Parameter BEATS_PER_BURST_WIDTH_DEST bound to: 4 - type: integer 
    	Parameter BURSTS_PER_TRANSFER_WIDTH bound to: 17 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'dmac_dest_mm_axi' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/dest_axi_mm.v:38]
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter DMA_DATA_WIDTH bound to: 64 - type: integer 
    	Parameter DMA_ADDR_WIDTH bound to: 30 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH bound to: 3 - type: integer 
    	Parameter BEATS_PER_BURST_WIDTH bound to: 4 - type: integer 
    	Parameter MAX_BYTES_PER_BURST bound to: 128 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    	Parameter AXI_LENGTH_WIDTH bound to: 4 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'dmac_address_generator' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/address_generator.v:38]
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter DMA_DATA_WIDTH bound to: 64 - type: integer 
    	Parameter DMA_ADDR_WIDTH bound to: 30 - type: integer 
    	Parameter BEATS_PER_BURST_WIDTH bound to: 4 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH bound to: 3 - type: integer 
    	Parameter LENGTH_WIDTH bound to: 4 - type: integer 
    	Parameter MAX_BEATS_PER_BURST bound to: 5'b10000 
    	Parameter MAX_LENGTH bound to: 4'b1111 
    INFO: [Synth 8-6155] done synthesizing module 'dmac_address_generator' (62#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/address_generator.v:38]
    INFO: [Synth 8-6157] synthesizing module 'dmac_response_handler' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/response_handler.v:38]
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter RESP_OKAY bound to: 2'b00 
    	Parameter RESP_EXOKAY bound to: 2'b01 
    	Parameter RESP_SLVERR bound to: 2'b10 
    	Parameter RESP_DECERR bound to: 2'b11 
    INFO: [Synth 8-6155] done synthesizing module 'dmac_response_handler' (63#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/response_handler.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'dmac_dest_mm_axi' (64#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/dest_axi_mm.v:38]
    INFO: [Synth 8-6157] synthesizing module 'util_axis_fifo__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/util_axis_fifo.v:38]
    	Parameter DATA_WIDTH bound to: 4 - type: integer 
    	Parameter ASYNC_CLK bound to: 1'b1 
    	Parameter ADDRESS_WIDTH bound to: 0 - type: integer 
    	Parameter S_AXIS_REGISTERED bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'util_axis_fifo__parameterized0' (64#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/util_axis_fifo.v:38]
    INFO: [Synth 8-6157] synthesizing module 'dmac_src_fifo_inf' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/src_fifo_inf.v:38]
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter DATA_WIDTH bound to: 64 - type: integer 
    	Parameter BEATS_PER_BURST_WIDTH bound to: 4 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'dmac_data_mover' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/data_mover.v:38]
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter DATA_WIDTH bound to: 64 - type: integer 
    	Parameter BEATS_PER_BURST_WIDTH bound to: 4 - type: integer 
    	Parameter ALLOW_ABORT bound to: 0 - type: integer 
    	Parameter BEAT_COUNTER_MAX bound to: 4'b1111 
    INFO: [Synth 8-6155] done synthesizing module 'dmac_data_mover' (65#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/data_mover.v:38]
    WARNING: [Synth 8-7023] instance 'i_data_mover' of module 'dmac_data_mover' has 29 connections declared, but only 22 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/src_fifo_inf.v:94]
    INFO: [Synth 8-6155] done synthesizing module 'dmac_src_fifo_inf' (66#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/src_fifo_inf.v:38]
    INFO: [Synth 8-6157] synthesizing module 'sync_bits__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cb53/sync_bits.v:46]
    	Parameter NUM_OF_BITS bound to: 4 - type: integer 
    	Parameter ASYNC_CLK bound to: 1'b1 
    INFO: [Synth 8-6155] done synthesizing module 'sync_bits__parameterized1' (66#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cb53/sync_bits.v:46]
    INFO: [Synth 8-6157] synthesizing module 'sync_event' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cb53/sync_event.v:38]
    	Parameter NUM_OF_EVENTS bound to: 1 - type: integer 
    	Parameter ASYNC_CLK bound to: 1'b1 
    INFO: [Synth 8-6157] synthesizing module 'sync_bits__parameterized2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cb53/sync_bits.v:46]
    	Parameter NUM_OF_BITS bound to: 1 - type: integer 
    	Parameter ASYNC_CLK bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'sync_bits__parameterized2' (66#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cb53/sync_bits.v:46]
    INFO: [Synth 8-6155] done synthesizing module 'sync_event' (67#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cb53/sync_event.v:38]
    INFO: [Synth 8-6157] synthesizing module 'sync_bits__parameterized3' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cb53/sync_bits.v:46]
    	Parameter NUM_OF_BITS bound to: 4 - type: integer 
    	Parameter ASYNC_CLK bound to: 1'b0 
    INFO: [Synth 8-6155] done synthesizing module 'sync_bits__parameterized3' (67#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cb53/sync_bits.v:46]
    INFO: [Synth 8-6157] synthesizing module 'axi_register_slice' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_register_slice.v:38]
    	Parameter DATA_WIDTH bound to: 69 - type: integer 
    	Parameter FORWARD_REGISTERED bound to: 1'b0 
    	Parameter BACKWARD_REGISTERED bound to: 0 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice' (68#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_register_slice.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac_burst_memory' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_burst_memory.v:38]
    	Parameter DATA_WIDTH_SRC bound to: 64 - type: integer 
    	Parameter DATA_WIDTH_DEST bound to: 64 - type: integer 
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter MAX_BYTES_PER_BURST bound to: 128 - type: integer 
    	Parameter ASYNC_CLK bound to: 1'b1 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    	Parameter DMA_LENGTH_ALIGN bound to: 3 - type: integer 
    	Parameter ENABLE_DIAGNOSTICS_IF bound to: 1'b0 
    	Parameter ALLOW_ASYM_MEM bound to: 1 - type: integer 
    	Parameter DATA_WIDTH_MEM bound to: 64 - type: integer 
    	Parameter MEM_RATIO bound to: 1 - type: integer 
    	Parameter BURST_LEN bound to: 16 - type: integer 
    	Parameter BURST_LEN_WIDTH bound to: 4 - type: integer 
    	Parameter AUX_FIFO_SIZE bound to: 8 - type: integer 
    	Parameter MEM_RATIO_WIDTH bound to: 0 - type: integer 
    	Parameter BURST_LEN_WIDTH_SRC bound to: 4 - type: integer 
    	Parameter BURST_LEN_WIDTH_DEST bound to: 4 - type: integer 
    	Parameter DATA_WIDTH_MEM_SRC bound to: 64 - type: integer 
    	Parameter DATA_WIDTH_MEM_DEST bound to: 64 - type: integer 
    	Parameter ADDRESS_WIDTH_SRC bound to: 7 - type: integer 
    	Parameter ADDRESS_WIDTH_DEST bound to: 7 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_MEM_SRC bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_DEST bound to: 3 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac_resize_src' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_resize_src.v:43]
    	Parameter DATA_WIDTH_SRC bound to: 64 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter DATA_WIDTH_MEM bound to: 64 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_MEM bound to: 3 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac_resize_src' (69#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_resize_src.v:43]
    INFO: [Synth 8-6157] synthesizing module 'ad_mem_asym' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_mem_asym.v:41]
    	Parameter A_ADDRESS_WIDTH bound to: 7 - type: integer 
    	Parameter A_DATA_WIDTH bound to: 64 - type: integer 
    	Parameter B_ADDRESS_WIDTH bound to: 7 - type: integer 
    	Parameter B_DATA_WIDTH bound to: 64 - type: integer 
    	Parameter MEM_ADDRESS_WIDTH bound to: 7 - type: integer 
    	Parameter MIN_WIDTH bound to: 64 - type: integer 
    	Parameter MAX_WIDTH bound to: 64 - type: integer 
    	Parameter MEM_DATA_WIDTH bound to: 64 - type: integer 
    	Parameter MEM_SIZE bound to: 128 - type: integer 
    	Parameter MEM_RATIO bound to: 1 - type: integer 
    	Parameter MEM_RATIO_LOG2 bound to: 1 - type: integer 
    INFO: [Synth 8-5534] Detected attribute (* ram_style = "block" *) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_mem_asym.v:86]
    INFO: [Synth 8-6155] done synthesizing module 'ad_mem_asym' (70#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_mem_asym.v:41]
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac_resize_dest' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_resize_dest.v:38]
    	Parameter DATA_WIDTH_DEST bound to: 64 - type: integer 
    	Parameter DATA_WIDTH_MEM bound to: 64 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac_resize_dest' (71#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_resize_dest.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac_burst_memory' (72#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_burst_memory.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_register_slice__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_register_slice.v:38]
    	Parameter DATA_WIDTH bound to: 73 - type: integer 
    	Parameter FORWARD_REGISTERED bound to: 1'b0 
    	Parameter BACKWARD_REGISTERED bound to: 1'b0 
    INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice__parameterized0' (72#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_register_slice.v:38]
    INFO: [Synth 8-6157] synthesizing module 'util_axis_fifo__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/util_axis_fifo.v:38]
    	Parameter DATA_WIDTH bound to: 28 - type: integer 
    	Parameter ASYNC_CLK bound to: 1'b1 
    	Parameter ADDRESS_WIDTH bound to: 0 - type: integer 
    	Parameter S_AXIS_REGISTERED bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'util_axis_fifo__parameterized1' (72#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/util_axis_fifo.v:38]
    INFO: [Synth 8-6157] synthesizing module 'util_axis_fifo__parameterized2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/util_axis_fifo.v:38]
    	Parameter DATA_WIDTH bound to: 63 - type: integer 
    	Parameter ASYNC_CLK bound to: 1'b1 
    	Parameter ADDRESS_WIDTH bound to: 0 - type: integer 
    	Parameter S_AXIS_REGISTERED bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'util_axis_fifo__parameterized2' (72#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/util_axis_fifo.v:38]
    INFO: [Synth 8-6157] synthesizing module 'dmac_request_generator' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/request_generator.v:38]
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter BURSTS_PER_TRANSFER_WIDTH bound to: 17 - type: integer 
    	Parameter STATE_IDLE bound to: 3'b000 
    	Parameter STATE_GEN_ID bound to: 3'b001 
    	Parameter STATE_REWIND_ID bound to: 3'b010 
    	Parameter STATE_CONSUME bound to: 3'b011 
    	Parameter STATE_WAIT_LAST bound to: 3'b100 
    INFO: [Synth 8-6155] done synthesizing module 'dmac_request_generator' (73#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/request_generator.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac_response_manager' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_response_manager.v:38]
    	Parameter DMA_DATA_WIDTH_SRC bound to: 64 - type: integer 
    	Parameter DMA_DATA_WIDTH_DEST bound to: 64 - type: integer 
    	Parameter DMA_LENGTH_WIDTH bound to: 24 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter ASYNC_CLK_DEST_REQ bound to: 1'b0 
    	Parameter STATE_IDLE bound to: 3'b000 
    	Parameter STATE_ACC bound to: 3'b001 
    	Parameter STATE_WRITE_RESPR bound to: 3'b010 
    	Parameter STATE_ZERO_COMPL bound to: 3'b011 
    	Parameter STATE_WRITE_ZRCMPL bound to: 3'b100 
    	Parameter DEST_SRC_RATIO bound to: 1 - type: integer 
    	Parameter DEST_SRC_RATIO_WIDTH bound to: 0 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH bound to: 3 - type: integer 
    	Parameter BURST_LEN_WIDTH bound to: 4 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'util_axis_fifo__parameterized3' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/util_axis_fifo.v:38]
    	Parameter DATA_WIDTH bound to: 9 - type: integer 
    	Parameter ASYNC_CLK bound to: 1'b0 
    	Parameter ADDRESS_WIDTH bound to: 0 - type: integer 
    	Parameter S_AXIS_REGISTERED bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'util_axis_fifo__parameterized3' (73#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/util_axis_fifo.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac_response_manager' (74#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_response_manager.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'dmac_request_arb' (75#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/request_arb.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac_transfer' (76#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_transfer.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac' (77#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'system_axi_ad9361_adc_dma_0' (78#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_adc_dma_0/synth/system_axi_ad9361_adc_dma_0.v:57]
    WARNING: [Synth 8-7023] instance 'axi_ad9361_adc_dma' of module 'system_axi_ad9361_adc_dma_0' has 46 connections declared, but only 45 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:3005]
    INFO: [Synth 8-6157] synthesizing module 'system_axi_ad9361_dac_dma_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_dma_0/synth/system_axi_ad9361_dac_dma_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac.v:38]
    	Parameter ID bound to: 0 - type: integer 
    	Parameter DMA_DATA_WIDTH_SRC bound to: 64 - type: integer 
    	Parameter DMA_DATA_WIDTH_DEST bound to: 64 - type: integer 
    	Parameter DMA_LENGTH_WIDTH bound to: 24 - type: integer 
    	Parameter DMA_2D_TRANSFER bound to: 1'b0 
    	Parameter ASYNC_CLK_REQ_SRC bound to: 1'b0 
    	Parameter ASYNC_CLK_SRC_DEST bound to: 1'b1 
    	Parameter ASYNC_CLK_DEST_REQ bound to: 1'b1 
    	Parameter AXI_SLICE_DEST bound to: 1'b0 
    	Parameter AXI_SLICE_SRC bound to: 1'b0 
    	Parameter SYNC_TRANSFER_START bound to: 1'b0 
    	Parameter CYCLIC bound to: 1'b1 
    	Parameter DMA_AXI_PROTOCOL_DEST bound to: 1 - type: integer 
    	Parameter DMA_AXI_PROTOCOL_SRC bound to: 1 - type: integer 
    	Parameter DMA_TYPE_DEST bound to: 1 - type: integer 
    	Parameter DMA_TYPE_SRC bound to: 0 - type: integer 
    	Parameter DMA_AXI_ADDR_WIDTH bound to: 30 - type: integer 
    	Parameter MAX_BYTES_PER_BURST bound to: 128 - type: integer 
    	Parameter FIFO_SIZE bound to: 8 - type: integer 
    	Parameter AXI_ID_WIDTH_SRC bound to: 1 - type: integer 
    	Parameter AXI_ID_WIDTH_DEST bound to: 1 - type: integer 
    	Parameter DMA_AXIS_ID_W bound to: 8 - type: integer 
    	Parameter DMA_AXIS_DEST_W bound to: 4 - type: integer 
    	Parameter DISABLE_DEBUG_REGISTERS bound to: 1'b0 
    	Parameter ENABLE_DIAGNOSTICS_IF bound to: 1'b0 
    	Parameter ALLOW_ASYM_MEM bound to: 1 - type: integer 
    	Parameter DMA_TYPE_AXI_MM bound to: 0 - type: integer 
    	Parameter DMA_TYPE_AXI_STREAM bound to: 1 - type: integer 
    	Parameter DMA_TYPE_FIFO bound to: 2 - type: integer 
    	Parameter HAS_DEST_ADDR bound to: 1'b0 
    	Parameter HAS_SRC_ADDR bound to: 1'b1 
    	Parameter BYTES_PER_BEAT_WIDTH_DEST bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter DBG_ID_PADDING bound to: 4 - type: integer 
    	Parameter BEATS_PER_BURST_LIMIT_DEST bound to: 1024 - type: integer 
    	Parameter BYTES_PER_BURST_LIMIT_DEST bound to: 8192 - type: integer 
    	Parameter BEATS_PER_BURST_LIMIT_SRC bound to: 16 - type: integer 
    	Parameter BYTES_PER_BURST_LIMIT_SRC bound to: 128 - type: integer 
    	Parameter BYTES_PER_BURST_LIMIT bound to: 128 - type: integer 
    	Parameter REAL_MAX_BYTES_PER_BURST bound to: 128 - type: integer 
    	Parameter DMA_LENGTH_ALIGN_SRC bound to: 0 - type: integer 
    	Parameter DMA_LENGTH_ALIGN_DEST bound to: 3 - type: integer 
    	Parameter DMA_LENGTH_ALIGN bound to: 3 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac_regmap__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_regmap.v:38]
    	Parameter ID bound to: 0 - type: integer 
    	Parameter DISABLE_DEBUG_REGISTERS bound to: 1'b0 
    	Parameter BYTES_PER_BEAT_WIDTH_DEST bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    	Parameter DMA_TYPE_DEST bound to: 1 - type: integer 
    	Parameter DMA_TYPE_SRC bound to: 0 - type: integer 
    	Parameter DMA_AXI_ADDR_WIDTH bound to: 30 - type: integer 
    	Parameter DMA_LENGTH_WIDTH bound to: 24 - type: integer 
    	Parameter DMA_LENGTH_ALIGN bound to: 3 - type: integer 
    	Parameter DMA_CYCLIC bound to: 1'b1 
    	Parameter HAS_DEST_ADDR bound to: 1'b0 
    	Parameter HAS_SRC_ADDR bound to: 1'b1 
    	Parameter DMA_2D_TRANSFER bound to: 1'b0 
    	Parameter SYNC_TRANSFER_START bound to: 1'b0 
    	Parameter PCORE_VERSION bound to: 263009 - type: integer 
    INFO: [Synth 8-155] case statement is not full and has no default [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_regmap.v:180]
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac_regmap_request__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_regmap_request.v:38]
    	Parameter DISABLE_DEBUG_REGISTERS bound to: 1'b0 
    	Parameter BYTES_PER_BEAT_WIDTH_DEST bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    	Parameter DMA_AXI_ADDR_WIDTH bound to: 30 - type: integer 
    	Parameter DMA_LENGTH_WIDTH bound to: 24 - type: integer 
    	Parameter DMA_LENGTH_ALIGN bound to: 3 - type: integer 
    	Parameter DMA_CYCLIC bound to: 1'b1 
    	Parameter HAS_DEST_ADDR bound to: 1'b0 
    	Parameter HAS_SRC_ADDR bound to: 1'b1 
    	Parameter DMA_2D_TRANSFER bound to: 1'b0 
    	Parameter SYNC_TRANSFER_START bound to: 1'b0 
    	Parameter MEASURED_LENGTH_WIDTH bound to: 24 - type: integer 
    INFO: [Synth 8-155] case statement is not full and has no default [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_regmap_request.v:148]
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac_regmap_request__parameterized0' (78#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_regmap_request.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac_regmap__parameterized0' (78#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_regmap.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac_transfer__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_transfer.v:38]
    	Parameter DMA_DATA_WIDTH_SRC bound to: 64 - type: integer 
    	Parameter DMA_DATA_WIDTH_DEST bound to: 64 - type: integer 
    	Parameter DMA_LENGTH_WIDTH bound to: 24 - type: integer 
    	Parameter DMA_LENGTH_ALIGN bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_DEST bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter DMA_TYPE_DEST bound to: 1 - type: integer 
    	Parameter DMA_TYPE_SRC bound to: 0 - type: integer 
    	Parameter DMA_AXI_ADDR_WIDTH bound to: 30 - type: integer 
    	Parameter DMA_2D_TRANSFER bound to: 1'b0 
    	Parameter ASYNC_CLK_REQ_SRC bound to: 1'b0 
    	Parameter ASYNC_CLK_SRC_DEST bound to: 1'b1 
    	Parameter ASYNC_CLK_DEST_REQ bound to: 1'b1 
    	Parameter AXI_SLICE_DEST bound to: 1'b0 
    	Parameter AXI_SLICE_SRC bound to: 1'b0 
    	Parameter MAX_BYTES_PER_BURST bound to: 128 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    	Parameter FIFO_SIZE bound to: 8 - type: integer 
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter AXI_LENGTH_WIDTH_SRC bound to: 4 - type: integer 
    	Parameter AXI_LENGTH_WIDTH_DEST bound to: 4 - type: integer 
    	Parameter ENABLE_DIAGNOSTICS_IF bound to: 1'b0 
    	Parameter ALLOW_ASYM_MEM bound to: 1 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac_reset_manager__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_reset_manager.v:38]
    	Parameter ASYNC_CLK_REQ_SRC bound to: 1'b0 
    	Parameter ASYNC_CLK_SRC_DEST bound to: 1'b1 
    	Parameter ASYNC_CLK_DEST_REQ bound to: 1'b1 
    	Parameter STATE_DO_RESET bound to: 3'b000 
    	Parameter STATE_RESET bound to: 3'b001 
    	Parameter STATE_DISABLED bound to: 3'b010 
    	Parameter STATE_STARTUP bound to: 3'b011 
    	Parameter STATE_ENABLED bound to: 3'b100 
    	Parameter STATE_SHUTDOWN bound to: 3'b101 
    	Parameter GEN_ASYNC_RESET bound to: 3'b011 
    INFO: [Synth 8-155] case statement is not full and has no default [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_reset_manager.v:156]
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac_reset_manager__parameterized0' (78#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_reset_manager.v:38]
    INFO: [Synth 8-6157] synthesizing module 'dmac_request_arb__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/request_arb.v:38]
    	Parameter DMA_DATA_WIDTH_SRC bound to: 64 - type: integer 
    	Parameter DMA_DATA_WIDTH_DEST bound to: 64 - type: integer 
    	Parameter DMA_LENGTH_WIDTH bound to: 24 - type: integer 
    	Parameter DMA_LENGTH_ALIGN bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_DEST bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter DMA_TYPE_DEST bound to: 1 - type: integer 
    	Parameter DMA_TYPE_SRC bound to: 0 - type: integer 
    	Parameter DMA_AXI_ADDR_WIDTH bound to: 30 - type: integer 
    	Parameter ASYNC_CLK_REQ_SRC bound to: 1'b0 
    	Parameter ASYNC_CLK_SRC_DEST bound to: 1'b1 
    	Parameter ASYNC_CLK_DEST_REQ bound to: 1'b1 
    	Parameter AXI_SLICE_DEST bound to: 1'b0 
    	Parameter AXI_SLICE_SRC bound to: 1'b0 
    	Parameter MAX_BYTES_PER_BURST bound to: 128 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    	Parameter FIFO_SIZE bound to: 8 - type: integer 
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter AXI_LENGTH_WIDTH_SRC bound to: 4 - type: integer 
    	Parameter AXI_LENGTH_WIDTH_DEST bound to: 4 - type: integer 
    	Parameter ENABLE_DIAGNOSTICS_IF bound to: 1'b0 
    	Parameter ALLOW_ASYM_MEM bound to: 1 - type: integer 
    	Parameter DMA_TYPE_MM_AXI bound to: 0 - type: integer 
    	Parameter DMA_TYPE_STREAM_AXI bound to: 1 - type: integer 
    	Parameter DMA_TYPE_FIFO bound to: 2 - type: integer 
    	Parameter DMA_ADDRESS_WIDTH_DEST bound to: 27 - type: integer 
    	Parameter DMA_ADDRESS_WIDTH_SRC bound to: 27 - type: integer 
    	Parameter BEATS_PER_BURST_WIDTH_SRC bound to: 4 - type: integer 
    	Parameter BEATS_PER_BURST_WIDTH_DEST bound to: 4 - type: integer 
    	Parameter BURSTS_PER_TRANSFER_WIDTH bound to: 17 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'dmac_dest_axi_stream' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/dest_axi_stream.v:38]
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter S_AXIS_DATA_WIDTH bound to: 64 - type: integer 
    	Parameter BEATS_PER_BURST_WIDTH bound to: 4 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'dmac_response_generator' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/response_generator.v:38]
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter RESP_OKAY bound to: 2'b00 
    	Parameter RESP_EXOKAY bound to: 2'b01 
    	Parameter RESP_SLVERR bound to: 2'b10 
    	Parameter RESP_DECERR bound to: 2'b11 
    INFO: [Synth 8-6155] done synthesizing module 'dmac_response_generator' (79#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/response_generator.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'dmac_dest_axi_stream' (80#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/dest_axi_stream.v:38]
    INFO: [Synth 8-6157] synthesizing module 'dmac_src_mm_axi' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/src_axi_mm.v:38]
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter DMA_DATA_WIDTH bound to: 64 - type: integer 
    	Parameter DMA_ADDR_WIDTH bound to: 30 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH bound to: 3 - type: integer 
    	Parameter BEATS_PER_BURST_WIDTH bound to: 4 - type: integer 
    	Parameter AXI_LENGTH_WIDTH bound to: 4 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'splitter' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/splitter.v:38]
    	Parameter NUM_M bound to: 3 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'splitter' (81#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/splitter.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'dmac_src_mm_axi' (82#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/src_axi_mm.v:38]
    INFO: [Synth 8-6157] synthesizing module 'sync_event__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cb53/sync_event.v:38]
    	Parameter NUM_OF_EVENTS bound to: 1 - type: integer 
    	Parameter ASYNC_CLK bound to: 1'b0 
    INFO: [Synth 8-6155] done synthesizing module 'sync_event__parameterized0' (82#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cb53/sync_event.v:38]
    INFO: [Synth 8-6157] synthesizing module 'util_axis_fifo__parameterized4' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/util_axis_fifo.v:38]
    	Parameter DATA_WIDTH bound to: 63 - type: integer 
    	Parameter ASYNC_CLK bound to: 1'b0 
    	Parameter ADDRESS_WIDTH bound to: 0 - type: integer 
    	Parameter S_AXIS_REGISTERED bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'util_axis_fifo__parameterized4' (82#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/util_axis_fifo.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac_response_manager__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_response_manager.v:38]
    	Parameter DMA_DATA_WIDTH_SRC bound to: 64 - type: integer 
    	Parameter DMA_DATA_WIDTH_DEST bound to: 64 - type: integer 
    	Parameter DMA_LENGTH_WIDTH bound to: 24 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter ASYNC_CLK_DEST_REQ bound to: 1'b1 
    	Parameter STATE_IDLE bound to: 3'b000 
    	Parameter STATE_ACC bound to: 3'b001 
    	Parameter STATE_WRITE_RESPR bound to: 3'b010 
    	Parameter STATE_ZERO_COMPL bound to: 3'b011 
    	Parameter STATE_WRITE_ZRCMPL bound to: 3'b100 
    	Parameter DEST_SRC_RATIO bound to: 1 - type: integer 
    	Parameter DEST_SRC_RATIO_WIDTH bound to: 0 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH bound to: 3 - type: integer 
    	Parameter BURST_LEN_WIDTH bound to: 4 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'util_axis_fifo__parameterized5' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/util_axis_fifo.v:38]
    	Parameter DATA_WIDTH bound to: 9 - type: integer 
    	Parameter ASYNC_CLK bound to: 1'b1 
    	Parameter ADDRESS_WIDTH bound to: 0 - type: integer 
    	Parameter S_AXIS_REGISTERED bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'util_axis_fifo__parameterized5' (82#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/util_axis_fifo.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac_response_manager__parameterized0' (82#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_response_manager.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'dmac_request_arb__parameterized0' (82#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/request_arb.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac_transfer__parameterized0' (82#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_transfer.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac__parameterized0' (82#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'system_axi_ad9361_dac_dma_0' (83#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_dma_0/synth/system_axi_ad9361_dac_dma_0.v:57]
    WARNING: [Synth 8-7023] instance 'axi_ad9361_dac_dma' of module 'system_axi_ad9361_dac_dma_0' has 48 connections declared, but only 41 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:3051]
    INFO: [Synth 8-6157] synthesizing module 'system_axi_ad9361_dac_fifo_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_fifo_0/synth/system_axi_ad9361_dac_fifo_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'util_rfifo' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c5cc/util_rfifo.v:38]
    	Parameter NUM_OF_CHANNELS bound to: 4 - type: integer 
    	Parameter DIN_DATA_WIDTH bound to: 16 - type: integer 
    	Parameter DOUT_DATA_WIDTH bound to: 16 - type: integer 
    	Parameter DIN_ADDRESS_WIDTH bound to: 4 - type: integer 
    	Parameter M_MEM_RATIO bound to: 1 - type: integer 
    	Parameter ADDRESS_WIDTH bound to: 5 - type: integer 
    	Parameter DATA_WIDTH bound to: 64 - type: integer 
    	Parameter T_DIN_DATA_WIDTH bound to: 128 - type: integer 
    	Parameter T_DOUT_DATA_WIDTH bound to: 128 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'ad_mem' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_mem.v:38]
    	Parameter DATA_WIDTH bound to: 64 - type: integer 
    	Parameter ADDRESS_WIDTH bound to: 5 - type: integer 
    INFO: [Synth 8-5534] Detected attribute (* ram_style = "block" *) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_mem.v:54]
    INFO: [Synth 8-6155] done synthesizing module 'ad_mem' (84#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_mem.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'util_rfifo' (85#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c5cc/util_rfifo.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'system_axi_ad9361_dac_fifo_0' (86#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_fifo_0/synth/system_axi_ad9361_dac_fifo_0.v:57]
    WARNING: [Synth 8-7023] instance 'axi_ad9361_dac_fifo' of module 'system_axi_ad9361_dac_fifo_0' has 38 connections declared, but only 31 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:3093]
    INFO: [Synth 8-6157] synthesizing module 'system_axi_cpu_interconnect_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:4200]
    INFO: [Synth 8-6157] synthesizing module 'm00_couplers_imp_I5GH1N' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:12]
    INFO: [Synth 8-6155] done synthesizing module 'm00_couplers_imp_I5GH1N' (87#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:12]
    INFO: [Synth 8-6157] synthesizing module 'm01_couplers_imp_1UBGIXM' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:158]
    INFO: [Synth 8-6155] done synthesizing module 'm01_couplers_imp_1UBGIXM' (88#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:158]
    INFO: [Synth 8-6157] synthesizing module 'm02_couplers_imp_1J5P44O' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:290]
    INFO: [Synth 8-6155] done synthesizing module 'm02_couplers_imp_1J5P44O' (89#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:290]
    INFO: [Synth 8-6157] synthesizing module 'm03_couplers_imp_T17W6X' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:436]
    INFO: [Synth 8-6155] done synthesizing module 'm03_couplers_imp_T17W6X' (90#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:436]
    INFO: [Synth 8-6157] synthesizing module 'm04_couplers_imp_15FU5SC' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:582]
    INFO: [Synth 8-6155] done synthesizing module 'm04_couplers_imp_15FU5SC' (91#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:582]
    INFO: [Synth 8-6157] synthesizing module 'm05_couplers_imp_GFBASD' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:728]
    INFO: [Synth 8-6155] done synthesizing module 'm05_couplers_imp_GFBASD' (92#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:728]
    INFO: [Synth 8-6157] synthesizing module 'm06_couplers_imp_59JXRJ' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:874]
    INFO: [Synth 8-6155] done synthesizing module 'm06_couplers_imp_59JXRJ' (93#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:874]
    INFO: [Synth 8-6157] synthesizing module 'm07_couplers_imp_1GBLMBI' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:1020]
    INFO: [Synth 8-6155] done synthesizing module 'm07_couplers_imp_1GBLMBI' (94#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:1020]
    INFO: [Synth 8-6157] synthesizing module 'm08_couplers_imp_E05M9W' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:1166]
    INFO: [Synth 8-6155] done synthesizing module 'm08_couplers_imp_E05M9W' (95#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:1166]
    INFO: [Synth 8-6157] synthesizing module 'm09_couplers_imp_17AVPN9' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:1312]
    INFO: [Synth 8-6155] done synthesizing module 'm09_couplers_imp_17AVPN9' (96#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:1312]
    INFO: [Synth 8-6157] synthesizing module 'm10_couplers_imp_1J5SI6G' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:1458]
    INFO: [Synth 8-6155] done synthesizing module 'm10_couplers_imp_1J5SI6G' (97#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:1458]
    INFO: [Synth 8-6157] synthesizing module 'm11_couplers_imp_T19VO9' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:1604]
    INFO: [Synth 8-6155] done synthesizing module 'm11_couplers_imp_T19VO9' (98#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:1604]
    INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_WZLZH6' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:1750]
    INFO: [Synth 8-6157] synthesizing module 'system_auto_pc_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:58]
    INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_19_axi_protocol_converter' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4808]
    	Parameter C_FAMILY bound to: zynq - type: string 
    	Parameter C_M_AXI_PROTOCOL bound to: 2 - type: integer 
    	Parameter C_S_AXI_PROTOCOL bound to: 1 - type: integer 
    	Parameter C_IGNORE_ID bound to: 0 - type: integer 
    	Parameter C_AXI_ID_WIDTH bound to: 12 - type: integer 
    	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer 
    	Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer 
    	Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer 
    	Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_TRANSLATION_MODE bound to: 2 - type: integer 
    	Parameter P_AXI4 bound to: 0 - type: integer 
    	Parameter P_AXI3 bound to: 1 - type: integer 
    	Parameter P_AXILITE bound to: 2 - type: integer 
    	Parameter P_AXILITE_SIZE bound to: 3'b010 
    	Parameter P_INCR bound to: 2'b01 
    	Parameter P_DECERR bound to: 2'b11 
    	Parameter P_SLVERR bound to: 2'b10 
    	Parameter P_PROTECTION bound to: 1 - type: integer 
    	Parameter P_CONVERSION bound to: 2 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_19_b2s' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4226]
    	Parameter C_S_AXI_PROTOCOL bound to: 1 - type: integer 
    	Parameter C_AXI_ID_WIDTH bound to: 12 - type: integer 
    	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer 
    	Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_19_b2s_aw_channel' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3971]
    	Parameter C_ID_WIDTH bound to: 12 - type: integer 
    	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_19_b2s_cmd_translator' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3464]
    	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
    	Parameter P_AXBURST_FIXED bound to: 2'b00 
    	Parameter P_AXBURST_INCR bound to: 2'b01 
    	Parameter P_AXBURST_WRAP bound to: 2'b10 
    INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_19_b2s_incr_cmd' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3092]
    	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
    	Parameter L_AXI_ADDR_LOW_BIT bound to: 12 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_19_b2s_incr_cmd' (99#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3092]
    INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_19_b2s_wrap_cmd' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2902]
    	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
    	Parameter L_AXI_ADDR_LOW_BIT bound to: 12 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_19_b2s_wrap_cmd' (100#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2902]
    INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_19_b2s_cmd_translator' (101#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3464]
    INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_19_b2s_wr_cmd_fsm' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3224]
    	Parameter SM_IDLE bound to: 2'b00 
    	Parameter SM_CMD_EN bound to: 2'b01 
    	Parameter SM_CMD_ACCEPTED bound to: 2'b10 
    	Parameter SM_DONE_WAIT bound to: 2'b11 
    INFO: [Synth 8-226] default block is never used [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3277]
    INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_19_b2s_wr_cmd_fsm' (102#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3224]
    INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_19_b2s_aw_channel' (103#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3971]
    INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_19_b2s_b_channel' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3606]
    	Parameter C_ID_WIDTH bound to: 12 - type: integer 
    	Parameter LP_RESP_OKAY bound to: 2'b00 
    	Parameter LP_RESP_EXOKAY bound to: 2'b01 
    	Parameter LP_RESP_SLVERROR bound to: 2'b10 
    	Parameter LP_RESP_DECERR bound to: 2'b11 
    	Parameter P_WIDTH bound to: 20 - type: integer 
    	Parameter P_DEPTH bound to: 4 - type: integer 
    	Parameter P_AWIDTH bound to: 2 - type: integer 
    	Parameter P_RWIDTH bound to: 2 - type: integer 
    	Parameter P_RDEPTH bound to: 4 - type: integer 
    	Parameter P_RAWIDTH bound to: 2 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_19_b2s_simple_fifo' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816]
    	Parameter C_WIDTH bound to: 20 - type: integer 
    	Parameter C_AWIDTH bound to: 2 - type: integer 
    	Parameter C_DEPTH bound to: 4 - type: integer 
    	Parameter C_EMPTY bound to: 2'b11 
    	Parameter C_EMPTY_PRE bound to: 2'b00 
    	Parameter C_FULL bound to: 2'b10 
    	Parameter C_FULL_PRE bound to: 2'b01 
    INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_19_b2s_simple_fifo' (104#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816]
    INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816]
    	Parameter C_WIDTH bound to: 2 - type: integer 
    	Parameter C_AWIDTH bound to: 2 - type: integer 
    	Parameter C_DEPTH bound to: 4 - type: integer 
    	Parameter C_EMPTY bound to: 2'b11 
    	Parameter C_EMPTY_PRE bound to: 2'b00 
    	Parameter C_FULL bound to: 2'b10 
    	Parameter C_FULL_PRE bound to: 2'b01 
    INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized0' (104#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816]
    INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_19_b2s_b_channel' (105#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3606]
    INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_19_b2s_ar_channel' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4082]
    	Parameter C_ID_WIDTH bound to: 12 - type: integer 
    	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_19_b2s_rd_cmd_fsm' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3334]
    	Parameter SM_IDLE bound to: 2'b00 
    	Parameter SM_CMD_EN bound to: 2'b01 
    	Parameter SM_CMD_ACCEPTED bound to: 2'b10 
    	Parameter SM_DONE bound to: 2'b11 
    INFO: [Synth 8-226] default block is never used [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3395]
    WARNING: [Synth 8-6014] Unused sequential element state_r1_reg was removed.  [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3383]
    WARNING: [Synth 8-6014] Unused sequential element s_arlen_r_reg was removed.  [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3384]
    INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_19_b2s_rd_cmd_fsm' (106#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3334]
    INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_19_b2s_ar_channel' (107#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4082]
    INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_19_b2s_r_channel' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3811]
    	Parameter C_ID_WIDTH bound to: 12 - type: integer 
    	Parameter C_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter P_WIDTH bound to: 13 - type: integer 
    	Parameter P_DEPTH bound to: 32 - type: integer 
    	Parameter P_AWIDTH bound to: 5 - type: integer 
    	Parameter P_D_WIDTH bound to: 34 - type: integer 
    	Parameter P_D_DEPTH bound to: 32 - type: integer 
    	Parameter P_D_AWIDTH bound to: 5 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816]
    	Parameter C_WIDTH bound to: 34 - type: integer 
    	Parameter C_AWIDTH bound to: 5 - type: integer 
    	Parameter C_DEPTH bound to: 32 - type: integer 
    	Parameter C_EMPTY bound to: 5'b11111 
    	Parameter C_EMPTY_PRE bound to: 5'b00000 
    	Parameter C_FULL bound to: 5'b11110 
    	Parameter C_FULL_PRE bound to: 5'b11010 
    INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized1' (107#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816]
    INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816]
    	Parameter C_WIDTH bound to: 13 - type: integer 
    	Parameter C_AWIDTH bound to: 5 - type: integer 
    	Parameter C_DEPTH bound to: 32 - type: integer 
    	Parameter C_EMPTY bound to: 5'b11111 
    	Parameter C_EMPTY_PRE bound to: 5'b00000 
    	Parameter C_FULL bound to: 5'b11110 
    	Parameter C_FULL_PRE bound to: 5'b11010 
    INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_19_b2s_simple_fifo__parameterized2' (107#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816]
    INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_19_b2s_r_channel' (108#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3811]
    INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_19_axi_register_slice' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:2716]
    	Parameter C_FAMILY bound to: virtex6 - type: string 
    	Parameter C_AXI_PROTOCOL bound to: 1 - type: integer 
    	Parameter C_AXI_ID_WIDTH bound to: 12 - type: integer 
    	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer 
    	Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_REG_CONFIG_AW bound to: 1 - type: integer 
    	Parameter C_REG_CONFIG_W bound to: 0 - type: integer 
    	Parameter C_REG_CONFIG_B bound to: 1 - type: integer 
    	Parameter C_REG_CONFIG_AR bound to: 1 - type: integer 
    	Parameter C_REG_CONFIG_R bound to: 1 - type: integer 
    	Parameter C_NUM_SLR_CROSSINGS bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MASTER_AW bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MASTER_W bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MASTER_B bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MASTER_AR bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MASTER_R bound to: 0 - type: integer 
    	Parameter C_PIPELINES_SLAVE_AW bound to: 0 - type: integer 
    	Parameter C_PIPELINES_SLAVE_W bound to: 0 - type: integer 
    	Parameter C_PIPELINES_SLAVE_B bound to: 0 - type: integer 
    	Parameter C_PIPELINES_SLAVE_AR bound to: 0 - type: integer 
    	Parameter C_PIPELINES_SLAVE_R bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MIDDLE_AW bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MIDDLE_W bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MIDDLE_B bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MIDDLE_AR bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MIDDLE_R bound to: 0 - type: integer 
    	Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer 
    	Parameter P_FORWARD bound to: 0 - type: integer 
    	Parameter P_RESPONSE bound to: 1 - type: integer 
    	Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer 
    	Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer 
    	Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer 
    	Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer 
    	Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer 
    	Parameter G_AXI_AWLEN_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_AWLOCK_INDEX bound to: 48 - type: integer 
    	Parameter G_AXI_AWLOCK_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_AWID_INDEX bound to: 50 - type: integer 
    	Parameter G_AXI_AWID_WIDTH bound to: 12 - type: integer 
    	Parameter G_AXI_AWQOS_INDEX bound to: 62 - type: integer 
    	Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_AWREGION_INDEX bound to: 66 - type: integer 
    	Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWUSER_INDEX bound to: 66 - type: integer 
    	Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 66 - type: integer 
    	Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer 
    	Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer 
    	Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer 
    	Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer 
    	Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer 
    	Parameter G_AXI_ARLEN_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_ARLOCK_INDEX bound to: 48 - type: integer 
    	Parameter G_AXI_ARLOCK_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_ARID_INDEX bound to: 50 - type: integer 
    	Parameter G_AXI_ARID_WIDTH bound to: 12 - type: integer 
    	Parameter G_AXI_ARQOS_INDEX bound to: 62 - type: integer 
    	Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_ARREGION_INDEX bound to: 66 - type: integer 
    	Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARUSER_INDEX bound to: 66 - type: integer 
    	Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 66 - type: integer 
    	Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer 
    	Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer 
    	Parameter G_AXI_WID_INDEX bound to: 37 - type: integer 
    	Parameter G_AXI_WID_WIDTH bound to: 12 - type: integer 
    	Parameter G_AXI_WUSER_INDEX bound to: 49 - type: integer 
    	Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_WPAYLOAD_WIDTH bound to: 49 - type: integer 
    	Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_BID_INDEX bound to: 2 - type: integer 
    	Parameter G_AXI_BID_WIDTH bound to: 12 - type: integer 
    	Parameter G_AXI_BUSER_INDEX bound to: 14 - type: integer 
    	Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_BPAYLOAD_WIDTH bound to: 14 - type: integer 
    	Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer 
    	Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer 
    	Parameter G_AXI_RID_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_RID_WIDTH bound to: 12 - type: integer 
    	Parameter G_AXI_RUSER_INDEX bound to: 47 - type: integer 
    	Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_RPAYLOAD_WIDTH bound to: 47 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_19_axic_register_slice' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:488]
    	Parameter C_FAMILY bound to: virtex6 - type: string 
    	Parameter C_DATA_WIDTH bound to: 66 - type: integer 
    	Parameter C_REG_CONFIG bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_19_axic_register_slice' (109#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:488]
    INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_19_axic_register_slice__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:488]
    	Parameter C_FAMILY bound to: virtex6 - type: string 
    	Parameter C_DATA_WIDTH bound to: 49 - type: integer 
    	Parameter C_REG_CONFIG bound to: 0 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_19_axic_register_slice__parameterized0' (109#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:488]
    INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_19_axic_register_slice__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:488]
    	Parameter C_FAMILY bound to: virtex6 - type: string 
    	Parameter C_DATA_WIDTH bound to: 14 - type: integer 
    	Parameter C_REG_CONFIG bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_19_axic_register_slice__parameterized1' (109#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:488]
    INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_19_axic_register_slice__parameterized2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:488]
    	Parameter C_FAMILY bound to: virtex6 - type: string 
    	Parameter C_DATA_WIDTH bound to: 47 - type: integer 
    	Parameter C_REG_CONFIG bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_19_axic_register_slice__parameterized2' (109#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:488]
    INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:60]
    	Parameter C_AXI_PROTOCOL bound to: 1 - type: integer 
    	Parameter C_AXI_ID_WIDTH bound to: 12 - type: integer 
    	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer 
    	Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer 
    	Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AWPAYLOAD_WIDTH bound to: 66 - type: integer 
    	Parameter C_WPAYLOAD_WIDTH bound to: 49 - type: integer 
    	Parameter C_BPAYLOAD_WIDTH bound to: 14 - type: integer 
    	Parameter C_ARPAYLOAD_WIDTH bound to: 66 - type: integer 
    	Parameter C_RPAYLOAD_WIDTH bound to: 47 - type: integer 
    	Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer 
    	Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer 
    	Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer 
    	Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer 
    	Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer 
    	Parameter G_AXI_AWLEN_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_AWLOCK_INDEX bound to: 48 - type: integer 
    	Parameter G_AXI_AWLOCK_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_AWID_INDEX bound to: 50 - type: integer 
    	Parameter G_AXI_AWID_WIDTH bound to: 12 - type: integer 
    	Parameter G_AXI_AWQOS_INDEX bound to: 62 - type: integer 
    	Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_AWREGION_INDEX bound to: 66 - type: integer 
    	Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWUSER_INDEX bound to: 66 - type: integer 
    	Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 66 - type: integer 
    	Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer 
    	Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer 
    	Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer 
    	Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer 
    	Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer 
    	Parameter G_AXI_ARLEN_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_ARLOCK_INDEX bound to: 48 - type: integer 
    	Parameter G_AXI_ARLOCK_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_ARID_INDEX bound to: 50 - type: integer 
    	Parameter G_AXI_ARID_WIDTH bound to: 12 - type: integer 
    	Parameter G_AXI_ARQOS_INDEX bound to: 62 - type: integer 
    	Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_ARREGION_INDEX bound to: 66 - type: integer 
    	Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARUSER_INDEX bound to: 66 - type: integer 
    	Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 66 - type: integer 
    	Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer 
    	Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer 
    	Parameter G_AXI_WID_INDEX bound to: 37 - type: integer 
    	Parameter G_AXI_WID_WIDTH bound to: 12 - type: integer 
    	Parameter G_AXI_WUSER_INDEX bound to: 49 - type: integer 
    	Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_WPAYLOAD_WIDTH bound to: 49 - type: integer 
    	Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_BID_INDEX bound to: 2 - type: integer 
    	Parameter G_AXI_BID_WIDTH bound to: 12 - type: integer 
    	Parameter G_AXI_BUSER_INDEX bound to: 14 - type: integer 
    	Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_BPAYLOAD_WIDTH bound to: 14 - type: integer 
    	Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer 
    	Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer 
    	Parameter G_AXI_RID_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_RID_WIDTH bound to: 12 - type: integer 
    	Parameter G_AXI_RUSER_INDEX bound to: 47 - type: integer 
    	Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_RPAYLOAD_WIDTH bound to: 47 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' (110#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:60]
    INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:474]
    	Parameter C_AXI_PROTOCOL bound to: 1 - type: integer 
    	Parameter C_AXI_ID_WIDTH bound to: 12 - type: integer 
    	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer 
    	Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer 
    	Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AWPAYLOAD_WIDTH bound to: 66 - type: integer 
    	Parameter C_WPAYLOAD_WIDTH bound to: 49 - type: integer 
    	Parameter C_BPAYLOAD_WIDTH bound to: 14 - type: integer 
    	Parameter C_ARPAYLOAD_WIDTH bound to: 66 - type: integer 
    	Parameter C_RPAYLOAD_WIDTH bound to: 47 - type: integer 
    	Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer 
    	Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer 
    	Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer 
    	Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer 
    	Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer 
    	Parameter G_AXI_AWLEN_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_AWLOCK_INDEX bound to: 48 - type: integer 
    	Parameter G_AXI_AWLOCK_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_AWID_INDEX bound to: 50 - type: integer 
    	Parameter G_AXI_AWID_WIDTH bound to: 12 - type: integer 
    	Parameter G_AXI_AWQOS_INDEX bound to: 62 - type: integer 
    	Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_AWREGION_INDEX bound to: 66 - type: integer 
    	Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWUSER_INDEX bound to: 66 - type: integer 
    	Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 66 - type: integer 
    	Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer 
    	Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer 
    	Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer 
    	Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer 
    	Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer 
    	Parameter G_AXI_ARLEN_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_ARLOCK_INDEX bound to: 48 - type: integer 
    	Parameter G_AXI_ARLOCK_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_ARID_INDEX bound to: 50 - type: integer 
    	Parameter G_AXI_ARID_WIDTH bound to: 12 - type: integer 
    	Parameter G_AXI_ARQOS_INDEX bound to: 62 - type: integer 
    	Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_ARREGION_INDEX bound to: 66 - type: integer 
    	Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARUSER_INDEX bound to: 66 - type: integer 
    	Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 66 - type: integer 
    	Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer 
    	Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer 
    	Parameter G_AXI_WID_INDEX bound to: 37 - type: integer 
    	Parameter G_AXI_WID_WIDTH bound to: 12 - type: integer 
    	Parameter G_AXI_WUSER_INDEX bound to: 49 - type: integer 
    	Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_WPAYLOAD_WIDTH bound to: 49 - type: integer 
    	Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_BID_INDEX bound to: 2 - type: integer 
    	Parameter G_AXI_BID_WIDTH bound to: 12 - type: integer 
    	Parameter G_AXI_BUSER_INDEX bound to: 14 - type: integer 
    	Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_BPAYLOAD_WIDTH bound to: 14 - type: integer 
    	Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer 
    	Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer 
    	Parameter G_AXI_RID_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_RID_WIDTH bound to: 12 - type: integer 
    	Parameter G_AXI_RUSER_INDEX bound to: 47 - type: integer 
    	Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_RPAYLOAD_WIDTH bound to: 47 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' (111#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:474]
    INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_19_axi_register_slice' (112#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:2716]
    WARNING: [Synth 8-7023] instance 'SI_REG' of module 'axi_register_slice_v2_1_19_axi_register_slice' has 93 connections declared, but only 92 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4392]
    INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_19_axi_register_slice__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:2716]
    	Parameter C_FAMILY bound to: virtex6 - type: string 
    	Parameter C_AXI_PROTOCOL bound to: 2 - type: integer 
    	Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer 
    	Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_REG_CONFIG_AW bound to: 0 - type: integer 
    	Parameter C_REG_CONFIG_W bound to: 0 - type: integer 
    	Parameter C_REG_CONFIG_B bound to: 0 - type: integer 
    	Parameter C_REG_CONFIG_AR bound to: 0 - type: integer 
    	Parameter C_REG_CONFIG_R bound to: 0 - type: integer 
    	Parameter C_NUM_SLR_CROSSINGS bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MASTER_AW bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MASTER_W bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MASTER_B bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MASTER_AR bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MASTER_R bound to: 0 - type: integer 
    	Parameter C_PIPELINES_SLAVE_AW bound to: 0 - type: integer 
    	Parameter C_PIPELINES_SLAVE_W bound to: 0 - type: integer 
    	Parameter C_PIPELINES_SLAVE_B bound to: 0 - type: integer 
    	Parameter C_PIPELINES_SLAVE_AR bound to: 0 - type: integer 
    	Parameter C_PIPELINES_SLAVE_R bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MIDDLE_AW bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MIDDLE_W bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MIDDLE_B bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MIDDLE_AR bound to: 0 - type: integer 
    	Parameter C_PIPELINES_MIDDLE_R bound to: 0 - type: integer 
    	Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer 
    	Parameter P_FORWARD bound to: 0 - type: integer 
    	Parameter P_RESPONSE bound to: 1 - type: integer 
    	Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer 
    	Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWSIZE_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWBURST_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWBURST_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWCACHE_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWCACHE_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWLEN_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWLEN_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWLOCK_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWLOCK_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWID_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWID_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWQOS_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWQOS_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWREGION_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWUSER_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 35 - type: integer 
    	Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer 
    	Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARSIZE_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARBURST_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARBURST_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARCACHE_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARCACHE_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARLEN_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARLEN_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARLOCK_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARLOCK_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARID_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARID_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARQOS_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARQOS_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARREGION_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARUSER_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 35 - type: integer 
    	Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer 
    	Parameter G_AXI_WLAST_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_WID_INDEX bound to: 36 - type: integer 
    	Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_WUSER_INDEX bound to: 36 - type: integer 
    	Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_WPAYLOAD_WIDTH bound to: 36 - type: integer 
    	Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_BID_INDEX bound to: 2 - type: integer 
    	Parameter G_AXI_BID_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_BUSER_INDEX bound to: 2 - type: integer 
    	Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_BPAYLOAD_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer 
    	Parameter G_AXI_RLAST_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_RID_INDEX bound to: 34 - type: integer 
    	Parameter G_AXI_RID_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_RUSER_INDEX bound to: 34 - type: integer 
    	Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_RPAYLOAD_WIDTH bound to: 34 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_19_axic_register_slice__parameterized3' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:488]
    	Parameter C_FAMILY bound to: virtex6 - type: string 
    	Parameter C_DATA_WIDTH bound to: 35 - type: integer 
    	Parameter C_REG_CONFIG bound to: 0 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_19_axic_register_slice__parameterized3' (112#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:488]
    INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_19_axic_register_slice__parameterized4' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:488]
    	Parameter C_FAMILY bound to: virtex6 - type: string 
    	Parameter C_DATA_WIDTH bound to: 36 - type: integer 
    	Parameter C_REG_CONFIG bound to: 0 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_19_axic_register_slice__parameterized4' (112#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:488]
    INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_19_axic_register_slice__parameterized5' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:488]
    	Parameter C_FAMILY bound to: virtex6 - type: string 
    	Parameter C_DATA_WIDTH bound to: 2 - type: integer 
    	Parameter C_REG_CONFIG bound to: 0 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_19_axic_register_slice__parameterized5' (112#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:488]
    INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_19_axic_register_slice__parameterized6' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:488]
    	Parameter C_FAMILY bound to: virtex6 - type: string 
    	Parameter C_DATA_WIDTH bound to: 34 - type: integer 
    	Parameter C_REG_CONFIG bound to: 0 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_19_axic_register_slice__parameterized6' (112#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:488]
    INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:60]
    	Parameter C_AXI_PROTOCOL bound to: 2 - type: integer 
    	Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer 
    	Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer 
    	Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AWPAYLOAD_WIDTH bound to: 35 - type: integer 
    	Parameter C_WPAYLOAD_WIDTH bound to: 36 - type: integer 
    	Parameter C_BPAYLOAD_WIDTH bound to: 2 - type: integer 
    	Parameter C_ARPAYLOAD_WIDTH bound to: 35 - type: integer 
    	Parameter C_RPAYLOAD_WIDTH bound to: 34 - type: integer 
    	Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer 
    	Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWSIZE_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWBURST_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWBURST_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWCACHE_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWCACHE_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWLEN_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWLEN_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWLOCK_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWLOCK_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWID_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWID_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWQOS_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWQOS_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWREGION_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWUSER_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 35 - type: integer 
    	Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer 
    	Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARSIZE_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARBURST_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARBURST_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARCACHE_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARCACHE_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARLEN_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARLEN_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARLOCK_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARLOCK_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARID_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARID_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARQOS_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARQOS_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARREGION_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARUSER_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 35 - type: integer 
    	Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer 
    	Parameter G_AXI_WLAST_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_WID_INDEX bound to: 36 - type: integer 
    	Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_WUSER_INDEX bound to: 36 - type: integer 
    	Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_WPAYLOAD_WIDTH bound to: 36 - type: integer 
    	Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_BID_INDEX bound to: 2 - type: integer 
    	Parameter G_AXI_BID_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_BUSER_INDEX bound to: 2 - type: integer 
    	Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_BPAYLOAD_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer 
    	Parameter G_AXI_RLAST_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_RID_INDEX bound to: 34 - type: integer 
    	Parameter G_AXI_RID_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_RUSER_INDEX bound to: 34 - type: integer 
    	Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_RPAYLOAD_WIDTH bound to: 34 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' (112#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:60]
    INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:474]
    	Parameter C_AXI_PROTOCOL bound to: 2 - type: integer 
    	Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer 
    	Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer 
    	Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AWPAYLOAD_WIDTH bound to: 35 - type: integer 
    	Parameter C_WPAYLOAD_WIDTH bound to: 36 - type: integer 
    	Parameter C_BPAYLOAD_WIDTH bound to: 2 - type: integer 
    	Parameter C_ARPAYLOAD_WIDTH bound to: 35 - type: integer 
    	Parameter C_RPAYLOAD_WIDTH bound to: 34 - type: integer 
    	Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer 
    	Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWSIZE_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWBURST_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWBURST_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWCACHE_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWCACHE_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWLEN_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWLEN_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWLOCK_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWLOCK_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWID_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWID_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWQOS_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWQOS_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWREGION_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWUSER_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 35 - type: integer 
    	Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer 
    	Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARSIZE_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARBURST_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARBURST_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARCACHE_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARCACHE_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARLEN_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARLEN_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARLOCK_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARLOCK_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARID_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARID_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARQOS_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARQOS_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARREGION_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARUSER_INDEX bound to: 35 - type: integer 
    	Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 35 - type: integer 
    	Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer 
    	Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer 
    	Parameter G_AXI_WLAST_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_WID_INDEX bound to: 36 - type: integer 
    	Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_WUSER_INDEX bound to: 36 - type: integer 
    	Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_WPAYLOAD_WIDTH bound to: 36 - type: integer 
    	Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_BID_INDEX bound to: 2 - type: integer 
    	Parameter G_AXI_BID_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_BUSER_INDEX bound to: 2 - type: integer 
    	Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_BPAYLOAD_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer 
    	Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer 
    	Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer 
    	Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer 
    	Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer 
    	Parameter G_AXI_RLAST_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_RID_INDEX bound to: 34 - type: integer 
    	Parameter G_AXI_RID_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_RUSER_INDEX bound to: 34 - type: integer 
    	Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer 
    	Parameter G_AXI_RPAYLOAD_WIDTH bound to: 34 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' (112#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:474]
    INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_19_axi_register_slice__parameterized0' (112#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:2716]
    WARNING: [Synth 8-7023] instance 'MI_REG' of module 'axi_register_slice_v2_1_19_axi_register_slice' has 93 connections declared, but only 92 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4647]
    INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_19_b2s' (113#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4226]
    INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_19_axi_protocol_converter' (114#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c83a/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4808]
    INFO: [Synth 8-6155] done synthesizing module 'system_auto_pc_0' (115#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:58]
    INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_WZLZH6' (116#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:1750]
    INFO: [Synth 8-6157] synthesizing module 'system_xbar_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_xbar_0/synth/system_xbar_0.v:60]
    INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_20_axi_crossbar' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v:4884]
    	Parameter C_FAMILY bound to: zynq - type: string 
    	Parameter C_NUM_SLAVE_SLOTS bound to: 1 - type: integer 
    	Parameter C_NUM_MASTER_SLOTS bound to: 12 - type: integer 
    	Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_PROTOCOL bound to: 2 - type: integer 
    	Parameter C_NUM_ADDR_RANGES bound to: 1 - type: integer 
    	Parameter C_M_AXI_BASE_ADDR bound to: 768'b000000000000000000000000000000000100000100100000000000000000000000000000000000000000000000000000010001001010011000000000000000000000000000000000000000000000000001110111011000000000000000000000000000000000000000000000000000000111010111000000000000000000000000000000000000000000000000000000011100001110000000000000000000000000000000000000000000000000000001000011000000000000000000000000000000000000000000000000000000000111100100000000000000000000000000000000000000000000000000000000011111000100001000000000000000000000000000000000000000000000000001111100010000000000000000000000000000000000000000000000000000000111100100000010000000000000000000000000000000000000000000000000010000010110000000000000000000000000000000000000000000000000000001000101000000000000000000000000 
    	Parameter C_M_AXI_ADDR_WIDTH bound to: 384'b000000000000000000000000000100000000000000000000000000000000110000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001100000000000000000000000000000100000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000100000000000000000000000000000000110000000000000000000000000000010000 
    	Parameter C_S_AXI_BASE_ID bound to: 0 - type: integer 
    	Parameter C_S_AXI_THREAD_ID_WIDTH bound to: 0 - type: integer 
    	Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer 
    	Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_M_AXI_WRITE_CONNECTIVITY bound to: 384'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001 
    	Parameter C_M_AXI_READ_CONNECTIVITY bound to: 384'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001 
    	Parameter C_R_REGISTER bound to: 1 - type: integer 
    	Parameter C_S_AXI_SINGLE_THREAD bound to: 1 - type: integer 
    	Parameter C_S_AXI_WRITE_ACCEPTANCE bound to: 1 - type: integer 
    	Parameter C_S_AXI_READ_ACCEPTANCE bound to: 1 - type: integer 
    	Parameter C_M_AXI_WRITE_ISSUING bound to: 384'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001 
    	Parameter C_M_AXI_READ_ISSUING bound to: 384'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001 
    	Parameter C_S_AXI_ARB_PRIORITY bound to: 0 - type: integer 
    	Parameter C_M_AXI_SECURE bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
    	Parameter C_CONNECTIVITY_MODE bound to: 0 - type: integer 
    	Parameter P_ONES bound to: 65'b11111111111111111111111111111111111111111111111111111111111111111 
    	Parameter P_S_AXI_BASE_ID bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 
    	Parameter P_S_AXI_HIGH_ID bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 
    	Parameter P_AXI4 bound to: 0 - type: integer 
    	Parameter P_AXI3 bound to: 1 - type: integer 
    	Parameter P_AXILITE bound to: 2 - type: integer 
    	Parameter P_AXILITE_SIZE bound to: 3'b010 
    	Parameter P_INCR bound to: 2'b01 
    	Parameter P_M_AXI_SUPPORTS_WRITE bound to: 12'b111111111111 
    	Parameter P_M_AXI_SUPPORTS_READ bound to: 12'b111111111111 
    	Parameter P_S_AXI_SUPPORTS_WRITE bound to: 1'b1 
    	Parameter P_S_AXI_SUPPORTS_READ bound to: 1'b1 
    	Parameter C_DEBUG bound to: 1 - type: integer 
    	Parameter P_RANGE_CHECK bound to: 1 - type: integer 
    	Parameter P_ADDR_DECODE bound to: 1 - type: integer 
    	Parameter P_M_AXI_ERR_MODE bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
    	Parameter P_LEN bound to: 8 - type: integer 
    	Parameter P_LOCK bound to: 1 - type: integer 
    	Parameter P_FAMILY bound to: zynq - type: string 
    INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_20_crossbar_sasd' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v:1240]
    	Parameter C_FAMILY bound to: zynq - type: string 
    	Parameter C_NUM_SLAVE_SLOTS bound to: 1 - type: integer 
    	Parameter C_NUM_MASTER_SLOTS bound to: 12 - type: integer 
    	Parameter C_NUM_ADDR_RANGES bound to: 1 - type: integer 
    	Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_PROTOCOL bound to: 2 - type: integer 
    	Parameter C_M_AXI_BASE_ADDR bound to: 768'b000000000000000000000000000000000100000100100000000000000000000000000000000000000000000000000000010001001010011000000000000000000000000000000000000000000000000001110111011000000000000000000000000000000000000000000000000000000111010111000000000000000000000000000000000000000000000000000000011100001110000000000000000000000000000000000000000000000000000001000011000000000000000000000000000000000000000000000000000000000111100100000000000000000000000000000000000000000000000000000000011111000100001000000000000000000000000000000000000000000000000001111100010000000000000000000000000000000000000000000000000000000111100100000010000000000000000000000000000000000000000000000000010000010110000000000000000000000000000000000000000000000000000001000101000000000000000000000000 
    	Parameter C_M_AXI_HIGH_ADDR bound to: 768'b000000000000000000000000000000000100000100100000111111111111111100000000000000000000000000000000010001001010011000001111111111110000000000000000000000000000000001110111011000001111111111111111000000000000000000000000000000000111010111000000111111111111111100000000000000000000000000000000011100001110000011111111111111110000000000000000000000000000000001000011000000000000111111111111000000000000000000000000000000000111100100000000111111111111111100000000000000000000000000000000011111000100001000001111111111110000000000000000000000000000000001111100010000000000111111111111000000000000000000000000000000000111100100000010111111111111111100000000000000000000000000000000010000010110000000001111111111110000000000000000000000000000000001000101000000001111111111111111 
    	Parameter C_S_AXI_BASE_ID bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 
    	Parameter C_S_AXI_HIGH_ID bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 
    	Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer 
    	Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_S_AXI_SUPPORTS_WRITE bound to: 1'b1 
    	Parameter C_S_AXI_SUPPORTS_READ bound to: 1'b1 
    	Parameter C_M_AXI_SUPPORTS_WRITE bound to: 12'b111111111111 
    	Parameter C_M_AXI_SUPPORTS_READ bound to: 12'b111111111111 
    	Parameter C_S_AXI_ARB_PRIORITY bound to: 0 - type: integer 
    	Parameter C_M_AXI_SECURE bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
    	Parameter C_M_AXI_ERR_MODE bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 
    	Parameter C_R_REGISTER bound to: 1 - type: integer 
    	Parameter C_RANGE_CHECK bound to: 1 - type: integer 
    	Parameter C_ADDR_DECODE bound to: 1 - type: integer 
    	Parameter C_DEBUG bound to: 1 - type: integer 
    	Parameter P_AXI4 bound to: 0 - type: integer 
    	Parameter P_AXI3 bound to: 1 - type: integer 
    	Parameter P_AXILITE bound to: 2 - type: integer 
    	Parameter P_NUM_MASTER_SLOTS_DE bound to: 13 - type: integer 
    	Parameter P_NUM_MASTER_SLOTS_LOG bound to: 4 - type: integer 
    	Parameter P_NUM_MASTER_SLOTS_DE_LOG bound to: 4 - type: integer 
    	Parameter P_NUM_SLAVE_SLOTS_LOG bound to: 1 - type: integer 
    	Parameter P_AXI_AUSER_WIDTH bound to: 1 - type: integer 
    	Parameter P_AXI_WID_WIDTH bound to: 1 - type: integer 
    	Parameter P_AMESG_WIDTH bound to: 64 - type: integer 
    	Parameter P_BMESG_WIDTH bound to: 3 - type: integer 
    	Parameter P_RMESG_WIDTH bound to: 36 - type: integer 
    	Parameter P_WMESG_WIDTH bound to: 39 - type: integer 
    	Parameter P_AXILITE_ERRMODE bound to: 1 - type: integer 
    	Parameter P_NONSECURE_BIT bound to: 1 - type: integer 
    	Parameter P_M_SECURE_MASK bound to: 12'b000000000000 
    	Parameter P_M_AXILITE_MASK bound to: 12'b000000000000 
    	Parameter P_FIXED bound to: 2'b00 
    	Parameter P_BYPASS bound to: 0 - type: integer 
    	Parameter P_LIGHTWT bound to: 7 - type: integer 
    	Parameter P_FULLY_REG bound to: 1 - type: integer 
    	Parameter P_R_REG_CONFIG bound to: 1 - type: integer 
    	Parameter P_DECERR bound to: 2'b11 
    INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_20_addr_decoder' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v:794]
    	Parameter C_FAMILY bound to: zynq - type: string 
    	Parameter C_NUM_TARGETS bound to: 12 - type: integer 
    	Parameter C_NUM_TARGETS_LOG bound to: 4 - type: integer 
    	Parameter C_NUM_RANGES bound to: 1 - type: integer 
    	Parameter C_ADDR_WIDTH bound to: 32 - type: integer 
    	Parameter C_TARGET_ENC bound to: 1 - type: integer 
    	Parameter C_TARGET_HOT bound to: 1 - type: integer 
    	Parameter C_REGION_ENC bound to: 1 - type: integer 
    	Parameter C_BASE_ADDR bound to: 768'b000000000000000000000000000000000100000100100000000000000000000000000000000000000000000000000000010001001010011000000000000000000000000000000000000000000000000001110111011000000000000000000000000000000000000000000000000000000111010111000000000000000000000000000000000000000000000000000000011100001110000000000000000000000000000000000000000000000000000001000011000000000000000000000000000000000000000000000000000000000111100100000000000000000000000000000000000000000000000000000000011111000100001000000000000000000000000000000000000000000000000001111100010000000000000000000000000000000000000000000000000000000111100100000010000000000000000000000000000000000000000000000000010000010110000000000000000000000000000000000000000000000000000001000101000000000000000000000000 
    	Parameter C_HIGH_ADDR bound to: 768'b000000000000000000000000000000000100000100100000111111111111111100000000000000000000000000000000010001001010011000001111111111110000000000000000000000000000000001110111011000001111111111111111000000000000000000000000000000000111010111000000111111111111111100000000000000000000000000000000011100001110000011111111111111110000000000000000000000000000000001000011000000000000111111111111000000000000000000000000000000000111100100000000111111111111111100000000000000000000000000000000011111000100001000001111111111110000000000000000000000000000000001111100010000000000111111111111000000000000000000000000000000000111100100000010111111111111111100000000000000000000000000000000010000010110000000001111111111110000000000000000000000000000000001000101000000001111111111111111 
    	Parameter C_TARGET_QUAL bound to: 13'b0111111111111 
    	Parameter C_RESOLUTION bound to: 2 - type: integer 
    	Parameter C_COMPARATOR_THRESHOLD bound to: 6 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    	Parameter C_FAMILY bound to: rtl - type: string 
    	Parameter C_VALUE bound to: 30'b010001010000000000000000000000 
    	Parameter C_DATA_WIDTH bound to: 30 - type: integer 
    	Parameter C_BITS_PER_LUT bound to: 6 - type: integer 
    	Parameter C_NUM_LUT bound to: 5 - type: integer 
    	Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_carry_and' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:62]
    	Parameter C_FAMILY bound to: rtl - type: string 
    INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_carry_and' (117#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:62]
    INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static' (118#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    	Parameter C_FAMILY bound to: rtl - type: string 
    	Parameter C_VALUE bound to: 30'b010000010110000000000000000000 
    	Parameter C_DATA_WIDTH bound to: 30 - type: integer 
    	Parameter C_BITS_PER_LUT bound to: 6 - type: integer 
    	Parameter C_NUM_LUT bound to: 5 - type: integer 
    	Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized0' (118#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    	Parameter C_FAMILY bound to: rtl - type: string 
    	Parameter C_VALUE bound to: 30'b011110010000001000000000000000 
    	Parameter C_DATA_WIDTH bound to: 30 - type: integer 
    	Parameter C_BITS_PER_LUT bound to: 6 - type: integer 
    	Parameter C_NUM_LUT bound to: 5 - type: integer 
    	Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized1' (118#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    	Parameter C_FAMILY bound to: rtl - type: string 
    	Parameter C_VALUE bound to: 30'b011111000100000000000000000000 
    	Parameter C_DATA_WIDTH bound to: 30 - type: integer 
    	Parameter C_BITS_PER_LUT bound to: 6 - type: integer 
    	Parameter C_NUM_LUT bound to: 5 - type: integer 
    	Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized2' (118#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized3' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    	Parameter C_FAMILY bound to: rtl - type: string 
    	Parameter C_VALUE bound to: 30'b011111000100001000000000000000 
    	Parameter C_DATA_WIDTH bound to: 30 - type: integer 
    	Parameter C_BITS_PER_LUT bound to: 6 - type: integer 
    	Parameter C_NUM_LUT bound to: 5 - type: integer 
    	Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized3' (118#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized4' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    	Parameter C_FAMILY bound to: rtl - type: string 
    	Parameter C_VALUE bound to: 30'b011110010000000000000000000000 
    	Parameter C_DATA_WIDTH bound to: 30 - type: integer 
    	Parameter C_BITS_PER_LUT bound to: 6 - type: integer 
    	Parameter C_NUM_LUT bound to: 5 - type: integer 
    	Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized4' (118#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized5' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    	Parameter C_FAMILY bound to: rtl - type: string 
    	Parameter C_VALUE bound to: 30'b010000110000000000000000000000 
    	Parameter C_DATA_WIDTH bound to: 30 - type: integer 
    	Parameter C_BITS_PER_LUT bound to: 6 - type: integer 
    	Parameter C_NUM_LUT bound to: 5 - type: integer 
    	Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized5' (118#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized6' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    	Parameter C_FAMILY bound to: rtl - type: string 
    	Parameter C_VALUE bound to: 30'b011100001110000000000000000000 
    	Parameter C_DATA_WIDTH bound to: 30 - type: integer 
    	Parameter C_BITS_PER_LUT bound to: 6 - type: integer 
    	Parameter C_NUM_LUT bound to: 5 - type: integer 
    	Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized6' (118#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized7' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    	Parameter C_FAMILY bound to: rtl - type: string 
    	Parameter C_VALUE bound to: 30'b011101011100000000000000000000 
    	Parameter C_DATA_WIDTH bound to: 30 - type: integer 
    	Parameter C_BITS_PER_LUT bound to: 6 - type: integer 
    	Parameter C_NUM_LUT bound to: 5 - type: integer 
    	Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized7' (118#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized8' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    	Parameter C_FAMILY bound to: rtl - type: string 
    	Parameter C_VALUE bound to: 30'b011101110110000000000000000000 
    	Parameter C_DATA_WIDTH bound to: 30 - type: integer 
    	Parameter C_BITS_PER_LUT bound to: 6 - type: integer 
    	Parameter C_NUM_LUT bound to: 5 - type: integer 
    	Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized8' (118#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized9' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    	Parameter C_FAMILY bound to: rtl - type: string 
    	Parameter C_VALUE bound to: 30'b010001001010011000000000000000 
    	Parameter C_DATA_WIDTH bound to: 30 - type: integer 
    	Parameter C_BITS_PER_LUT bound to: 6 - type: integer 
    	Parameter C_NUM_LUT bound to: 5 - type: integer 
    	Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized9' (118#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized10' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    	Parameter C_FAMILY bound to: rtl - type: string 
    	Parameter C_VALUE bound to: 30'b010000010010000000000000000000 
    	Parameter C_DATA_WIDTH bound to: 30 - type: integer 
    	Parameter C_BITS_PER_LUT bound to: 6 - type: integer 
    	Parameter C_NUM_LUT bound to: 5 - type: integer 
    	Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized10' (118#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
    INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_20_addr_decoder' (119#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v:794]
    INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_20_decerr_slave' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v:3501]
    	Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer 
    	Parameter C_AXI_PROTOCOL bound to: 2 - type: integer 
    	Parameter C_RESP bound to: 3 - type: integer 
    	Parameter P_WRITE_IDLE bound to: 2'b00 
    	Parameter P_WRITE_DATA bound to: 2'b01 
    	Parameter P_WRITE_RESP bound to: 2'b10 
    	Parameter P_READ_IDLE bound to: 1'b0 
    	Parameter P_READ_DATA bound to: 1'b1 
    	Parameter P_AXI4 bound to: 0 - type: integer 
    	Parameter P_AXI3 bound to: 1 - type: integer 
    	Parameter P_AXILITE bound to: 2 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_20_decerr_slave' (120#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v:3501]
    INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_20_addr_arbiter_sasd' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v:65]
    	Parameter C_FAMILY bound to: zynq - type: string 
    	Parameter C_NUM_S bound to: 1 - type: integer 
    	Parameter C_NUM_S_LOG bound to: 1 - type: integer 
    	Parameter C_AMESG_WIDTH bound to: 64 - type: integer 
    	Parameter C_GRANT_ENC bound to: 1 - type: integer 
    	Parameter C_ARB_PRIORITY bound to: 0 - type: integer 
    	Parameter P_PRIO_MASK bound to: 1'b0 
    INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_20_addr_arbiter_sasd' (121#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v:65]
    INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_20_splitter' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v:4461]
    	Parameter C_NUM_M bound to: 3 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_20_splitter' (122#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v:4461]
    INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_20_splitter__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v:4461]
    	Parameter C_NUM_M bound to: 2 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_20_splitter__parameterized0' (122#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v:4461]
    INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_mux_enc' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452]
    	Parameter C_FAMILY bound to: rtl - type: string 
    	Parameter C_RATIO bound to: 13 - type: integer 
    	Parameter C_SEL_WIDTH bound to: 4 - type: integer 
    	Parameter C_DATA_WIDTH bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_mux_enc' (123#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452]
    INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452]
    	Parameter C_FAMILY bound to: rtl - type: string 
    	Parameter C_RATIO bound to: 1 - type: integer 
    	Parameter C_SEL_WIDTH bound to: 1 - type: integer 
    	Parameter C_DATA_WIDTH bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized0' (123#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452]
    INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452]
    	Parameter C_FAMILY bound to: rtl - type: string 
    	Parameter C_RATIO bound to: 13 - type: integer 
    	Parameter C_SEL_WIDTH bound to: 4 - type: integer 
    	Parameter C_DATA_WIDTH bound to: 36 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized1' (123#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452]
    INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_19_axic_register_slice__parameterized7' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:488]
    	Parameter C_FAMILY bound to: zynq - type: string 
    	Parameter C_DATA_WIDTH bound to: 36 - type: integer 
    	Parameter C_REG_CONFIG bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_19_axic_register_slice__parameterized7' (123#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v:488]
    INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452]
    	Parameter C_FAMILY bound to: rtl - type: string 
    	Parameter C_RATIO bound to: 13 - type: integer 
    	Parameter C_SEL_WIDTH bound to: 4 - type: integer 
    	Parameter C_DATA_WIDTH bound to: 3 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized2' (123#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452]
    WARNING: [Synth 8-6014] Unused sequential element gen_debug_trans_seq.debug_aw_trans_seq_i_reg was removed.  [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v:2056]
    WARNING: [Synth 8-6014] Unused sequential element gen_debug_trans_seq.debug_ar_trans_seq_i_reg was removed.  [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v:2067]
    WARNING: [Synth 8-6014] Unused sequential element gen_debug_trans_seq.debug_w_beat_cnt_i_reg was removed.  [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v:2078]
    WARNING: [Synth 8-6014] Unused sequential element gen_debug_trans_seq.debug_r_beat_cnt_i_reg was removed.  [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v:2091]
    INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_20_crossbar_sasd' (124#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v:1240]
    INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_20_axi_crossbar' (125#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v:4884]
    INFO: [Synth 8-6155] done synthesizing module 'system_xbar_0' (126#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_xbar_0/synth/system_xbar_0.v:60]
    INFO: [Synth 8-6155] done synthesizing module 'system_axi_cpu_interconnect_0' (127#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:4200]
    INFO: [Synth 8-6157] synthesizing module 'system_axi_gpreg_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_gpreg_0/synth/system_axi_gpreg_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'axi_gpreg' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ea9b/axi_gpreg.v:38]
    	Parameter ID bound to: 0 - type: integer 
    	Parameter NUM_OF_IO bound to: 2 - type: integer 
    	Parameter NUM_OF_CLK_MONS bound to: 3 - type: integer 
    	Parameter BUF_ENABLE_0 bound to: 1 - type: integer 
    	Parameter BUF_ENABLE_1 bound to: 1 - type: integer 
    	Parameter BUF_ENABLE_2 bound to: 1 - type: integer 
    	Parameter BUF_ENABLE_3 bound to: 1 - type: integer 
    	Parameter BUF_ENABLE_4 bound to: 1 - type: integer 
    	Parameter BUF_ENABLE_5 bound to: 1 - type: integer 
    	Parameter BUF_ENABLE_6 bound to: 1 - type: integer 
    	Parameter BUF_ENABLE_7 bound to: 1 - type: integer 
    	Parameter PCORE_VERSION bound to: 262243 - type: integer 
    	Parameter BUF_ENABLE bound to: 256'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001 
    INFO: [Synth 8-6157] synthesizing module 'axi_gpreg_io' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ea9b/axi_gpreg_io.v:38]
    	Parameter ID bound to: 16 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_gpreg_io' (128#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ea9b/axi_gpreg_io.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_gpreg_io__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ea9b/axi_gpreg_io.v:38]
    	Parameter ID bound to: 17 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_gpreg_io__parameterized0' (128#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ea9b/axi_gpreg_io.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_gpreg_clock_mon' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ea9b/axi_gpreg_clock_mon.v:38]
    	Parameter ID bound to: 32 - type: integer 
    	Parameter BUF_ENABLE bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_gpreg_clock_mon' (129#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ea9b/axi_gpreg_clock_mon.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_gpreg_clock_mon__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ea9b/axi_gpreg_clock_mon.v:38]
    	Parameter ID bound to: 33 - type: integer 
    	Parameter BUF_ENABLE bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_gpreg_clock_mon__parameterized0' (129#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ea9b/axi_gpreg_clock_mon.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_gpreg_clock_mon__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ea9b/axi_gpreg_clock_mon.v:38]
    	Parameter ID bound to: 34 - type: integer 
    	Parameter BUF_ENABLE bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_gpreg_clock_mon__parameterized1' (129#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ea9b/axi_gpreg_clock_mon.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_gpreg' (130#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ea9b/axi_gpreg.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'system_axi_gpreg_0' (131#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_gpreg_0/synth/system_axi_gpreg_0.v:57]
    WARNING: [Synth 8-7023] instance 'axi_gpreg' of module 'system_axi_gpreg_0' has 30 connections declared, but only 28 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:3418]
    INFO: [Synth 8-6157] synthesizing module 'system_axi_hdmi_clkgen_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hdmi_clkgen_0/synth/system_axi_hdmi_clkgen_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'axi_clkgen' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/05ff/axi_clkgen.v:39]
    	Parameter ID bound to: 0 - type: integer 
    	Parameter FPGA_TECHNOLOGY bound to: 1 - type: integer 
    	Parameter FPGA_FAMILY bound to: 4 - type: integer 
    	Parameter SPEED_GRADE bound to: 21 - type: integer 
    	Parameter DEV_PACKAGE bound to: 4 - type: integer 
    	Parameter FPGA_VOLTAGE bound to: 930 - type: integer 
    	Parameter CLKSEL_EN bound to: 0 - type: integer 
    	Parameter CLKIN_PERIOD bound to: 5.000000 - type: float 
    	Parameter CLKIN2_PERIOD bound to: 5.000000 - type: float 
    	Parameter VCO_DIV bound to: 11 - type: integer 
    	Parameter VCO_MUL bound to: 49.000000 - type: float 
    	Parameter CLK0_DIV bound to: 6.000000 - type: float 
    	Parameter CLK0_PHASE bound to: 0.000000 - type: float 
    	Parameter CLK1_DIV bound to: 6 - type: integer 
    	Parameter CLK1_PHASE bound to: 0.000000 - type: float 
    INFO: [Synth 8-6157] synthesizing module 'up_clkgen' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_clkgen.v:38]
    	Parameter ID bound to: 0 - type: integer 
    	Parameter FPGA_TECHNOLOGY bound to: 1 - type: integer 
    	Parameter FPGA_FAMILY bound to: 4 - type: integer 
    	Parameter SPEED_GRADE bound to: 21 - type: integer 
    	Parameter DEV_PACKAGE bound to: 4 - type: integer 
    	Parameter FPGA_VOLTAGE bound to: 930 - type: integer 
    	Parameter PCORE_VERSION bound to: 327779 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_clkgen' (132#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_clkgen.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_mmcm_drp' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_mmcm_drp.v:39]
    	Parameter FPGA_TECHNOLOGY bound to: 1 - type: integer 
    	Parameter MMCM_CLKIN_PERIOD bound to: 5.000000 - type: float 
    	Parameter MMCM_CLKIN2_PERIOD bound to: 5.000000 - type: float 
    	Parameter MMCM_VCO_DIV bound to: 11 - type: integer 
    	Parameter MMCM_VCO_MUL bound to: 49.000000 - type: float 
    	Parameter MMCM_CLK0_DIV bound to: 6.000000 - type: float 
    	Parameter MMCM_CLK0_PHASE bound to: 0.000000 - type: float 
    	Parameter MMCM_CLK1_DIV bound to: 6 - type: integer 
    	Parameter MMCM_CLK1_PHASE bound to: 0.000000 - type: float 
    	Parameter MMCM_CLK2_DIV bound to: 2.000000 - type: float 
    	Parameter MMCM_CLK2_PHASE bound to: 0.000000 - type: float 
    	Parameter SEVEN_SERIES bound to: 1 - type: integer 
    	Parameter ULTRASCALE bound to: 2 - type: integer 
    	Parameter ULTRASCALE_PLUS bound to: 3 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:39813]
    	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
    	Parameter CLKFBOUT_MULT_F bound to: 49.000000 - type: float 
    	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string 
    	Parameter CLKIN1_PERIOD bound to: 5.000000 - type: float 
    	Parameter CLKIN2_PERIOD bound to: 5.000000 - type: float 
    	Parameter CLKOUT0_DIVIDE_F bound to: 6.000000 - type: float 
    	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string 
    	Parameter CLKOUT1_DIVIDE bound to: 6 - type: integer 
    	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string 
    	Parameter CLKOUT2_DIVIDE bound to: 2 - type: integer 
    	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string 
    	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 
    	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string 
    	Parameter CLKOUT4_CASCADE bound to: FALSE - type: string 
    	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
    	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string 
    	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
    	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string 
    	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
    	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string 
    	Parameter COMPENSATION bound to: ZHOLD - type: string 
    	Parameter DIVCLK_DIVIDE bound to: 11 - type: integer 
    	Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 
    	Parameter IS_PSEN_INVERTED bound to: 1'b0 
    	Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 
    	Parameter IS_PWRDWN_INVERTED bound to: 1'b0 
    	Parameter IS_RST_INVERTED bound to: 1'b0 
    	Parameter REF_JITTER1 bound to: 0.010000 - type: float 
    	Parameter REF_JITTER2 bound to: 0.010000 - type: float 
    	Parameter SS_EN bound to: FALSE - type: string 
    	Parameter SS_MODE bound to: CENTER_HIGH - type: string 
    	Parameter SS_MOD_PERIOD bound to: 10000 - type: integer 
    	Parameter STARTUP_WAIT bound to: FALSE - type: string 
    INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (133#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:39813]
    INFO: [Synth 8-6155] done synthesizing module 'ad_mmcm_drp' (134#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/xilinx/common/ad_mmcm_drp.v:39]
    INFO: [Synth 8-6155] done synthesizing module 'axi_clkgen' (135#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/05ff/axi_clkgen.v:39]
    INFO: [Synth 8-6155] done synthesizing module 'system_axi_hdmi_clkgen_0' (136#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hdmi_clkgen_0/synth/system_axi_hdmi_clkgen_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'system_axi_hdmi_core_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hdmi_core_0/synth/system_axi_hdmi_core_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'axi_hdmi_tx' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/0c48/axi_hdmi_tx.v:38]
    	Parameter ID bound to: 0 - type: integer 
    	Parameter CR_CB_N bound to: 0 - type: integer 
    	Parameter FPGA_TECHNOLOGY bound to: 1 - type: integer 
    	Parameter INTERFACE bound to: 16_BIT - type: string 
    	Parameter OUT_CLK_POLARITY bound to: 1 - type: integer 
    	Parameter EMBEDDED_SYNC bound to: 0 - type: integer 
    	Parameter XILINX_7SERIES bound to: 1 - type: integer 
    	Parameter XILINX_ULTRASCALE bound to: 2 - type: integer 
    	Parameter INTEL_5SERIES bound to: 101 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'ODDR__parameterized0' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:49468]
    	Parameter DDR_CLK_EDGE bound to: OPPOSITE_EDGE - type: string 
    	Parameter INIT bound to: 1'b0 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D1_INVERTED bound to: 1'b0 
    	Parameter IS_D2_INVERTED bound to: 1'b0 
    	Parameter SRTYPE bound to: SYNC - type: string 
    INFO: [Synth 8-6155] done synthesizing module 'ODDR__parameterized0' (136#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:49468]
    INFO: [Synth 8-6157] synthesizing module 'up_hdmi_tx' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_hdmi_tx.v:38]
    	Parameter ID bound to: 0 - type: integer 
    	Parameter PCORE_VERSION bound to: 262243 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'up_xfer_cntrl__parameterized5' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_cntrl.v:38]
    	Parameter DATA_WIDTH bound to: 236 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_xfer_cntrl__parameterized5' (136#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_cntrl.v:38]
    INFO: [Synth 8-6157] synthesizing module 'up_xfer_status__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_status.v:38]
    	Parameter DATA_WIDTH bound to: 2 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_xfer_status__parameterized1' (136#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_xfer_status.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'up_hdmi_tx' (137#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_hdmi_tx.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_hdmi_tx_vdma' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/0c48/axi_hdmi_tx_vdma.v:39]
    	Parameter BUF_THRESHOLD_LO bound to: 9'b000000011 
    	Parameter BUF_THRESHOLD_HI bound to: 9'b111111101 
    	Parameter RDY_THRESHOLD_LO bound to: 9'b111000010 
    	Parameter RDY_THRESHOLD_HI bound to: 9'b111110100 
    INFO: [Synth 8-6155] done synthesizing module 'axi_hdmi_tx_vdma' (138#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/0c48/axi_hdmi_tx_vdma.v:39]
    INFO: [Synth 8-6157] synthesizing module 'axi_hdmi_tx_core' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/0c48/axi_hdmi_tx_core.v:39]
    	Parameter CR_CB_N bound to: 0 - type: integer 
    	Parameter EMBEDDED_SYNC bound to: 0 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'ad_mem__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_mem.v:38]
    	Parameter DATA_WIDTH bound to: 48 - type: integer 
    	Parameter ADDRESS_WIDTH bound to: 9 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_mem__parameterized0' (138#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_mem.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_csc_RGB2CrYCb' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_csc_RGB2CrYCb.v:44]
    	Parameter DELAY_DATA_WIDTH bound to: 5 - type: integer 
    	Parameter DW bound to: 4 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'ad_csc' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_csc.v:39]
    	Parameter DELAY_DW bound to: 5 - type: integer 
    	Parameter MUL_COEF_DW bound to: 17 - type: integer 
    	Parameter SUM_COEF_DW bound to: 24 - type: integer 
    	Parameter YCbCr_2_RGB bound to: 0 - type: integer 
    	Parameter PIXEL_WD bound to: 9 - type: integer 
    	Parameter MUL_DW bound to: 25 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_csc' (139#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_csc.v:39]
    INFO: [Synth 8-6157] synthesizing module 'ad_csc__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_csc.v:39]
    	Parameter DELAY_DW bound to: 0 - type: integer 
    	Parameter MUL_COEF_DW bound to: 17 - type: integer 
    	Parameter SUM_COEF_DW bound to: 24 - type: integer 
    	Parameter YCbCr_2_RGB bound to: 0 - type: integer 
    	Parameter PIXEL_WD bound to: 9 - type: integer 
    	Parameter MUL_DW bound to: 25 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_csc__parameterized0' (139#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_csc.v:39]
    INFO: [Synth 8-6155] done synthesizing module 'ad_csc_RGB2CrYCb' (140#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_csc_RGB2CrYCb.v:44]
    INFO: [Synth 8-6157] synthesizing module 'ad_ss_444to422' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_ss_444to422.v:39]
    	Parameter CR_CB_N bound to: 0 - type: integer 
    	Parameter DELAY_DATA_WIDTH bound to: 5 - type: integer 
    	Parameter DW bound to: 4 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_ss_444to422' (141#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_ss_444to422.v:39]
    INFO: [Synth 8-6157] synthesizing module 'axi_hdmi_tx_es' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/0c48/axi_hdmi_tx_es.v:39]
    	Parameter DATA_WIDTH bound to: 16 - type: integer 
    	Parameter BYTE_WIDTH bound to: 2 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_hdmi_tx_es' (142#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/0c48/axi_hdmi_tx_es.v:39]
    INFO: [Synth 8-4471] merging register 'hdmi_24_hsync_reg' into 'hdmi_36_hsync_reg' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/0c48/axi_hdmi_tx_core.v:467]
    INFO: [Synth 8-4471] merging register 'hdmi_24_vsync_reg' into 'hdmi_36_vsync_reg' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/0c48/axi_hdmi_tx_core.v:468]
    INFO: [Synth 8-4471] merging register 'hdmi_24_data_e_reg' into 'hdmi_36_data_e_reg' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/0c48/axi_hdmi_tx_core.v:469]
    WARNING: [Synth 8-6014] Unused sequential element hdmi_24_hsync_reg was removed.  [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/0c48/axi_hdmi_tx_core.v:467]
    WARNING: [Synth 8-6014] Unused sequential element hdmi_24_vsync_reg was removed.  [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/0c48/axi_hdmi_tx_core.v:468]
    WARNING: [Synth 8-6014] Unused sequential element hdmi_24_data_e_reg was removed.  [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/0c48/axi_hdmi_tx_core.v:469]
    INFO: [Synth 8-6155] done synthesizing module 'axi_hdmi_tx_core' (143#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/0c48/axi_hdmi_tx_core.v:39]
    INFO: [Synth 8-6155] done synthesizing module 'axi_hdmi_tx' (144#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/0c48/axi_hdmi_tx.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'system_axi_hdmi_core_0' (145#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hdmi_core_0/synth/system_axi_hdmi_core_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'system_axi_hdmi_dma_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hdmi_dma_0/synth/system_axi_hdmi_dma_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac.v:38]
    	Parameter ID bound to: 0 - type: integer 
    	Parameter DMA_DATA_WIDTH_SRC bound to: 64 - type: integer 
    	Parameter DMA_DATA_WIDTH_DEST bound to: 64 - type: integer 
    	Parameter DMA_LENGTH_WIDTH bound to: 24 - type: integer 
    	Parameter DMA_2D_TRANSFER bound to: 1'b1 
    	Parameter ASYNC_CLK_REQ_SRC bound to: 1'b0 
    	Parameter ASYNC_CLK_SRC_DEST bound to: 1'b0 
    	Parameter ASYNC_CLK_DEST_REQ bound to: 1'b0 
    	Parameter AXI_SLICE_DEST bound to: 1'b0 
    	Parameter AXI_SLICE_SRC bound to: 1'b0 
    	Parameter SYNC_TRANSFER_START bound to: 1'b0 
    	Parameter CYCLIC bound to: 1'b1 
    	Parameter DMA_AXI_PROTOCOL_DEST bound to: 1 - type: integer 
    	Parameter DMA_AXI_PROTOCOL_SRC bound to: 1 - type: integer 
    	Parameter DMA_TYPE_DEST bound to: 1 - type: integer 
    	Parameter DMA_TYPE_SRC bound to: 0 - type: integer 
    	Parameter DMA_AXI_ADDR_WIDTH bound to: 30 - type: integer 
    	Parameter MAX_BYTES_PER_BURST bound to: 128 - type: integer 
    	Parameter FIFO_SIZE bound to: 8 - type: integer 
    	Parameter AXI_ID_WIDTH_SRC bound to: 1 - type: integer 
    	Parameter AXI_ID_WIDTH_DEST bound to: 1 - type: integer 
    	Parameter DMA_AXIS_ID_W bound to: 8 - type: integer 
    	Parameter DMA_AXIS_DEST_W bound to: 4 - type: integer 
    	Parameter DISABLE_DEBUG_REGISTERS bound to: 1'b0 
    	Parameter ENABLE_DIAGNOSTICS_IF bound to: 1'b0 
    	Parameter ALLOW_ASYM_MEM bound to: 1 - type: integer 
    	Parameter DMA_TYPE_AXI_MM bound to: 0 - type: integer 
    	Parameter DMA_TYPE_AXI_STREAM bound to: 1 - type: integer 
    	Parameter DMA_TYPE_FIFO bound to: 2 - type: integer 
    	Parameter HAS_DEST_ADDR bound to: 1'b0 
    	Parameter HAS_SRC_ADDR bound to: 1'b1 
    	Parameter BYTES_PER_BEAT_WIDTH_DEST bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter DBG_ID_PADDING bound to: 4 - type: integer 
    	Parameter BEATS_PER_BURST_LIMIT_DEST bound to: 1024 - type: integer 
    	Parameter BYTES_PER_BURST_LIMIT_DEST bound to: 8192 - type: integer 
    	Parameter BEATS_PER_BURST_LIMIT_SRC bound to: 16 - type: integer 
    	Parameter BYTES_PER_BURST_LIMIT_SRC bound to: 128 - type: integer 
    	Parameter BYTES_PER_BURST_LIMIT bound to: 128 - type: integer 
    	Parameter REAL_MAX_BYTES_PER_BURST bound to: 128 - type: integer 
    	Parameter DMA_LENGTH_ALIGN_SRC bound to: 0 - type: integer 
    	Parameter DMA_LENGTH_ALIGN_DEST bound to: 3 - type: integer 
    	Parameter DMA_LENGTH_ALIGN bound to: 3 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac_regmap__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_regmap.v:38]
    	Parameter ID bound to: 0 - type: integer 
    	Parameter DISABLE_DEBUG_REGISTERS bound to: 1'b0 
    	Parameter BYTES_PER_BEAT_WIDTH_DEST bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    	Parameter DMA_TYPE_DEST bound to: 1 - type: integer 
    	Parameter DMA_TYPE_SRC bound to: 0 - type: integer 
    	Parameter DMA_AXI_ADDR_WIDTH bound to: 30 - type: integer 
    	Parameter DMA_LENGTH_WIDTH bound to: 24 - type: integer 
    	Parameter DMA_LENGTH_ALIGN bound to: 3 - type: integer 
    	Parameter DMA_CYCLIC bound to: 1'b1 
    	Parameter HAS_DEST_ADDR bound to: 1'b0 
    	Parameter HAS_SRC_ADDR bound to: 1'b1 
    	Parameter DMA_2D_TRANSFER bound to: 1'b1 
    	Parameter SYNC_TRANSFER_START bound to: 1'b0 
    	Parameter PCORE_VERSION bound to: 263009 - type: integer 
    INFO: [Synth 8-155] case statement is not full and has no default [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_regmap.v:180]
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac_regmap_request__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_regmap_request.v:38]
    	Parameter DISABLE_DEBUG_REGISTERS bound to: 1'b0 
    	Parameter BYTES_PER_BEAT_WIDTH_DEST bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    	Parameter DMA_AXI_ADDR_WIDTH bound to: 30 - type: integer 
    	Parameter DMA_LENGTH_WIDTH bound to: 24 - type: integer 
    	Parameter DMA_LENGTH_ALIGN bound to: 3 - type: integer 
    	Parameter DMA_CYCLIC bound to: 1'b1 
    	Parameter HAS_DEST_ADDR bound to: 1'b0 
    	Parameter HAS_SRC_ADDR bound to: 1'b1 
    	Parameter DMA_2D_TRANSFER bound to: 1'b1 
    	Parameter SYNC_TRANSFER_START bound to: 1'b0 
    	Parameter MEASURED_LENGTH_WIDTH bound to: 32 - type: integer 
    INFO: [Synth 8-155] case statement is not full and has no default [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_regmap_request.v:195]
    INFO: [Synth 8-155] case statement is not full and has no default [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_regmap_request.v:148]
    INFO: [Synth 8-6157] synthesizing module 'util_axis_fifo__parameterized6' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/util_axis_fifo.v:38]
    	Parameter DATA_WIDTH bound to: 34 - type: integer 
    	Parameter ASYNC_CLK bound to: 0 - type: integer 
    	Parameter ADDRESS_WIDTH bound to: 2 - type: integer 
    	Parameter S_AXIS_REGISTERED bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'util_axis_fifo__parameterized6' (145#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/util_axis_fifo.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac_regmap_request__parameterized1' (145#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_regmap_request.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac_regmap__parameterized1' (145#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_regmap.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac_transfer__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_transfer.v:38]
    	Parameter DMA_DATA_WIDTH_SRC bound to: 64 - type: integer 
    	Parameter DMA_DATA_WIDTH_DEST bound to: 64 - type: integer 
    	Parameter DMA_LENGTH_WIDTH bound to: 24 - type: integer 
    	Parameter DMA_LENGTH_ALIGN bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_DEST bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter DMA_TYPE_DEST bound to: 1 - type: integer 
    	Parameter DMA_TYPE_SRC bound to: 0 - type: integer 
    	Parameter DMA_AXI_ADDR_WIDTH bound to: 30 - type: integer 
    	Parameter DMA_2D_TRANSFER bound to: 1'b1 
    	Parameter ASYNC_CLK_REQ_SRC bound to: 1'b0 
    	Parameter ASYNC_CLK_SRC_DEST bound to: 1'b0 
    	Parameter ASYNC_CLK_DEST_REQ bound to: 1'b0 
    	Parameter AXI_SLICE_DEST bound to: 1'b0 
    	Parameter AXI_SLICE_SRC bound to: 1'b0 
    	Parameter MAX_BYTES_PER_BURST bound to: 128 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    	Parameter FIFO_SIZE bound to: 8 - type: integer 
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter AXI_LENGTH_WIDTH_SRC bound to: 4 - type: integer 
    	Parameter AXI_LENGTH_WIDTH_DEST bound to: 4 - type: integer 
    	Parameter ENABLE_DIAGNOSTICS_IF bound to: 1'b0 
    	Parameter ALLOW_ASYM_MEM bound to: 1 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'dmac_2d_transfer' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/2d_transfer.v:38]
    	Parameter DMA_AXI_ADDR_WIDTH bound to: 30 - type: integer 
    	Parameter DMA_LENGTH_WIDTH bound to: 24 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_DEST bound to: 3 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'dmac_2d_transfer' (146#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/2d_transfer.v:38]
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac_reset_manager__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_reset_manager.v:38]
    	Parameter ASYNC_CLK_REQ_SRC bound to: 1'b0 
    	Parameter ASYNC_CLK_SRC_DEST bound to: 1'b0 
    	Parameter ASYNC_CLK_DEST_REQ bound to: 1'b0 
    	Parameter STATE_DO_RESET bound to: 3'b000 
    	Parameter STATE_RESET bound to: 3'b001 
    	Parameter STATE_DISABLED bound to: 3'b010 
    	Parameter STATE_STARTUP bound to: 3'b011 
    	Parameter STATE_ENABLED bound to: 3'b100 
    	Parameter STATE_SHUTDOWN bound to: 3'b101 
    	Parameter GEN_ASYNC_RESET bound to: 3'b001 
    INFO: [Synth 8-155] case statement is not full and has no default [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_reset_manager.v:156]
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac_reset_manager__parameterized1' (146#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_reset_manager.v:38]
    INFO: [Synth 8-6157] synthesizing module 'dmac_request_arb__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/request_arb.v:38]
    	Parameter DMA_DATA_WIDTH_SRC bound to: 64 - type: integer 
    	Parameter DMA_DATA_WIDTH_DEST bound to: 64 - type: integer 
    	Parameter DMA_LENGTH_WIDTH bound to: 24 - type: integer 
    	Parameter DMA_LENGTH_ALIGN bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_DEST bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter DMA_TYPE_DEST bound to: 1 - type: integer 
    	Parameter DMA_TYPE_SRC bound to: 0 - type: integer 
    	Parameter DMA_AXI_ADDR_WIDTH bound to: 30 - type: integer 
    	Parameter ASYNC_CLK_REQ_SRC bound to: 1'b0 
    	Parameter ASYNC_CLK_SRC_DEST bound to: 1'b0 
    	Parameter ASYNC_CLK_DEST_REQ bound to: 1'b0 
    	Parameter AXI_SLICE_DEST bound to: 1'b0 
    	Parameter AXI_SLICE_SRC bound to: 1'b0 
    	Parameter MAX_BYTES_PER_BURST bound to: 128 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    	Parameter FIFO_SIZE bound to: 8 - type: integer 
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter AXI_LENGTH_WIDTH_SRC bound to: 4 - type: integer 
    	Parameter AXI_LENGTH_WIDTH_DEST bound to: 4 - type: integer 
    	Parameter ENABLE_DIAGNOSTICS_IF bound to: 1'b0 
    	Parameter ALLOW_ASYM_MEM bound to: 1 - type: integer 
    	Parameter DMA_TYPE_MM_AXI bound to: 0 - type: integer 
    	Parameter DMA_TYPE_STREAM_AXI bound to: 1 - type: integer 
    	Parameter DMA_TYPE_FIFO bound to: 2 - type: integer 
    	Parameter DMA_ADDRESS_WIDTH_DEST bound to: 27 - type: integer 
    	Parameter DMA_ADDRESS_WIDTH_SRC bound to: 27 - type: integer 
    	Parameter BEATS_PER_BURST_WIDTH_SRC bound to: 4 - type: integer 
    	Parameter BEATS_PER_BURST_WIDTH_DEST bound to: 4 - type: integer 
    	Parameter BURSTS_PER_TRANSFER_WIDTH bound to: 17 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_dmac_burst_memory__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_burst_memory.v:38]
    	Parameter DATA_WIDTH_SRC bound to: 64 - type: integer 
    	Parameter DATA_WIDTH_DEST bound to: 64 - type: integer 
    	Parameter ID_WIDTH bound to: 4 - type: integer 
    	Parameter MAX_BYTES_PER_BURST bound to: 128 - type: integer 
    	Parameter ASYNC_CLK bound to: 1'b0 
    	Parameter BYTES_PER_BEAT_WIDTH_SRC bound to: 3 - type: integer 
    	Parameter BYTES_PER_BURST_WIDTH bound to: 7 - type: integer 
    	Parameter DMA_LENGTH_ALIGN bound to: 3 - type: integer 
    	Parameter ENABLE_DIAGNOSTICS_IF bound to: 1'b0 
    	Parameter ALLOW_ASYM_MEM bound to: 1 - type: integer 
    	Parameter DATA_WIDTH_MEM bound to: 64 - type: integer 
    	Parameter MEM_RATIO bound to: 1 - type: integer 
    	Parameter BURST_LEN bound to: 16 - type: integer 
    	Parameter BURST_LEN_WIDTH bound to: 4 - type: integer 
    	Parameter AUX_FIFO_SIZE bound to: 8 - type: integer 
    	Parameter MEM_RATIO_WIDTH bound to: 0 - type: integer 
    	Parameter BURST_LEN_WIDTH_SRC bound to: 4 - type: integer 
    	Parameter BURST_LEN_WIDTH_DEST bound to: 4 - type: integer 
    	Parameter DATA_WIDTH_MEM_SRC bound to: 64 - type: integer 
    	Parameter DATA_WIDTH_MEM_DEST bound to: 64 - type: integer 
    	Parameter ADDRESS_WIDTH_SRC bound to: 7 - type: integer 
    	Parameter ADDRESS_WIDTH_DEST bound to: 7 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_MEM_SRC bound to: 3 - type: integer 
    	Parameter BYTES_PER_BEAT_WIDTH_DEST bound to: 3 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac_burst_memory__parameterized0' (146#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_burst_memory.v:38]
    INFO: [Synth 8-6157] synthesizing module 'util_axis_fifo__parameterized7' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/util_axis_fifo.v:38]
    	Parameter DATA_WIDTH bound to: 28 - type: integer 
    	Parameter ASYNC_CLK bound to: 1'b0 
    	Parameter ADDRESS_WIDTH bound to: 0 - type: integer 
    	Parameter S_AXIS_REGISTERED bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'util_axis_fifo__parameterized7' (146#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/cf62/util_axis_fifo.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'dmac_request_arb__parameterized1' (146#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/request_arb.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac_transfer__parameterized1' (146#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac_transfer.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_dmac__parameterized1' (146#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/27b8/axi_dmac.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'system_axi_hdmi_dma_0' (147#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hdmi_dma_0/synth/system_axi_hdmi_dma_0.v:57]
    WARNING: [Synth 8-7023] instance 'axi_hdmi_dma' of module 'system_axi_hdmi_dma_0' has 48 connections declared, but only 42 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:3504]
    INFO: [Synth 8-6157] synthesizing module 'system_axi_hp0_interconnect_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/synth/system_axi_hp0_interconnect_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'bd_a17c' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/synth/bd_a17c.v:10]
    INFO: [Synth 8-6157] synthesizing module 'clk_map_imp_1JU3II5' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/synth/bd_a17c.v:367]
    INFO: [Synth 8-6157] synthesizing module 'bd_a17c_one_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_0/synth/bd_a17c_one_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'xlconstant_v1_1_6_xlconstant__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66e7/hdl/xlconstant_v1_1_vl_rfs.v:23]
    	Parameter CONST_VAL bound to: 1 - type: integer 
    	Parameter CONST_WIDTH bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'xlconstant_v1_1_6_xlconstant__parameterized0' (147#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66e7/hdl/xlconstant_v1_1_vl_rfs.v:23]
    INFO: [Synth 8-6155] done synthesizing module 'bd_a17c_one_0' (148#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_0/synth/bd_a17c_one_0.v:57]
    INFO: [Synth 8-638] synthesizing module 'bd_a17c_psr_aclk_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_1/synth/bd_a17c_psr_aclk_0.vhd:74]
    	Parameter C_FAMILY bound to: zynq - type: string 
    	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
    	Parameter C_AUX_RST_WIDTH bound to: 1 - type: integer 
    	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
    	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
    	Parameter C_NUM_BUS_RST bound to: 1 - type: integer 
    	Parameter C_NUM_PERP_RST bound to: 1 - type: integer 
    	Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer 
    	Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer 
    INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1264' bound to instance 'U0' of component 'proc_sys_reset' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_1/synth/bd_a17c_psr_aclk_0.vhd:129]
    INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323]
    	Parameter C_FAMILY bound to: zynq - type: string 
    	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
    	Parameter C_AUX_RST_WIDTH bound to: 1 - type: integer 
    	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
    	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
    	Parameter C_NUM_BUS_RST bound to: 1 - type: integer 
    	Parameter C_NUM_PERP_RST bound to: 1 - type: integer 
    	Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer 
    	Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer 
    	Parameter INIT bound to: 1'b1 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1392]
    	Parameter INIT bound to: 1'b1 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1408]
    	Parameter INIT bound to: 1'b0 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1434]
    	Parameter INIT bound to: 1'b1 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1457]
    	Parameter INIT bound to: 1'b0 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1481]
    INFO: [Synth 8-638] synthesizing module 'lpf' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816]
    	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
    	Parameter C_AUX_RST_WIDTH bound to: 1 - type: integer 
    	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
    	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
    INFO: [Synth 8-3491] module 'SRL16' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77684' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:868]
    INFO: [Synth 8-6157] synthesizing module 'SRL16' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77684]
    	Parameter INIT bound to: 16'b0000000000000000 
    INFO: [Synth 8-6155] done synthesizing module 'SRL16' (149#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77684]
    INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
    	Parameter C_CDC_TYPE bound to: 1 - type: integer 
    	Parameter C_RESET_STATE bound to: 0 - type: integer 
    	Parameter C_SINGLE_BIT bound to: 1 - type: integer 
    	Parameter C_FLOP_INPUT bound to: 0 - type: integer 
    	Parameter C_VECTOR_WIDTH bound to: 2 - type: integer 
    	Parameter C_MTBF_STAGES bound to: 4 - type: integer 
    	Parameter INIT bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514]
    	Parameter INIT bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545]
    	Parameter INIT bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554]
    	Parameter INIT bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564]
    	Parameter INIT bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574]
    	Parameter INIT bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584]
    INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (150#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
    INFO: [Synth 8-256] done synthesizing module 'lpf' (151#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816]
    INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:301]
    INFO: [Synth 8-638] synthesizing module 'proc_sys_reset_v5_0_13_upcnt_n' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:125]
    	Parameter C_SIZE bound to: 6 - type: integer 
    INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset_v5_0_13_upcnt_n' (152#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:125]
    INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (153#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:301]
    INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (154#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323]
    INFO: [Synth 8-256] done synthesizing module 'bd_a17c_psr_aclk_0' (155#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_1/synth/bd_a17c_psr_aclk_0.vhd:74]
    WARNING: [Synth 8-7023] instance 'psr_aclk' of module 'bd_a17c_psr_aclk_0' has 10 connections declared, but only 6 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/synth/bd_a17c.v:402]
    WARNING: [Synth 8-3848] Net aresetn_out in module/entity clk_map_imp_1JU3II5 does not have driver. [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/synth/bd_a17c.v:383]
    INFO: [Synth 8-6155] done synthesizing module 'clk_map_imp_1JU3II5' (156#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/synth/bd_a17c.v:367]
    INFO: [Synth 8-6157] synthesizing module 'm00_exit_pipeline_imp_DR7KC6' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/synth/bd_a17c.v:411]
    INFO: [Synth 8-6157] synthesizing module 'bd_a17c_m00e_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_9/synth/bd_a17c_m00e_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'bd_a17c_m00e_0' (166#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_9/synth/bd_a17c_m00e_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'm00_exit_pipeline_imp_DR7KC6' (167#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/synth/bd_a17c.v:411]
    INFO: [Synth 8-6157] synthesizing module 'bd_a17c_m00s2a_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_8/synth/bd_a17c_m00s2a_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'bd_a17c_m00s2a_0' (169#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_8/synth/bd_a17c_m00s2a_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 'bd_a17c_s00a2s_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_5/synth/bd_a17c_s00a2s_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'bd_a17c_s00a2s_0' (171#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_5/synth/bd_a17c_s00a2s_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 's00_entry_pipeline_imp_1DL9FW5' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/synth/bd_a17c.v:587]
    INFO: [Synth 8-6157] synthesizing module 'bd_a17c_s00mmu_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_2/synth/bd_a17c_s00mmu_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'bd_a17c_s00mmu_0' (175#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_2/synth/bd_a17c_s00mmu_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 'bd_a17c_s00sic_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_4/synth/bd_a17c_s00sic_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'bd_a17c_s00sic_0' (178#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_4/synth/bd_a17c_s00sic_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 'bd_a17c_s00tr_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_3/synth/bd_a17c_s00tr_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'bd_a17c_s00tr_0' (181#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_3/synth/bd_a17c_s00tr_0.sv:58]
    WARNING: [Synth 8-7023] instance 's00_transaction_regulator' of module 'bd_a17c_s00tr_0' has 38 connections declared, but only 37 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/synth/bd_a17c.v:834]
    INFO: [Synth 8-6155] done synthesizing module 's00_entry_pipeline_imp_1DL9FW5' (182#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/synth/bd_a17c.v:587]
    INFO: [Synth 8-6157] synthesizing module 's00_nodes_imp_1AC8KA7' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/synth/bd_a17c.v:874]
    INFO: [Synth 8-6157] synthesizing module 'bd_a17c_sarn_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_6/synth/bd_a17c_sarn_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 'xpm_memory_sdpram' [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:8320]
    INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base' [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
    	Parameter MEMORY_TYPE bound to: 1 - type: integer 
    	Parameter MEMORY_SIZE bound to: 4928 - type: integer 
    	Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer 
    	Parameter CLOCKING_MODE bound to: 0 - type: integer 
    	Parameter ECC_MODE bound to: 0 - type: integer 
    	Parameter MEMORY_INIT_FILE bound to: none - type: string 
    	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
    	Parameter USE_MEM_INIT bound to: 0 - type: integer 
    	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
    	Parameter WAKEUP_TIME bound to: 0 - type: integer 
    	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
    	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
    	Parameter VERSION bound to: 0 - type: integer 
    	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
    	Parameter CASCADE_HEIGHT bound to: 0 - type: integer 
    	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
    	Parameter WRITE_DATA_WIDTH_A bound to: 154 - type: integer 
    	Parameter READ_DATA_WIDTH_A bound to: 154 - type: integer 
    	Parameter BYTE_WRITE_WIDTH_A bound to: 154 - type: integer 
    	Parameter ADDR_WIDTH_A bound to: 5 - type: integer 
    	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
    	Parameter READ_LATENCY_A bound to: 2 - type: integer 
    	Parameter WRITE_MODE_A bound to: 1 - type: integer 
    	Parameter RST_MODE_A bound to: SYNC - type: string 
    	Parameter WRITE_DATA_WIDTH_B bound to: 154 - type: integer 
    	Parameter READ_DATA_WIDTH_B bound to: 154 - type: integer 
    	Parameter BYTE_WRITE_WIDTH_B bound to: 154 - type: integer 
    	Parameter ADDR_WIDTH_B bound to: 5 - type: integer 
    	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
    	Parameter READ_LATENCY_B bound to: 1 - type: integer 
    	Parameter WRITE_MODE_B bound to: 1 - type: integer 
    	Parameter RST_MODE_B bound to: SYNC - type: string 
    	Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string 
    	Parameter P_MIN_WIDTH_DATA_A bound to: 154 - type: integer 
    	Parameter P_MIN_WIDTH_DATA_B bound to: 154 - type: integer 
    	Parameter P_MIN_WIDTH_DATA bound to: 154 - type: integer 
    	Parameter P_MIN_WIDTH_DATA_ECC bound to: 154 - type: integer 
    	Parameter P_MAX_DEPTH_DATA bound to: 32 - type: integer 
    	Parameter P_ECC_MODE bound to: no_ecc - type: string 
    	Parameter P_MEMORY_OPT bound to: yes - type: string 
    	Parameter P_WIDTH_COL_WRITE_A bound to: 154 - type: integer 
    	Parameter P_WIDTH_COL_WRITE_B bound to: 154 - type: integer 
    	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
    	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
    	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
    	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
    	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
    	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
    	Parameter P_WIDTH_ADDR_WRITE_A bound to: 5 - type: integer 
    	Parameter P_WIDTH_ADDR_WRITE_B bound to: 5 - type: integer 
    	Parameter P_WIDTH_ADDR_READ_A bound to: 5 - type: integer 
    	Parameter P_WIDTH_ADDR_READ_B bound to: 5 - type: integer 
    	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
    	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
    	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
    	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
    	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
    	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
    	Parameter P_SDP_WRITE_MODE bound to: yes - type: string 
    	Parameter rsta_loop_iter bound to: 156 - type: integer 
    	Parameter rstb_loop_iter bound to: 156 - type: integer 
    	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
    	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
    	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 154 - type: integer 
    	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
    INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base' (187#1) [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
    INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_sdpram' (188#1) [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:8320]
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'bd_a17c_sarn_0' (197#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_6/synth/bd_a17c_sarn_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 'bd_a17c_srn_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_7/synth/bd_a17c_srn_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 'xpm_memory_sdpram__parameterized0' [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:8320]
    INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized0' [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
    	Parameter MEMORY_TYPE bound to: 1 - type: integer 
    	Parameter MEMORY_SIZE bound to: 3232 - type: integer 
    	Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer 
    	Parameter CLOCKING_MODE bound to: 0 - type: integer 
    	Parameter ECC_MODE bound to: 0 - type: integer 
    	Parameter MEMORY_INIT_FILE bound to: none - type: string 
    	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
    	Parameter USE_MEM_INIT bound to: 0 - type: integer 
    	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
    	Parameter WAKEUP_TIME bound to: 0 - type: integer 
    	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
    	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
    	Parameter VERSION bound to: 0 - type: integer 
    	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
    	Parameter CASCADE_HEIGHT bound to: 0 - type: integer 
    	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
    	Parameter WRITE_DATA_WIDTH_A bound to: 101 - type: integer 
    	Parameter READ_DATA_WIDTH_A bound to: 101 - type: integer 
    	Parameter BYTE_WRITE_WIDTH_A bound to: 101 - type: integer 
    	Parameter ADDR_WIDTH_A bound to: 5 - type: integer 
    	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
    	Parameter READ_LATENCY_A bound to: 2 - type: integer 
    	Parameter WRITE_MODE_A bound to: 1 - type: integer 
    	Parameter RST_MODE_A bound to: SYNC - type: string 
    	Parameter WRITE_DATA_WIDTH_B bound to: 101 - type: integer 
    	Parameter READ_DATA_WIDTH_B bound to: 101 - type: integer 
    	Parameter BYTE_WRITE_WIDTH_B bound to: 101 - type: integer 
    	Parameter ADDR_WIDTH_B bound to: 5 - type: integer 
    	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
    	Parameter READ_LATENCY_B bound to: 1 - type: integer 
    	Parameter WRITE_MODE_B bound to: 1 - type: integer 
    	Parameter RST_MODE_B bound to: SYNC - type: string 
    	Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string 
    	Parameter P_MIN_WIDTH_DATA_A bound to: 101 - type: integer 
    	Parameter P_MIN_WIDTH_DATA_B bound to: 101 - type: integer 
    	Parameter P_MIN_WIDTH_DATA bound to: 101 - type: integer 
    	Parameter P_MIN_WIDTH_DATA_ECC bound to: 101 - type: integer 
    	Parameter P_MAX_DEPTH_DATA bound to: 32 - type: integer 
    	Parameter P_ECC_MODE bound to: no_ecc - type: string 
    	Parameter P_MEMORY_OPT bound to: yes - type: string 
    	Parameter P_WIDTH_COL_WRITE_A bound to: 101 - type: integer 
    	Parameter P_WIDTH_COL_WRITE_B bound to: 101 - type: integer 
    	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
    	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
    	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
    	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
    	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
    	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
    	Parameter P_WIDTH_ADDR_WRITE_A bound to: 5 - type: integer 
    	Parameter P_WIDTH_ADDR_WRITE_B bound to: 5 - type: integer 
    	Parameter P_WIDTH_ADDR_READ_A bound to: 5 - type: integer 
    	Parameter P_WIDTH_ADDR_READ_B bound to: 5 - type: integer 
    	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
    	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
    	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
    	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
    	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
    	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
    	Parameter P_SDP_WRITE_MODE bound to: yes - type: string 
    	Parameter rsta_loop_iter bound to: 104 - type: integer 
    	Parameter rstb_loop_iter bound to: 104 - type: integer 
    	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
    	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
    	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 101 - type: integer 
    	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
    INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized0' (197#1) [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
    INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_sdpram__parameterized0' (197#1) [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:8320]
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'bd_a17c_srn_0' (198#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_7/synth/bd_a17c_srn_0.sv:58]
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 's00_nodes_imp_1AC8KA7' (199#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/synth/bd_a17c.v:874]
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'bd_a17c' (200#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/synth/bd_a17c.v:10]
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'system_axi_hp0_interconnect_0' (201#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/synth/system_axi_hp0_interconnect_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'system_axi_hp1_interconnect_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/synth/system_axi_hp1_interconnect_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'bd_31bd' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/synth/bd_31bd.v:10]
    INFO: [Synth 8-6157] synthesizing module 'clk_map_imp_1V0WYD2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/synth/bd_31bd.v:451]
    INFO: [Synth 8-6157] synthesizing module 'bd_31bd_one_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_0/synth/bd_31bd_one_0.v:57]
    INFO: [Synth 8-6155] done synthesizing module 'bd_31bd_one_0' (202#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_0/synth/bd_31bd_one_0.v:57]
    INFO: [Synth 8-638] synthesizing module 'bd_31bd_psr_aclk_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_1/synth/bd_31bd_psr_aclk_0.vhd:74]
    	Parameter C_FAMILY bound to: zynq - type: string 
    	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
    	Parameter C_AUX_RST_WIDTH bound to: 1 - type: integer 
    	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
    	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
    	Parameter C_NUM_BUS_RST bound to: 1 - type: integer 
    	Parameter C_NUM_PERP_RST bound to: 1 - type: integer 
    	Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer 
    	Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer 
    INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1264' bound to instance 'U0' of component 'proc_sys_reset' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_1/synth/bd_31bd_psr_aclk_0.vhd:129]
    INFO: [Synth 8-256] done synthesizing module 'bd_31bd_psr_aclk_0' (203#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_1/synth/bd_31bd_psr_aclk_0.vhd:74]
    WARNING: [Synth 8-7023] instance 'psr_aclk' of module 'bd_31bd_psr_aclk_0' has 10 connections declared, but only 6 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/synth/bd_31bd.v:486]
    WARNING: [Synth 8-3848] Net aresetn_out in module/entity clk_map_imp_1V0WYD2 does not have driver. [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/synth/bd_31bd.v:467]
    INFO: [Synth 8-6155] done synthesizing module 'clk_map_imp_1V0WYD2' (204#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/synth/bd_31bd.v:451]
    INFO: [Synth 8-6157] synthesizing module 'm00_exit_pipeline_imp_2KD8VH' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/synth/bd_31bd.v:495]
    INFO: [Synth 8-6157] synthesizing module 'bd_31bd_m00e_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_10/synth/bd_31bd_m00e_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'bd_31bd_m00e_0' (205#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_10/synth/bd_31bd_m00e_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'm00_exit_pipeline_imp_2KD8VH' (206#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/synth/bd_31bd.v:495]
    INFO: [Synth 8-6157] synthesizing module 'bd_31bd_m00s2a_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_9/synth/bd_31bd_m00s2a_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'bd_31bd_m00s2a_0' (207#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_9/synth/bd_31bd_m00s2a_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 'bd_31bd_s00a2s_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_5/synth/bd_31bd_s00a2s_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'bd_31bd_s00a2s_0' (208#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_5/synth/bd_31bd_s00a2s_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 's00_entry_pipeline_imp_12BBSXA' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/synth/bd_31bd.v:706]
    INFO: [Synth 8-6157] synthesizing module 'bd_31bd_s00mmu_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_2/synth/bd_31bd_s00mmu_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'bd_31bd_s00mmu_0' (209#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_2/synth/bd_31bd_s00mmu_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 'bd_31bd_s00sic_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_4/synth/bd_31bd_s00sic_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'bd_31bd_s00sic_0' (210#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_4/synth/bd_31bd_s00sic_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 'bd_31bd_s00tr_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_3/synth/bd_31bd_s00tr_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'bd_31bd_s00tr_0' (211#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_3/synth/bd_31bd_s00tr_0.sv:58]
    WARNING: [Synth 8-7023] instance 's00_transaction_regulator' of module 'bd_31bd_s00tr_0' has 46 connections declared, but only 45 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/synth/bd_31bd.v:1004]
    INFO: [Synth 8-6155] done synthesizing module 's00_entry_pipeline_imp_12BBSXA' (212#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/synth/bd_31bd.v:706]
    INFO: [Synth 8-6157] synthesizing module 's00_nodes_imp_18B2IWK' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/synth/bd_31bd.v:1052]
    INFO: [Synth 8-6157] synthesizing module 'bd_31bd_sawn_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_6/synth/bd_31bd_sawn_0.sv:58]
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'bd_31bd_sawn_0' (213#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_6/synth/bd_31bd_sawn_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 'bd_31bd_sbn_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_8/synth/bd_31bd_sbn_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 'xpm_memory_sdpram__parameterized1' [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:8320]
    INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized1' [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
    	Parameter MEMORY_TYPE bound to: 1 - type: integer 
    	Parameter MEMORY_SIZE bound to: 736 - type: integer 
    	Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer 
    	Parameter CLOCKING_MODE bound to: 0 - type: integer 
    	Parameter ECC_MODE bound to: 0 - type: integer 
    	Parameter MEMORY_INIT_FILE bound to: none - type: string 
    	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
    	Parameter USE_MEM_INIT bound to: 0 - type: integer 
    	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
    	Parameter WAKEUP_TIME bound to: 0 - type: integer 
    	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
    	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
    	Parameter VERSION bound to: 0 - type: integer 
    	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
    	Parameter CASCADE_HEIGHT bound to: 0 - type: integer 
    	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
    	Parameter WRITE_DATA_WIDTH_A bound to: 23 - type: integer 
    	Parameter READ_DATA_WIDTH_A bound to: 23 - type: integer 
    	Parameter BYTE_WRITE_WIDTH_A bound to: 23 - type: integer 
    	Parameter ADDR_WIDTH_A bound to: 5 - type: integer 
    	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
    	Parameter READ_LATENCY_A bound to: 2 - type: integer 
    	Parameter WRITE_MODE_A bound to: 1 - type: integer 
    	Parameter RST_MODE_A bound to: SYNC - type: string 
    	Parameter WRITE_DATA_WIDTH_B bound to: 23 - type: integer 
    	Parameter READ_DATA_WIDTH_B bound to: 23 - type: integer 
    	Parameter BYTE_WRITE_WIDTH_B bound to: 23 - type: integer 
    	Parameter ADDR_WIDTH_B bound to: 5 - type: integer 
    	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
    	Parameter READ_LATENCY_B bound to: 1 - type: integer 
    	Parameter WRITE_MODE_B bound to: 1 - type: integer 
    	Parameter RST_MODE_B bound to: SYNC - type: string 
    	Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string 
    	Parameter P_MIN_WIDTH_DATA_A bound to: 23 - type: integer 
    	Parameter P_MIN_WIDTH_DATA_B bound to: 23 - type: integer 
    	Parameter P_MIN_WIDTH_DATA bound to: 23 - type: integer 
    	Parameter P_MIN_WIDTH_DATA_ECC bound to: 23 - type: integer 
    	Parameter P_MAX_DEPTH_DATA bound to: 32 - type: integer 
    	Parameter P_ECC_MODE bound to: no_ecc - type: string 
    	Parameter P_MEMORY_OPT bound to: yes - type: string 
    	Parameter P_WIDTH_COL_WRITE_A bound to: 23 - type: integer 
    	Parameter P_WIDTH_COL_WRITE_B bound to: 23 - type: integer 
    	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
    	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
    	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
    	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
    	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
    	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
    	Parameter P_WIDTH_ADDR_WRITE_A bound to: 5 - type: integer 
    	Parameter P_WIDTH_ADDR_WRITE_B bound to: 5 - type: integer 
    	Parameter P_WIDTH_ADDR_READ_A bound to: 5 - type: integer 
    	Parameter P_WIDTH_ADDR_READ_B bound to: 5 - type: integer 
    	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
    	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
    	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
    	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
    	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
    	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
    	Parameter P_SDP_WRITE_MODE bound to: yes - type: string 
    	Parameter rsta_loop_iter bound to: 24 - type: integer 
    	Parameter rstb_loop_iter bound to: 24 - type: integer 
    	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
    	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
    	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 23 - type: integer 
    	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
    INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized1' (213#1) [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
    INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_sdpram__parameterized1' (213#1) [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:8320]
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'bd_31bd_sbn_0' (214#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_8/synth/bd_31bd_sbn_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 'bd_31bd_swn_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_7/synth/bd_31bd_swn_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 'xpm_memory_sdpram__parameterized2' [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:8320]
    INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized2' [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
    	Parameter MEMORY_TYPE bound to: 1 - type: integer 
    	Parameter MEMORY_SIZE bound to: 3392 - type: integer 
    	Parameter MEMORY_PRIMITIVE bound to: 1 - type: integer 
    	Parameter CLOCKING_MODE bound to: 0 - type: integer 
    	Parameter ECC_MODE bound to: 0 - type: integer 
    	Parameter MEMORY_INIT_FILE bound to: none - type: string 
    	Parameter MEMORY_INIT_PARAM bound to: (null) - type: string 
    	Parameter USE_MEM_INIT bound to: 0 - type: integer 
    	Parameter MEMORY_OPTIMIZATION bound to: true - type: string 
    	Parameter WAKEUP_TIME bound to: 0 - type: integer 
    	Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer 
    	Parameter MESSAGE_CONTROL bound to: 0 - type: integer 
    	Parameter VERSION bound to: 0 - type: integer 
    	Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer 
    	Parameter CASCADE_HEIGHT bound to: 0 - type: integer 
    	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
    	Parameter WRITE_DATA_WIDTH_A bound to: 106 - type: integer 
    	Parameter READ_DATA_WIDTH_A bound to: 106 - type: integer 
    	Parameter BYTE_WRITE_WIDTH_A bound to: 106 - type: integer 
    	Parameter ADDR_WIDTH_A bound to: 5 - type: integer 
    	Parameter READ_RESET_VALUE_A bound to: 0 - type: string 
    	Parameter READ_LATENCY_A bound to: 2 - type: integer 
    	Parameter WRITE_MODE_A bound to: 1 - type: integer 
    	Parameter RST_MODE_A bound to: SYNC - type: string 
    	Parameter WRITE_DATA_WIDTH_B bound to: 106 - type: integer 
    	Parameter READ_DATA_WIDTH_B bound to: 106 - type: integer 
    	Parameter BYTE_WRITE_WIDTH_B bound to: 106 - type: integer 
    	Parameter ADDR_WIDTH_B bound to: 5 - type: integer 
    	Parameter READ_RESET_VALUE_B bound to: 0 - type: string 
    	Parameter READ_LATENCY_B bound to: 1 - type: integer 
    	Parameter WRITE_MODE_B bound to: 1 - type: integer 
    	Parameter RST_MODE_B bound to: SYNC - type: string 
    	Parameter P_MEMORY_PRIMITIVE bound to: distributed - type: string 
    	Parameter P_MIN_WIDTH_DATA_A bound to: 106 - type: integer 
    	Parameter P_MIN_WIDTH_DATA_B bound to: 106 - type: integer 
    	Parameter P_MIN_WIDTH_DATA bound to: 106 - type: integer 
    	Parameter P_MIN_WIDTH_DATA_ECC bound to: 106 - type: integer 
    	Parameter P_MAX_DEPTH_DATA bound to: 32 - type: integer 
    	Parameter P_ECC_MODE bound to: no_ecc - type: string 
    	Parameter P_MEMORY_OPT bound to: yes - type: string 
    	Parameter P_WIDTH_COL_WRITE_A bound to: 106 - type: integer 
    	Parameter P_WIDTH_COL_WRITE_B bound to: 106 - type: integer 
    	Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer 
    	Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer 
    	Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer 
    	Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer 
    	Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer 
    	Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer 
    	Parameter P_WIDTH_ADDR_WRITE_A bound to: 5 - type: integer 
    	Parameter P_WIDTH_ADDR_WRITE_B bound to: 5 - type: integer 
    	Parameter P_WIDTH_ADDR_READ_A bound to: 5 - type: integer 
    	Parameter P_WIDTH_ADDR_READ_B bound to: 5 - type: integer 
    	Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer 
    	Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer 
    	Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer 
    	Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer 
    	Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer 
    	Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer 
    	Parameter P_SDP_WRITE_MODE bound to: yes - type: string 
    	Parameter rsta_loop_iter bound to: 108 - type: integer 
    	Parameter rstb_loop_iter bound to: 108 - type: integer 
    	Parameter NUM_CHAR_LOC bound to: 0 - type: integer 
    	Parameter MAX_NUM_CHAR bound to: 0 - type: integer 
    	Parameter P_MIN_WIDTH_DATA_SHFT bound to: 106 - type: integer 
    	Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer 
    INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized2' (214#1) [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
    INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_sdpram__parameterized2' (214#1) [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:8320]
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'bd_31bd_swn_0' (215#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_7/synth/bd_31bd_swn_0.sv:58]
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 's00_nodes_imp_18B2IWK' (216#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/synth/bd_31bd.v:1052]
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'bd_31bd' (217#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/synth/bd_31bd.v:10]
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'system_axi_hp1_interconnect_0' (218#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/synth/system_axi_hp1_interconnect_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'system_axi_hp2_interconnect_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/synth/system_axi_hp2_interconnect_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'bd_c0fd' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/synth/bd_c0fd.v:10]
    INFO: [Synth 8-6157] synthesizing module 'clk_map_imp_QEY4IV' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/synth/bd_c0fd.v:367]
    INFO: [Synth 8-6157] synthesizing module 'bd_c0fd_one_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_0/synth/bd_c0fd_one_0.v:57]
    INFO: [Synth 8-6155] done synthesizing module 'bd_c0fd_one_0' (219#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_0/synth/bd_c0fd_one_0.v:57]
    INFO: [Synth 8-638] synthesizing module 'bd_c0fd_psr_aclk_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_1/synth/bd_c0fd_psr_aclk_0.vhd:74]
    	Parameter C_FAMILY bound to: zynq - type: string 
    	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
    	Parameter C_AUX_RST_WIDTH bound to: 1 - type: integer 
    	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
    	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
    	Parameter C_NUM_BUS_RST bound to: 1 - type: integer 
    	Parameter C_NUM_PERP_RST bound to: 1 - type: integer 
    	Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer 
    	Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer 
    INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1264' bound to instance 'U0' of component 'proc_sys_reset' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_1/synth/bd_c0fd_psr_aclk_0.vhd:129]
    INFO: [Synth 8-256] done synthesizing module 'bd_c0fd_psr_aclk_0' (220#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_1/synth/bd_c0fd_psr_aclk_0.vhd:74]
    WARNING: [Synth 8-7023] instance 'psr_aclk' of module 'bd_c0fd_psr_aclk_0' has 10 connections declared, but only 6 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/synth/bd_c0fd.v:402]
    WARNING: [Synth 8-3848] Net aresetn_out in module/entity clk_map_imp_QEY4IV does not have driver. [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/synth/bd_c0fd.v:383]
    INFO: [Synth 8-6155] done synthesizing module 'clk_map_imp_QEY4IV' (221#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/synth/bd_c0fd.v:367]
    INFO: [Synth 8-6157] synthesizing module 'm00_exit_pipeline_imp_1AI8LVG' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/synth/bd_c0fd.v:411]
    INFO: [Synth 8-6157] synthesizing module 'bd_c0fd_m00e_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_9/synth/bd_c0fd_m00e_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'bd_c0fd_m00e_0' (222#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_9/synth/bd_c0fd_m00e_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'm00_exit_pipeline_imp_1AI8LVG' (223#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/synth/bd_c0fd.v:411]
    INFO: [Synth 8-6157] synthesizing module 'bd_c0fd_m00s2a_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_8/synth/bd_c0fd_m00s2a_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'bd_c0fd_m00s2a_0' (224#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_8/synth/bd_c0fd_m00s2a_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 'bd_c0fd_s00a2s_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_5/synth/bd_c0fd_s00a2s_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'bd_c0fd_s00a2s_0' (225#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_5/synth/bd_c0fd_s00a2s_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 's00_entry_pipeline_imp_A6NOOV' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/synth/bd_c0fd.v:587]
    INFO: [Synth 8-6157] synthesizing module 'bd_c0fd_s00mmu_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_2/synth/bd_c0fd_s00mmu_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'bd_c0fd_s00mmu_0' (226#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_2/synth/bd_c0fd_s00mmu_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 'bd_c0fd_s00sic_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_4/synth/bd_c0fd_s00sic_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'bd_c0fd_s00sic_0' (227#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_4/synth/bd_c0fd_s00sic_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 'bd_c0fd_s00tr_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_3/synth/bd_c0fd_s00tr_0.sv:58]
    INFO: [Synth 8-6155] done synthesizing module 'bd_c0fd_s00tr_0' (228#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_3/synth/bd_c0fd_s00tr_0.sv:58]
    WARNING: [Synth 8-7023] instance 's00_transaction_regulator' of module 'bd_c0fd_s00tr_0' has 38 connections declared, but only 37 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/synth/bd_c0fd.v:834]
    INFO: [Synth 8-6155] done synthesizing module 's00_entry_pipeline_imp_A6NOOV' (229#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/synth/bd_c0fd.v:587]
    INFO: [Synth 8-6157] synthesizing module 's00_nodes_imp_DLXCPX' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/synth/bd_c0fd.v:874]
    INFO: [Synth 8-6157] synthesizing module 'bd_c0fd_sarn_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_6/synth/bd_c0fd_sarn_0.sv:58]
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'bd_c0fd_sarn_0' (230#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_6/synth/bd_c0fd_sarn_0.sv:58]
    INFO: [Synth 8-6157] synthesizing module 'bd_c0fd_srn_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_7/synth/bd_c0fd_srn_0.sv:58]
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'bd_c0fd_srn_0' (231#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_7/synth/bd_c0fd_srn_0.sv:58]
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 's00_nodes_imp_DLXCPX' (232#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/synth/bd_c0fd.v:874]
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'bd_c0fd' (233#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/synth/bd_c0fd.v:10]
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'system_axi_hp2_interconnect_0' (234#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/synth/system_axi_hp2_interconnect_0.v:57]
    INFO: [Synth 8-638] synthesizing module 'system_axi_i2s_adi_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_i2s_adi_0/synth/system_axi_i2s_adi_0.vhd:105]
    	Parameter SLOT_WIDTH bound to: 24 - type: integer 
    	Parameter LRCLK_POL bound to: 0 - type: integer 
    	Parameter BCLK_POL bound to: 0 - type: integer 
    	Parameter S_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter S_AXI_ADDRESS_WIDTH bound to: 16 - type: integer 
    	Parameter DEVICE_FAMILY bound to: virtex6 - type: string 
    	Parameter DMA_TYPE bound to: 1 - type: integer 
    	Parameter NUM_OF_CHANNEL bound to: 1 - type: integer 
    	Parameter HAS_TX bound to: 1 - type: integer 
    	Parameter HAS_RX bound to: 1 - type: integer 
    INFO: [Synth 8-3491] module 'axi_i2s_adi' declared at '/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c050/axi_i2s_adi.vhd:53' bound to instance 'U0' of component 'axi_i2s_adi' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_i2s_adi_0/synth/system_axi_i2s_adi_0.vhd:246]
    INFO: [Synth 8-638] synthesizing module 'axi_i2s_adi' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c050/axi_i2s_adi.vhd:146]
    	Parameter SLOT_WIDTH bound to: 24 - type: integer 
    	Parameter LRCLK_POL bound to: 0 - type: integer 
    	Parameter BCLK_POL bound to: 0 - type: integer 
    	Parameter S_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter S_AXI_ADDRESS_WIDTH bound to: 16 - type: integer 
    	Parameter DEVICE_FAMILY bound to: virtex6 - type: string 
    	Parameter DMA_TYPE bound to: 1 - type: integer 
    	Parameter NUM_OF_CHANNEL bound to: 1 - type: integer 
    	Parameter HAS_TX bound to: 1 - type: integer 
    	Parameter HAS_RX bound to: 1 - type: integer 
    INFO: [Synth 8-638] synthesizing module 'pl330_dma_fifo' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/pl330_dma_fifo.vhd:81]
    	Parameter RAM_ADDR_WIDTH bound to: 3 - type: integer 
    	Parameter FIFO_DWIDTH bound to: 24 - type: integer 
    	Parameter FIFO_DIRECTION bound to: 0 - type: integer 
    INFO: [Synth 8-638] synthesizing module 'dma_fifo' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/dma_fifo.vhd:62]
    	Parameter RAM_ADDR_WIDTH bound to: 3 - type: integer 
    	Parameter FIFO_DWIDTH bound to: 24 - type: integer 
    INFO: [Synth 8-256] done synthesizing module 'dma_fifo' (235#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/dma_fifo.vhd:62]
    INFO: [Synth 8-256] done synthesizing module 'pl330_dma_fifo' (236#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/pl330_dma_fifo.vhd:81]
    INFO: [Synth 8-638] synthesizing module 'pl330_dma_fifo__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/pl330_dma_fifo.vhd:81]
    	Parameter RAM_ADDR_WIDTH bound to: 3 - type: integer 
    	Parameter FIFO_DWIDTH bound to: 24 - type: integer 
    	Parameter FIFO_DIRECTION bound to: 1 - type: integer 
    INFO: [Synth 8-256] done synthesizing module 'pl330_dma_fifo__parameterized0' (236#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/pl330_dma_fifo.vhd:81]
    INFO: [Synth 8-638] synthesizing module 'i2s_controller' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c050/i2s_controller.vhd:80]
    	Parameter C_SLOT_WIDTH bound to: 24 - type: integer 
    	Parameter C_BCLK_POL bound to: 0 - type: integer 
    	Parameter C_LRCLK_POL bound to: 0 - type: integer 
    	Parameter C_NUM_CH bound to: 1 - type: integer 
    	Parameter C_HAS_TX bound to: 1 - type: integer 
    	Parameter C_HAS_RX bound to: 1 - type: integer 
    INFO: [Synth 8-638] synthesizing module 'fifo_synchronizer' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c050/fifo_synchronizer.vhd:59]
    	Parameter DEPTH bound to: 4 - type: integer 
    	Parameter WIDTH bound to: 5 - type: integer 
    INFO: [Synth 8-256] done synthesizing module 'fifo_synchronizer' (237#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c050/fifo_synchronizer.vhd:59]
    INFO: [Synth 8-638] synthesizing module 'i2s_clkgen' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c050/i2s_clkgen.vhd:58]
    WARNING: [Synth 8-6014] Unused sequential element prev_bclk_div_rate_reg was removed.  [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c050/i2s_clkgen.vhd:84]
    WARNING: [Synth 8-6014] Unused sequential element prev_lrclk_div_rate_reg was removed.  [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c050/i2s_clkgen.vhd:112]
    INFO: [Synth 8-256] done synthesizing module 'i2s_clkgen' (238#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c050/i2s_clkgen.vhd:58]
    INFO: [Synth 8-638] synthesizing module 'i2s_tx' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c050/i2s_tx.vhd:60]
    	Parameter C_SLOT_WIDTH bound to: 24 - type: integer 
    	Parameter C_NUM bound to: 1 - type: integer 
    INFO: [Synth 8-256] done synthesizing module 'i2s_tx' (239#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c050/i2s_tx.vhd:60]
    INFO: [Synth 8-638] synthesizing module 'i2s_rx' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c050/i2s_rx.vhd:61]
    	Parameter C_SLOT_WIDTH bound to: 24 - type: integer 
    	Parameter C_NUM bound to: 1 - type: integer 
    WARNING: [Synth 8-6014] Unused sequential element seq_reg was removed.  [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c050/i2s_rx.vhd:107]
    INFO: [Synth 8-256] done synthesizing module 'i2s_rx' (240#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c050/i2s_rx.vhd:61]
    INFO: [Synth 8-256] done synthesizing module 'i2s_controller' (241#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c050/i2s_controller.vhd:80]
    INFO: [Synth 8-638] synthesizing module 'axi_ctrlif' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/axi_ctrlif.vhd:84]
    	Parameter C_NUM_REG bound to: 12 - type: integer 
    	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter C_S_AXI_ADDR_WIDTH bound to: 16 - type: integer 
    	Parameter C_FAMILY bound to: virtex6 - type: string 
    INFO: [Synth 8-256] done synthesizing module 'axi_ctrlif' (242#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/axi_ctrlif.vhd:84]
    INFO: [Synth 8-256] done synthesizing module 'axi_i2s_adi' (243#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/c050/axi_i2s_adi.vhd:146]
    INFO: [Synth 8-256] done synthesizing module 'system_axi_i2s_adi_0' (244#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_i2s_adi_0/synth/system_axi_i2s_adi_0.vhd:105]
    INFO: [Synth 8-638] synthesizing module 'system_axi_iic_main_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_iic_main_0/synth/system_axi_iic_main_0.vhd:91]
    	Parameter C_FAMILY bound to: zynq - type: string 
    	Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer 
    	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter C_IIC_FREQ bound to: 100000 - type: integer 
    	Parameter C_TEN_BIT_ADR bound to: 0 - type: integer 
    	Parameter C_GPO_WIDTH bound to: 1 - type: integer 
    	Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 100000000 - type: integer 
    	Parameter C_SCL_INERTIAL_DELAY bound to: 0 - type: integer 
    	Parameter C_SDA_INERTIAL_DELAY bound to: 0 - type: integer 
    	Parameter C_SDA_LEVEL bound to: 1 - type: integer 
    	Parameter C_SMBUS_PMBUS_HOST bound to: 0 - type: integer 
    	Parameter C_DEFAULT_VALUE bound to: 8'b00000000 
    INFO: [Synth 8-3491] module 'axi_iic' declared at '/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:6799' bound to instance 'U0' of component 'axi_iic' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_iic_main_0/synth/system_axi_iic_main_0.vhd:180]
    INFO: [Synth 8-638] synthesizing module 'axi_iic' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:6870]
    	Parameter C_FAMILY bound to: zynq - type: string 
    	Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer 
    	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter C_IIC_FREQ bound to: 100000 - type: integer 
    	Parameter C_TEN_BIT_ADR bound to: 0 - type: integer 
    	Parameter C_GPO_WIDTH bound to: 1 - type: integer 
    	Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 100000000 - type: integer 
    	Parameter C_SCL_INERTIAL_DELAY bound to: 0 - type: integer 
    	Parameter C_SDA_INERTIAL_DELAY bound to: 0 - type: integer 
    	Parameter C_SDA_LEVEL bound to: 1 - type: integer 
    	Parameter C_SMBUS_PMBUS_HOST bound to: 0 - type: integer 
    	Parameter C_DEFAULT_VALUE bound to: 8'b00000000 
    INFO: [Synth 8-638] synthesizing module 'iic' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:6187]
    	Parameter C_NUM_IIC_REGS bound to: 18 - type: integer 
    	Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 100000000 - type: integer 
    	Parameter C_IIC_FREQ bound to: 100000 - type: integer 
    	Parameter C_TEN_BIT_ADR bound to: 0 - type: integer 
    	Parameter C_GPO_WIDTH bound to: 1 - type: integer 
    	Parameter C_SCL_INERTIAL_DELAY bound to: 0 - type: integer 
    	Parameter C_SDA_INERTIAL_DELAY bound to: 0 - type: integer 
    	Parameter C_SDA_LEVEL bound to: 1 - type: integer 
    	Parameter C_SMBUS_PMBUS_HOST bound to: 0 - type: integer 
    	Parameter C_TX_FIFO_EXIST bound to: 1 - type: bool 
    	Parameter C_RC_FIFO_EXIST bound to: 1 - type: bool 
    	Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer 
    	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter C_FAMILY bound to: zynq - type: string 
    	Parameter C_DEFAULT_VALUE bound to: 8'b00000000 
    INFO: [Synth 8-638] synthesizing module 'axi_ipif_ssp1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:5661]
    	Parameter C_NUM_IIC_REGS bound to: 18 - type: integer 
    	Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer 
    	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter C_FAMILY bound to: zynq - type: string 
    INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
    	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer 
    	Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000000111111111 
    	Parameter C_USE_WSTRB bound to: 0 - type: integer 
    	Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer 
    	Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111 
    	Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000100000000000000000000000000000000000100000000000000000000000000010010 
    	Parameter C_FAMILY bound to: zynq - type: string 
    INFO: [Synth 8-638] synthesizing module 'slave_attachment' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
    	Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111 
    	Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000100000000000000000000000000000000000100000000000000000000000000010010 
    	Parameter C_IPIF_ABUS_WIDTH bound to: 9 - type: integer 
    	Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer 
    	Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer 
    	Parameter C_USE_WSTRB bound to: 0 - type: integer 
    	Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer 
    	Parameter C_FAMILY bound to: zynq - type: string 
    INFO: [Synth 8-638] synthesizing module 'address_decoder' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
    	Parameter C_BUS_AWIDTH bound to: 9 - type: integer 
    	Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer 
    	Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111 
    	Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000100000000000000000000000000000000000100000000000000000000000000010010 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-638] synthesizing module 'pselect_f' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 3 - type: integer 
    	Parameter C_AW bound to: 9 - type: integer 
    	Parameter C_BAR bound to: 9'b000000000 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 4 - type: integer 
    	Parameter C_AW bound to: 4 - type: integer 
    	Parameter C_BAR bound to: 4'b0000 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized0' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 4 - type: integer 
    	Parameter C_AW bound to: 4 - type: integer 
    	Parameter C_BAR bound to: 4'b0001 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized1' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 4 - type: integer 
    	Parameter C_AW bound to: 4 - type: integer 
    	Parameter C_BAR bound to: 4'b0010 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized2' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized3' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 4 - type: integer 
    	Parameter C_AW bound to: 4 - type: integer 
    	Parameter C_BAR bound to: 4'b0011 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized3' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized4' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 4 - type: integer 
    	Parameter C_AW bound to: 4 - type: integer 
    	Parameter C_BAR bound to: 4'b0100 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized4' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized5' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 4 - type: integer 
    	Parameter C_AW bound to: 4 - type: integer 
    	Parameter C_BAR bound to: 4'b0101 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized5' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized6' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 4 - type: integer 
    	Parameter C_AW bound to: 4 - type: integer 
    	Parameter C_BAR bound to: 4'b0110 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized6' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized7' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 4 - type: integer 
    	Parameter C_AW bound to: 4 - type: integer 
    	Parameter C_BAR bound to: 4'b0111 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized7' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized8' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 4 - type: integer 
    	Parameter C_AW bound to: 4 - type: integer 
    	Parameter C_BAR bound to: 4'b1000 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized8' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized9' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 4 - type: integer 
    	Parameter C_AW bound to: 4 - type: integer 
    	Parameter C_BAR bound to: 4'b1001 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized9' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized10' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 4 - type: integer 
    	Parameter C_AW bound to: 4 - type: integer 
    	Parameter C_BAR bound to: 4'b1010 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized10' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized11' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 4 - type: integer 
    	Parameter C_AW bound to: 4 - type: integer 
    	Parameter C_BAR bound to: 4'b1011 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized11' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized12' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 4 - type: integer 
    	Parameter C_AW bound to: 4 - type: integer 
    	Parameter C_BAR bound to: 4'b1100 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized12' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized13' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 4 - type: integer 
    	Parameter C_AW bound to: 4 - type: integer 
    	Parameter C_BAR bound to: 4'b1101 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized13' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized14' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 4 - type: integer 
    	Parameter C_AW bound to: 4 - type: integer 
    	Parameter C_BAR bound to: 4'b1110 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized14' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized15' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 4 - type: integer 
    	Parameter C_AW bound to: 4 - type: integer 
    	Parameter C_BAR bound to: 4'b1111 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized15' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized16' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 7 - type: integer 
    	Parameter C_AW bound to: 9 - type: integer 
    	Parameter C_BAR bound to: 9'b001000000 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized16' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized17' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 1 - type: integer 
    	Parameter C_AW bound to: 9 - type: integer 
    	Parameter C_BAR bound to: 9'b100000000 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized17' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized18' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 5 - type: integer 
    	Parameter C_AW bound to: 5 - type: integer 
    	Parameter C_BAR bound to: 5'b00000 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized18' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized19' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 5 - type: integer 
    	Parameter C_AW bound to: 5 - type: integer 
    	Parameter C_BAR bound to: 5'b00001 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized19' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized20' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 5 - type: integer 
    	Parameter C_AW bound to: 5 - type: integer 
    	Parameter C_BAR bound to: 5'b00010 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized20' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized21' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 5 - type: integer 
    	Parameter C_AW bound to: 5 - type: integer 
    	Parameter C_BAR bound to: 5'b00011 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized21' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized22' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 5 - type: integer 
    	Parameter C_AW bound to: 5 - type: integer 
    	Parameter C_BAR bound to: 5'b00100 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized22' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized23' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 5 - type: integer 
    	Parameter C_AW bound to: 5 - type: integer 
    	Parameter C_BAR bound to: 5'b00101 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized23' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized24' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 5 - type: integer 
    	Parameter C_AW bound to: 5 - type: integer 
    	Parameter C_BAR bound to: 5'b00110 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized24' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized25' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 5 - type: integer 
    	Parameter C_AW bound to: 5 - type: integer 
    	Parameter C_BAR bound to: 5'b00111 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized25' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized26' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 5 - type: integer 
    	Parameter C_AW bound to: 5 - type: integer 
    	Parameter C_BAR bound to: 5'b01000 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized26' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized27' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 5 - type: integer 
    	Parameter C_AW bound to: 5 - type: integer 
    	Parameter C_BAR bound to: 5'b01001 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized27' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized28' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 5 - type: integer 
    	Parameter C_AW bound to: 5 - type: integer 
    	Parameter C_BAR bound to: 5'b01010 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized28' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized29' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 5 - type: integer 
    	Parameter C_AW bound to: 5 - type: integer 
    	Parameter C_BAR bound to: 5'b01011 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized29' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized30' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 5 - type: integer 
    	Parameter C_AW bound to: 5 - type: integer 
    	Parameter C_BAR bound to: 5'b01100 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized30' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized31' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 5 - type: integer 
    	Parameter C_AW bound to: 5 - type: integer 
    	Parameter C_BAR bound to: 5'b01101 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized31' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized32' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 5 - type: integer 
    	Parameter C_AW bound to: 5 - type: integer 
    	Parameter C_BAR bound to: 5'b01110 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized32' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized33' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 5 - type: integer 
    	Parameter C_AW bound to: 5 - type: integer 
    	Parameter C_BAR bound to: 5'b01111 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized33' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized34' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 5 - type: integer 
    	Parameter C_AW bound to: 5 - type: integer 
    	Parameter C_BAR bound to: 5'b10000 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized34' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized35' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    	Parameter C_AB bound to: 5 - type: integer 
    	Parameter C_AW bound to: 5 - type: integer 
    	Parameter C_BAR bound to: 5'b10001 
    	Parameter C_FAMILY bound to: nofamily - type: string 
    INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized35' (245#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
    INFO: [Synth 8-256] done synthesizing module 'address_decoder' (246#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
    INFO: [Synth 8-226] default block is never used [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550]
    INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (247#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
    INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (248#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
    INFO: [Synth 8-638] synthesizing module 'interrupt_control' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/a040/hdl/interrupt_control_v3_1_vh_rfs.vhd:259]
    	Parameter C_NUM_CE bound to: 16 - type: integer 
    	Parameter C_NUM_IPIF_IRPT_SRC bound to: 1 - type: integer 
    	Parameter C_IP_INTR_MODE_ARRAY bound to: 256'b0000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011 
    	Parameter C_INCLUDE_DEV_PENCODER bound to: 0 - type: bool 
    	Parameter C_INCLUDE_DEV_ISC bound to: 0 - type: bool 
    	Parameter C_IPIF_DWIDTH bound to: 32 - type: integer 
    INFO: [Synth 8-256] done synthesizing module 'interrupt_control' (249#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/a040/hdl/interrupt_control_v3_1_vh_rfs.vhd:259]
    INFO: [Synth 8-638] synthesizing module 'soft_reset' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:141]
    	Parameter C_SIPIF_DWIDTH bound to: 32 - type: integer 
    	Parameter C_RESET_WIDTH bound to: 4 - type: integer 
    	Parameter INIT bound to: 1'b0 
    	Parameter IS_CE_INVERTED bound to: 1'b0 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    	Parameter IS_S_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:272]
    	Parameter INIT bound to: 1'b0 
    	Parameter IS_CE_INVERTED bound to: 1'b0 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    	Parameter IS_S_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:272]
    	Parameter INIT bound to: 1'b0 
    	Parameter IS_CE_INVERTED bound to: 1'b0 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    	Parameter IS_S_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:272]
    	Parameter INIT bound to: 1'b0 
    	Parameter IS_CE_INVERTED bound to: 1'b0 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    	Parameter IS_S_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:272]
    	Parameter INIT bound to: 1'b0 
    	Parameter IS_CE_INVERTED bound to: 1'b0 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    	Parameter IS_S_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'FF_WRACK' to cell 'FDRSE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:295]
    INFO: [Synth 8-256] done synthesizing module 'soft_reset' (250#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:141]
    INFO: [Synth 8-256] done synthesizing module 'axi_ipif_ssp1' (251#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:5661]
    INFO: [Synth 8-638] synthesizing module 'reg_interface' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:1677]
    	Parameter C_SCL_INERTIAL_DELAY bound to: 0 - type: integer 
    	Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 100000000 - type: integer 
    	Parameter C_IIC_FREQ bound to: 100000 - type: integer 
    	Parameter C_SMBUS_PMBUS_HOST bound to: 0 - type: integer 
    	Parameter C_TX_FIFO_EXIST bound to: 1 - type: bool 
    	Parameter C_TX_FIFO_BITS bound to: 4 - type: integer 
    	Parameter C_RC_FIFO_EXIST bound to: 1 - type: bool 
    	Parameter C_RC_FIFO_BITS bound to: 4 - type: integer 
    	Parameter C_TEN_BIT_ADR bound to: 0 - type: integer 
    	Parameter C_GPO_WIDTH bound to: 1 - type: integer 
    	Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer 
    	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter C_SIZE bound to: 10 - type: integer 
    	Parameter C_NUM_IIC_REGS bound to: 18 - type: integer 
    	Parameter C_DEFAULT_VALUE bound to: 8'b00000000 
    WARNING: [Synth 8-6014] Unused sequential element ro_a_reg was removed.  [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:2273]
    INFO: [Synth 8-256] done synthesizing module 'reg_interface' (252#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:1677]
    INFO: [Synth 8-638] synthesizing module 'filter' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:4985]
    	Parameter SCL_INERTIAL_DELAY bound to: 0 - type: integer 
    	Parameter SDA_INERTIAL_DELAY bound to: 0 - type: integer 
    INFO: [Synth 8-638] synthesizing module 'debounce' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:1307]
    	Parameter C_INERTIAL_DELAY bound to: 0 - type: integer 
    	Parameter C_DEFAULT bound to: 1'b1 
    INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
    	Parameter C_CDC_TYPE bound to: 1 - type: integer 
    	Parameter C_RESET_STATE bound to: 0 - type: integer 
    	Parameter C_SINGLE_BIT bound to: 1 - type: integer 
    	Parameter C_FLOP_INPUT bound to: 0 - type: integer 
    	Parameter C_VECTOR_WIDTH bound to: 32 - type: integer 
    	Parameter C_MTBF_STAGES bound to: 4 - type: integer 
    	Parameter INIT bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514]
    	Parameter INIT bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545]
    	Parameter INIT bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554]
    	Parameter INIT bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564]
    	Parameter INIT bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574]
    	Parameter INIT bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584]
    INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized0' (252#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
    INFO: [Synth 8-256] done synthesizing module 'debounce' (253#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:1307]
    INFO: [Synth 8-256] done synthesizing module 'filter' (254#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:4985]
    INFO: [Synth 8-638] synthesizing module 'iic_control' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:2908]
    	Parameter C_SCL_INERTIAL_DELAY bound to: 0 - type: integer 
    	Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 100000000 - type: integer 
    	Parameter C_IIC_FREQ bound to: 100000 - type: integer 
    	Parameter C_SIZE bound to: 10 - type: integer 
    	Parameter C_TEN_BIT_ADR bound to: 0 - type: integer 
    	Parameter C_SDA_LEVEL bound to: 1 - type: integer 
    	Parameter C_SMBUS_PMBUS_HOST bound to: 0 - type: integer 
    INFO: [Synth 8-638] synthesizing module 'axi_iic_v2_0_22_upcnt_n' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:740]
    	Parameter C_SIZE bound to: 10 - type: integer 
    INFO: [Synth 8-256] done synthesizing module 'axi_iic_v2_0_22_upcnt_n' (255#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:740]
    INFO: [Synth 8-638] synthesizing module 'shift8' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:897]
    INFO: [Synth 8-256] done synthesizing module 'shift8' (256#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:897]
    INFO: [Synth 8-638] synthesizing module 'axi_iic_v2_0_22_upcnt_n__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:740]
    	Parameter C_SIZE bound to: 4 - type: integer 
    INFO: [Synth 8-256] done synthesizing module 'axi_iic_v2_0_22_upcnt_n__parameterized0' (256#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:740]
    WARNING: [Synth 8-6014] Unused sequential element sda_cout_reg_d1_reg was removed.  [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:3658]
    WARNING: [Synth 8-6014] Unused sequential element gen_stop_and_scl_hi_reg was removed.  [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:3874]
    INFO: [Synth 8-256] done synthesizing module 'iic_control' (257#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:2908]
    INFO: [Synth 8-638] synthesizing module 'SRL_FIFO' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:449]
    	Parameter C_DATA_BITS bound to: 8 - type: integer 
    	Parameter C_DEPTH bound to: 4 - type: integer 
    	Parameter C_XON bound to: 0 - type: bool 
    INFO: [Synth 8-3491] module 'FDR' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13651' bound to instance 'Data_Exists_DFF' of component 'FDR' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:543]
    INFO: [Synth 8-6157] synthesizing module 'FDR' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13651]
    	Parameter INIT bound to: 1'b0 
    INFO: [Synth 8-6155] done synthesizing module 'FDR' (258#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13651]
    INFO: [Synth 8-3491] module 'MUXCY_L' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:42771' bound to instance 'MUXCY_L_I' of component 'MUXCY_L' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:560]
    INFO: [Synth 8-6157] synthesizing module 'MUXCY_L' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:42771]
    INFO: [Synth 8-6155] done synthesizing module 'MUXCY_L' (259#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:42771]
    INFO: [Synth 8-3491] module 'XORCY' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:82038' bound to instance 'XORCY_I' of component 'XORCY' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:567]
    INFO: [Synth 8-6157] synthesizing module 'XORCY' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:82038]
    INFO: [Synth 8-6155] done synthesizing module 'XORCY' (260#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:82038]
    INFO: [Synth 8-3491] module 'FDRE' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664' bound to instance 'FDRE_I' of component 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:573]
    INFO: [Synth 8-6157] synthesizing module 'FDRE' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664]
    	Parameter INIT bound to: 1'b0 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    INFO: [Synth 8-6155] done synthesizing module 'FDRE' (261#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664]
    INFO: [Synth 8-3491] module 'MUXCY_L' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:42771' bound to instance 'MUXCY_L_I' of component 'MUXCY_L' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:560]
    INFO: [Synth 8-3491] module 'XORCY' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:82038' bound to instance 'XORCY_I' of component 'XORCY' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:567]
    INFO: [Synth 8-3491] module 'FDRE' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664' bound to instance 'FDRE_I' of component 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:573]
    INFO: [Synth 8-3491] module 'MUXCY_L' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:42771' bound to instance 'MUXCY_L_I' of component 'MUXCY_L' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:560]
    INFO: [Synth 8-3491] module 'XORCY' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:82038' bound to instance 'XORCY_I' of component 'XORCY' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:567]
    INFO: [Synth 8-3491] module 'FDRE' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664' bound to instance 'FDRE_I' of component 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:573]
    INFO: [Synth 8-3491] module 'MUXCY_L' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:42771' bound to instance 'MUXCY_L_I' of component 'MUXCY_L' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:560]
    INFO: [Synth 8-3491] module 'XORCY' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:82038' bound to instance 'XORCY_I' of component 'XORCY' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:567]
    INFO: [Synth 8-3491] module 'FDRE' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664' bound to instance 'FDRE_I' of component 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:573]
    INFO: [Synth 8-3491] module 'SRL16E' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700' bound to instance 'SRL16E_I' of component 'SRL16E' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:584]
    INFO: [Synth 8-6157] synthesizing module 'SRL16E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700]
    	Parameter INIT bound to: 16'b0000000000000000 
    	Parameter IS_CLK_INVERTED bound to: 1'b0 
    INFO: [Synth 8-6155] done synthesizing module 'SRL16E' (262#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700]
    INFO: [Synth 8-3491] module 'SRL16E' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700' bound to instance 'SRL16E_I' of component 'SRL16E' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:584]
    INFO: [Synth 8-3491] module 'SRL16E' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700' bound to instance 'SRL16E_I' of component 'SRL16E' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:584]
    INFO: [Synth 8-3491] module 'SRL16E' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700' bound to instance 'SRL16E_I' of component 'SRL16E' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:584]
    INFO: [Synth 8-3491] module 'SRL16E' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700' bound to instance 'SRL16E_I' of component 'SRL16E' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:584]
    INFO: [Synth 8-3491] module 'SRL16E' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700' bound to instance 'SRL16E_I' of component 'SRL16E' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:584]
    INFO: [Synth 8-3491] module 'SRL16E' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700' bound to instance 'SRL16E_I' of component 'SRL16E' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:584]
    INFO: [Synth 8-3491] module 'SRL16E' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700' bound to instance 'SRL16E_I' of component 'SRL16E' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:584]
    INFO: [Synth 8-256] done synthesizing module 'SRL_FIFO' (263#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:449]
    INFO: [Synth 8-638] synthesizing module 'dynamic_master' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:5204]
    WARNING: [Synth 8-6014] Unused sequential element dynamic_MSMS_d_reg was removed.  [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:5265]
    INFO: [Synth 8-256] done synthesizing module 'dynamic_master' (264#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:5204]
    INFO: [Synth 8-638] synthesizing module 'SRL_FIFO__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:449]
    	Parameter C_DATA_BITS bound to: 2 - type: integer 
    	Parameter C_DEPTH bound to: 4 - type: integer 
    	Parameter C_XON bound to: 0 - type: bool 
    INFO: [Synth 8-3491] module 'FDR' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13651' bound to instance 'Data_Exists_DFF' of component 'FDR' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:543]
    INFO: [Synth 8-3491] module 'MUXCY_L' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:42771' bound to instance 'MUXCY_L_I' of component 'MUXCY_L' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:560]
    INFO: [Synth 8-3491] module 'XORCY' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:82038' bound to instance 'XORCY_I' of component 'XORCY' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:567]
    INFO: [Synth 8-3491] module 'FDRE' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664' bound to instance 'FDRE_I' of component 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:573]
    INFO: [Synth 8-3491] module 'MUXCY_L' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:42771' bound to instance 'MUXCY_L_I' of component 'MUXCY_L' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:560]
    INFO: [Synth 8-3491] module 'XORCY' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:82038' bound to instance 'XORCY_I' of component 'XORCY' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:567]
    INFO: [Synth 8-3491] module 'FDRE' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664' bound to instance 'FDRE_I' of component 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:573]
    INFO: [Synth 8-3491] module 'MUXCY_L' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:42771' bound to instance 'MUXCY_L_I' of component 'MUXCY_L' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:560]
    INFO: [Synth 8-3491] module 'XORCY' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:82038' bound to instance 'XORCY_I' of component 'XORCY' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:567]
    INFO: [Synth 8-3491] module 'FDRE' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664' bound to instance 'FDRE_I' of component 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:573]
    INFO: [Synth 8-3491] module 'MUXCY_L' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:42771' bound to instance 'MUXCY_L_I' of component 'MUXCY_L' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:560]
    INFO: [Synth 8-3491] module 'XORCY' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:82038' bound to instance 'XORCY_I' of component 'XORCY' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:567]
    INFO: [Synth 8-3491] module 'FDRE' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664' bound to instance 'FDRE_I' of component 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:573]
    INFO: [Synth 8-3491] module 'SRL16E' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700' bound to instance 'SRL16E_I' of component 'SRL16E' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:584]
    INFO: [Synth 8-3491] module 'SRL16E' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700' bound to instance 'SRL16E_I' of component 'SRL16E' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:584]
    INFO: [Synth 8-256] done synthesizing module 'SRL_FIFO__parameterized0' (264#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:449]
    INFO: [Synth 8-256] done synthesizing module 'iic' (265#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:6187]
    INFO: [Synth 8-256] done synthesizing module 'axi_iic' (266#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d5df/hdl/axi_iic_v2_0_vh_rfs.vhd:6870]
    INFO: [Synth 8-256] done synthesizing module 'system_axi_iic_main_0' (267#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_iic_main_0/synth/system_axi_iic_main_0.vhd:91]
    WARNING: [Synth 8-7023] instance 'axi_iic_main' of module 'system_axi_iic_main_0' has 27 connections declared, but only 26 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:3697]
    INFO: [Synth 8-6157] synthesizing module 'system_axi_pz_xcvrlb_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_pz_xcvrlb_0/synth/system_axi_pz_xcvrlb_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'axi_xcvrlb' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/785d/axi_xcvrlb.v:38]
    	Parameter CPLL_FBDIV bound to: 1 - type: integer 
    	Parameter CPLL_FBDIV_4_5 bound to: 5 - type: integer 
    	Parameter NUM_OF_LANES bound to: 2 - type: integer 
    	Parameter XCVR_TYPE bound to: 2 - type: integer 
    	Parameter VERSION bound to: 1048929 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'axi_xcvrlb_1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/785d/axi_xcvrlb_1.v:38]
    	Parameter CPLL_FBDIV bound to: 1 - type: integer 
    	Parameter CPLL_FBDIV_4_5 bound to: 5 - type: integer 
    	Parameter XCVR_TYPE bound to: 2 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'ad_pnmon__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_pnmon.v:39]
    	Parameter DATA_WIDTH bound to: 32 - type: integer 
    	Parameter OOS_THRESHOLD bound to: 16 - type: integer 
    	Parameter ALLOW_ZERO_MASKING bound to: 0 - type: integer 
    	Parameter CNT_W bound to: 4 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_pnmon__parameterized0' (267#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_pnmon.v:39]
    WARNING: [Synth 8-7023] instance 'i_pnmon' of module 'ad_pnmon' has 7 connections declared, but only 6 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/785d/axi_xcvrlb_1.v:236]
    INFO: [Synth 8-6157] synthesizing module 'util_adxcvr_xch' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_adxcvr/util_adxcvr_xch.v:38]
    	Parameter XCVR_TYPE bound to: 2 - type: integer 
    	Parameter CPLL_FBDIV bound to: 1 - type: integer 
    	Parameter CPLL_FBDIV_4_5 bound to: 5 - type: integer 
    	Parameter CPLL_CFG0 bound to: 16'b0000000111111010 
    	Parameter CPLL_CFG1 bound to: 16'b0000000000100011 
    	Parameter CPLL_CFG2 bound to: 16'b0000000000000010 
    	Parameter CPLL_CFG3 bound to: 16'b0000000000000000 
    	Parameter CH_HSPMUX bound to: 16'b0010010000100100 
    	Parameter PREIQ_FREQ_BST bound to: 0 - type: integer 
    	Parameter RXPI_CFG0 bound to: 16'b0000000000000010 
    	Parameter RXPI_CFG1 bound to: 16'b0000000000010101 
    	Parameter RTX_BUF_CML_CTRL bound to: 3'b011 
    	Parameter TX_OUT_DIV bound to: 1 - type: integer 
    	Parameter TX_CLK25_DIV bound to: 10 - type: integer 
    	Parameter TX_POLARITY bound to: 0 - type: integer 
    	Parameter TX_PI_BIASSET bound to: 16'b0000000000000001 
    	Parameter TXPI_CFG bound to: 16'b0000000001010100 
    	Parameter A_TXDIFFCTRL bound to: 16'b0000000000010110 
    	Parameter RX_OUT_DIV bound to: 1 - type: integer 
    	Parameter RX_CLK25_DIV bound to: 10 - type: integer 
    	Parameter RX_DFE_LPM_CFG bound to: 16'b0000100100000100 
    	Parameter RX_PMA_CFG bound to: 32'b00000000000000011000010010000000 
    	Parameter RX_CDR_CFG bound to: 73'b0000000110000000000000000001000111111111100010000001000000000000000100000 
    	Parameter RXCDR_CFG0 bound to: 16'b0000000000000010 
    	Parameter RXCDR_CFG2 bound to: 16'b0000001001101001 
    	Parameter RXCDR_CFG2_GEN2 bound to: 10'b1001100101 
    	Parameter RXCDR_CFG2_GEN4 bound to: 16'b0000000010110100 
    	Parameter RXCDR_CFG3 bound to: 16'b0000000000010010 
    	Parameter RXCDR_CFG3_GEN2 bound to: 6'b011010 
    	Parameter RXCDR_CFG3_GEN3 bound to: 16'b0000000000010010 
    	Parameter RXCDR_CFG3_GEN4 bound to: 16'b0000000000100100 
    	Parameter RX_WIDEMODE_CDR bound to: 2'b00 
    	Parameter RX_XMODE_SEL bound to: 1'b1 
    	Parameter TXDRV_FREQBAND bound to: 0 - type: integer 
    	Parameter TXFE_CFG1 bound to: 16'b0110110000000000 
    	Parameter TXFE_CFG2 bound to: 16'b0110110000000000 
    	Parameter TXFE_CFG3 bound to: 16'b0110110000000000 
    	Parameter TXPI_CFG0 bound to: 16'b0000001100000000 
    	Parameter TXPI_CFG1 bound to: 16'b0001000000000000 
    	Parameter RX_POLARITY bound to: 0 - type: integer 
    	Parameter GTXE2_TRANSCEIVERS bound to: 2 - type: integer 
    	Parameter GTHE3_TRANSCEIVERS bound to: 5 - type: integer 
    	Parameter GTHE4_TRANSCEIVERS bound to: 8 - type: integer 
    	Parameter GTYE4_TRANSCEIVERS bound to: 9 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'GTXE2_CHANNEL' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:21274]
    	Parameter ALIGN_COMMA_DOUBLE bound to: FALSE - type: string 
    	Parameter ALIGN_COMMA_ENABLE bound to: 10'b1111111111 
    	Parameter ALIGN_COMMA_WORD bound to: 4 - type: integer 
    	Parameter ALIGN_MCOMMA_DET bound to: TRUE - type: string 
    	Parameter ALIGN_MCOMMA_VALUE bound to: 10'b1010000011 
    	Parameter ALIGN_PCOMMA_DET bound to: TRUE - type: string 
    	Parameter ALIGN_PCOMMA_VALUE bound to: 10'b0101111100 
    	Parameter CBCC_DATA_SOURCE_SEL bound to: DECODED - type: string 
    	Parameter CHAN_BOND_KEEP_ALIGN bound to: FALSE - type: string 
    	Parameter CHAN_BOND_MAX_SKEW bound to: 1 - type: integer 
    	Parameter CHAN_BOND_SEQ_1_1 bound to: 10'b0000000000 
    	Parameter CHAN_BOND_SEQ_1_2 bound to: 10'b0000000000 
    	Parameter CHAN_BOND_SEQ_1_3 bound to: 10'b0000000000 
    	Parameter CHAN_BOND_SEQ_1_4 bound to: 10'b0000000000 
    	Parameter CHAN_BOND_SEQ_1_ENABLE bound to: 4'b1111 
    	Parameter CHAN_BOND_SEQ_2_1 bound to: 10'b0000000000 
    	Parameter CHAN_BOND_SEQ_2_2 bound to: 10'b0000000000 
    	Parameter CHAN_BOND_SEQ_2_3 bound to: 10'b0000000000 
    	Parameter CHAN_BOND_SEQ_2_4 bound to: 10'b0000000000 
    	Parameter CHAN_BOND_SEQ_2_ENABLE bound to: 4'b1111 
    	Parameter CHAN_BOND_SEQ_2_USE bound to: FALSE - type: string 
    	Parameter CHAN_BOND_SEQ_LEN bound to: 1 - type: integer 
    	Parameter CLK_CORRECT_USE bound to: FALSE - type: string 
    	Parameter CLK_COR_KEEP_IDLE bound to: FALSE - type: string 
    	Parameter CLK_COR_MAX_LAT bound to: 12 - type: integer 
    	Parameter CLK_COR_MIN_LAT bound to: 8 - type: integer 
    	Parameter CLK_COR_PRECEDENCE bound to: TRUE - type: string 
    	Parameter CLK_COR_REPEAT_WAIT bound to: 0 - type: integer 
    	Parameter CLK_COR_SEQ_1_1 bound to: 10'b0100000000 
    	Parameter CLK_COR_SEQ_1_2 bound to: 10'b0000000000 
    	Parameter CLK_COR_SEQ_1_3 bound to: 10'b0000000000 
    	Parameter CLK_COR_SEQ_1_4 bound to: 10'b0000000000 
    	Parameter CLK_COR_SEQ_1_ENABLE bound to: 4'b1111 
    	Parameter CLK_COR_SEQ_2_1 bound to: 10'b0100000000 
    	Parameter CLK_COR_SEQ_2_2 bound to: 10'b0000000000 
    	Parameter CLK_COR_SEQ_2_3 bound to: 10'b0000000000 
    	Parameter CLK_COR_SEQ_2_4 bound to: 10'b0000000000 
    	Parameter CLK_COR_SEQ_2_ENABLE bound to: 4'b1111 
    	Parameter CLK_COR_SEQ_2_USE bound to: FALSE - type: string 
    	Parameter CLK_COR_SEQ_LEN bound to: 1 - type: integer 
    	Parameter CPLL_CFG bound to: 24'b101111000000011111011100 
    	Parameter CPLL_FBDIV bound to: 1 - type: integer 
    	Parameter CPLL_FBDIV_45 bound to: 5 - type: integer 
    	Parameter CPLL_INIT_CFG bound to: 24'b000000000000000000011110 
    	Parameter CPLL_LOCK_CFG bound to: 16'b0000000111101000 
    	Parameter CPLL_REFCLK_DIV bound to: 1 - type: integer 
    	Parameter DEC_MCOMMA_DETECT bound to: TRUE - type: string 
    	Parameter DEC_PCOMMA_DETECT bound to: TRUE - type: string 
    	Parameter DEC_VALID_COMMA_ONLY bound to: FALSE - type: string 
    	Parameter DMONITOR_CFG bound to: 24'b000000000000101000000000 
    	Parameter ES_CONTROL bound to: 6'b000000 
    	Parameter ES_ERRDET_EN bound to: TRUE - type: string 
    	Parameter ES_EYE_SCAN_EN bound to: TRUE - type: string 
    	Parameter ES_HORZ_OFFSET bound to: 12'b000000000000 
    	Parameter ES_PMA_CFG bound to: 10'b0000000000 
    	Parameter ES_PRESCALE bound to: 5'b00000 
    	Parameter ES_QUALIFIER bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 
    	Parameter ES_QUAL_MASK bound to: 80'b11111111111111111111111111111111111111111111111111111111111111111111111111111111 
    	Parameter ES_SDATA_MASK bound to: 80'b11111111111111111111111111111111111111110000000000000000000000000000000000000000 
    	Parameter ES_VERT_OFFSET bound to: 9'b000000000 
    	Parameter FTS_DESKEW_SEQ_ENABLE bound to: 4'b1111 
    	Parameter FTS_LANE_DESKEW_CFG bound to: 4'b1111 
    	Parameter FTS_LANE_DESKEW_EN bound to: FALSE - type: string 
    	Parameter GEARBOX_MODE bound to: 3'b000 
    	Parameter IS_CPLLLOCKDETCLK_INVERTED bound to: 1'b0 
    	Parameter IS_DRPCLK_INVERTED bound to: 1'b0 
    	Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 
    	Parameter IS_RXUSRCLK2_INVERTED bound to: 1'b0 
    	Parameter IS_RXUSRCLK_INVERTED bound to: 1'b0 
    	Parameter IS_TXPHDLYTSTCLK_INVERTED bound to: 1'b0 
    	Parameter IS_TXUSRCLK2_INVERTED bound to: 1'b0 
    	Parameter IS_TXUSRCLK_INVERTED bound to: 1'b0 
    	Parameter OUTREFCLK_SEL_INV bound to: 2'b11 
    	Parameter PCS_PCIE_EN bound to: FALSE - type: string 
    	Parameter PCS_RSVD_ATTR bound to: 48'b000000000000000000000000000000000000000000000000 
    	Parameter PD_TRANS_TIME_FROM_P2 bound to: 12'b000000111100 
    	Parameter PD_TRANS_TIME_NONE_P2 bound to: 8'b00111100 
    	Parameter PD_TRANS_TIME_TO_P2 bound to: 8'b01100100 
    	Parameter PMA_RSV bound to: 32'b00000000000000011000010010000000 
    	Parameter PMA_RSV2 bound to: 16'b0010000001110000 
    	Parameter PMA_RSV3 bound to: 2'b00 
    	Parameter PMA_RSV4 bound to: 0 - type: integer 
    	Parameter RXBUFRESET_TIME bound to: 5'b00001 
    	Parameter RXBUF_ADDR_MODE bound to: FAST - type: string 
    	Parameter RXBUF_EIDLE_HI_CNT bound to: 4'b1000 
    	Parameter RXBUF_EIDLE_LO_CNT bound to: 4'b0000 
    	Parameter RXBUF_EN bound to: TRUE - type: string 
    	Parameter RXBUF_RESET_ON_CB_CHANGE bound to: TRUE - type: string 
    	Parameter RXBUF_RESET_ON_COMMAALIGN bound to: FALSE - type: string 
    	Parameter RXBUF_RESET_ON_EIDLE bound to: FALSE - type: string 
    	Parameter RXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string 
    	Parameter RXBUF_THRESH_OVFLW bound to: 57 - type: integer 
    	Parameter RXBUF_THRESH_OVRD bound to: TRUE - type: string 
    	Parameter RXBUF_THRESH_UNDFLW bound to: 3 - type: integer 
    	Parameter RXCDRFREQRESET_TIME bound to: 5'b00001 
    	Parameter RXCDRPHRESET_TIME bound to: 5'b00001 
    	Parameter RXCDR_CFG bound to: 72'b000000110000000000000000001000111111111100010000001000000000000000100000 
    	Parameter RXCDR_FR_RESET_ON_EIDLE bound to: 1'b0 
    	Parameter RXCDR_HOLD_DURING_EIDLE bound to: 1'b0 
    	Parameter RXCDR_LOCK_CFG bound to: 6'b010101 
    	Parameter RXCDR_PH_RESET_ON_EIDLE bound to: 1'b0 
    	Parameter RXDFELPMRESET_TIME bound to: 7'b0001111 
    	Parameter RXDLY_CFG bound to: 16'b0000000000011111 
    	Parameter RXDLY_LCFG bound to: 9'b000110000 
    	Parameter RXDLY_TAP_CFG bound to: 16'b0000000000000000 
    	Parameter RXGEARBOX_EN bound to: FALSE - type: string 
    	Parameter RXISCANRESET_TIME bound to: 5'b00001 
    	Parameter RXLPM_HF_CFG bound to: 14'b00000011110000 
    	Parameter RXLPM_LF_CFG bound to: 14'b00000011110000 
    	Parameter RXOOB_CFG bound to: 7'b0000110 
    	Parameter RXOUT_DIV bound to: 1 - type: integer 
    	Parameter RXPCSRESET_TIME bound to: 5'b00001 
    	Parameter RXPHDLY_CFG bound to: 24'b000010000100000000100000 
    	Parameter RXPH_CFG bound to: 24'b000000000000000000000000 
    	Parameter RXPH_MONITOR_SEL bound to: 5'b00000 
    	Parameter RXPMARESET_TIME bound to: 5'b00011 
    	Parameter RXPRBS_ERR_LOOPBACK bound to: 1'b0 
    	Parameter RXSLIDE_AUTO_WAIT bound to: 7 - type: integer 
    	Parameter RXSLIDE_MODE bound to: OFF - type: string 
    	Parameter RX_BIAS_CFG bound to: 12'b000000000100 
    	Parameter RX_BUFFER_CFG bound to: 6'b000000 
    	Parameter RX_CLK25_DIV bound to: 10 - type: integer 
    	Parameter RX_CLKMUX_PD bound to: 1'b1 
    	Parameter RX_CM_SEL bound to: 2'b11 
    	Parameter RX_CM_TRIM bound to: 3'b010 
    	Parameter RX_DATA_WIDTH bound to: 40 - type: integer 
    	Parameter RX_DDI_SEL bound to: 6'b000000 
    	Parameter RX_DEBUG_CFG bound to: 12'b000000000000 
    	Parameter RX_DEFER_RESET_BUF_EN bound to: TRUE - type: string 
    	Parameter RX_DFE_GAIN_CFG bound to: 23'b00000100000111111101010 
    	Parameter RX_DFE_H2_CFG bound to: 12'b000000000000 
    	Parameter RX_DFE_H3_CFG bound to: 12'b000001000000 
    	Parameter RX_DFE_H4_CFG bound to: 11'b00011110000 
    	Parameter RX_DFE_H5_CFG bound to: 11'b00011100000 
    	Parameter RX_DFE_KL_CFG bound to: 13'b0000011111110 
    	Parameter RX_DFE_KL_CFG2 bound to: 806439084 - type: integer 
    	Parameter RX_DFE_LPM_CFG bound to: 16'b0000100100000100 
    	Parameter RX_DFE_LPM_HOLD_DURING_EIDLE bound to: 1'b0 
    	Parameter RX_DFE_UT_CFG bound to: 17'b10001111000000000 
    	Parameter RX_DFE_VP_CFG bound to: 17'b00011111100000011 
    	Parameter RX_DFE_XYD_CFG bound to: 13'b0000000000000 
    	Parameter RX_DISPERR_SEQ_MATCH bound to: TRUE - type: string 
    	Parameter RX_INT_DATAWIDTH bound to: 1 - type: integer 
    	Parameter RX_OS_CFG bound to: 13'b0000010000000 
    	Parameter RX_SIG_VALID_DLY bound to: 10 - type: integer 
    	Parameter RX_XCLK_SEL bound to: RXREC - type: string 
    	Parameter SAS_MAX_COM bound to: 64 - type: integer 
    	Parameter SAS_MIN_COM bound to: 36 - type: integer 
    	Parameter SATA_BURST_SEQ_LEN bound to: 4'b0101 
    	Parameter SATA_BURST_VAL bound to: 3'b111 
    	Parameter SATA_CPLL_CFG bound to: VCO_3000MHZ - type: string 
    	Parameter SATA_EIDLE_VAL bound to: 3'b111 
    	Parameter SATA_MAX_BURST bound to: 8 - type: integer 
    	Parameter SATA_MAX_INIT bound to: 21 - type: integer 
    	Parameter SATA_MAX_WAKE bound to: 7 - type: integer 
    	Parameter SATA_MIN_BURST bound to: 4 - type: integer 
    	Parameter SATA_MIN_INIT bound to: 12 - type: integer 
    	Parameter SATA_MIN_WAKE bound to: 4 - type: integer 
    	Parameter SHOW_REALIGN_COMMA bound to: TRUE - type: string 
    	Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 
    	Parameter SIM_RECEIVER_DETECT_PASS bound to: TRUE - type: string 
    	Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string 
    	Parameter SIM_TX_EIDLE_DRIVE_LEVEL bound to: X - type: string 
    	Parameter SIM_VERSION bound to: 4.0 - type: string 
    	Parameter TERM_RCAL_CFG bound to: 5'b10000 
    	Parameter TERM_RCAL_OVRD bound to: 1'b0 
    	Parameter TRANS_TIME_RATE bound to: 8'b00001110 
    	Parameter TST_RSV bound to: 0 - type: integer 
    	Parameter TXBUF_EN bound to: TRUE - type: string 
    	Parameter TXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string 
    	Parameter TXDLY_CFG bound to: 16'b0000000000011111 
    	Parameter TXDLY_LCFG bound to: 9'b000110000 
    	Parameter TXDLY_TAP_CFG bound to: 16'b0000000000000000 
    	Parameter TXGEARBOX_EN bound to: FALSE - type: string 
    	Parameter TXOUT_DIV bound to: 1 - type: integer 
    	Parameter TXPCSRESET_TIME bound to: 5'b00001 
    	Parameter TXPHDLY_CFG bound to: 24'b000010000100000000100000 
    	Parameter TXPH_CFG bound to: 16'b0000011110000000 
    	Parameter TXPH_MONITOR_SEL bound to: 5'b00000 
    	Parameter TXPMARESET_TIME bound to: 5'b00001 
    	Parameter TX_CLK25_DIV bound to: 10 - type: integer 
    	Parameter TX_CLKMUX_PD bound to: 1'b1 
    	Parameter TX_DATA_WIDTH bound to: 40 - type: integer 
    	Parameter TX_DEEMPH0 bound to: 5'b00000 
    	Parameter TX_DEEMPH1 bound to: 5'b00000 
    	Parameter TX_DRIVE_MODE bound to: DIRECT - type: string 
    	Parameter TX_EIDLE_ASSERT_DELAY bound to: 3'b110 
    	Parameter TX_EIDLE_DEASSERT_DELAY bound to: 3'b100 
    	Parameter TX_INT_DATAWIDTH bound to: 1 - type: integer 
    	Parameter TX_LOOPBACK_DRIVE_HIZ bound to: FALSE - type: string 
    	Parameter TX_MAINCURSOR_SEL bound to: 1'b0 
    	Parameter TX_MARGIN_FULL_0 bound to: 7'b1001110 
    	Parameter TX_MARGIN_FULL_1 bound to: 7'b1001001 
    	Parameter TX_MARGIN_FULL_2 bound to: 7'b1000101 
    	Parameter TX_MARGIN_FULL_3 bound to: 7'b1000010 
    	Parameter TX_MARGIN_FULL_4 bound to: 7'b1000000 
    	Parameter TX_MARGIN_LOW_0 bound to: 7'b1000110 
    	Parameter TX_MARGIN_LOW_1 bound to: 7'b1000100 
    	Parameter TX_MARGIN_LOW_2 bound to: 7'b1000010 
    	Parameter TX_MARGIN_LOW_3 bound to: 7'b1000000 
    	Parameter TX_MARGIN_LOW_4 bound to: 7'b1000000 
    	Parameter TX_PREDRIVER_MODE bound to: 1'b0 
    	Parameter TX_QPI_STATUS_EN bound to: 1'b0 
    	Parameter TX_RXDETECT_CFG bound to: 14'b01100000110010 
    	Parameter TX_RXDETECT_REF bound to: 3'b100 
    	Parameter TX_XCLK_SEL bound to: TXOUT - type: string 
    	Parameter UCODEER_CLR bound to: 1'b0 
    INFO: [Synth 8-6155] done synthesizing module 'GTXE2_CHANNEL' (268#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:21274]
    INFO: [Synth 8-6155] done synthesizing module 'util_adxcvr_xch' (269#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_adxcvr/util_adxcvr_xch.v:38]
    WARNING: [Synth 8-7023] instance 'i_xch' of module 'util_adxcvr_xch' has 63 connections declared, but only 56 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/785d/axi_xcvrlb_1.v:263]
    INFO: [Synth 8-6155] done synthesizing module 'axi_xcvrlb_1' (270#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/785d/axi_xcvrlb_1.v:38]
    INFO: [Synth 8-6157] synthesizing module 'up_axi__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_axi.v:38]
    	Parameter AXI_ADDRESS_WIDTH bound to: 10 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_axi__parameterized1' (270#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_axi.v:38]
    WARNING: [Synth 8-689] width (16) of port connection 'up_axi_awaddr' does not match port width (10) of module 'up_axi__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/785d/axi_xcvrlb.v:191]
    WARNING: [Synth 8-689] width (16) of port connection 'up_axi_araddr' does not match port width (10) of module 'up_axi__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/785d/axi_xcvrlb.v:201]
    INFO: [Synth 8-6155] done synthesizing module 'axi_xcvrlb' (271#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/785d/axi_xcvrlb.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'system_axi_pz_xcvrlb_0' (272#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_pz_xcvrlb_0/synth/system_axi_pz_xcvrlb_0.v:57]
    INFO: [Synth 8-638] synthesizing module 'system_axi_spdif_tx_core_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_spdif_tx_core_0/synth/system_axi_spdif_tx_core_0.vhd:93]
    	Parameter S_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter S_AXI_ADDRESS_WIDTH bound to: 16 - type: integer 
    	Parameter DEVICE_FAMILY bound to: virtex6 - type: string 
    	Parameter DMA_TYPE bound to: 1 - type: integer 
    INFO: [Synth 8-3491] module 'axi_spdif_tx' declared at '/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/422e/axi_spdif_tx.vhd:45' bound to instance 'U0' of component 'axi_spdif_tx' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_spdif_tx_core_0/synth/system_axi_spdif_tx_core_0.vhd:193]
    INFO: [Synth 8-638] synthesizing module 'axi_spdif_tx' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/422e/axi_spdif_tx.vhd:105]
    	Parameter S_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter S_AXI_ADDRESS_WIDTH bound to: 16 - type: integer 
    	Parameter DEVICE_FAMILY bound to: virtex6 - type: string 
    	Parameter DMA_TYPE bound to: 1 - type: integer 
    INFO: [Synth 8-638] synthesizing module 'pl330_dma_fifo__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/pl330_dma_fifo.vhd:81]
    	Parameter RAM_ADDR_WIDTH bound to: 3 - type: integer 
    	Parameter FIFO_DWIDTH bound to: 32 - type: integer 
    	Parameter FIFO_DIRECTION bound to: 0 - type: integer 
    INFO: [Synth 8-638] synthesizing module 'dma_fifo__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/dma_fifo.vhd:62]
    	Parameter RAM_ADDR_WIDTH bound to: 3 - type: integer 
    	Parameter FIFO_DWIDTH bound to: 32 - type: integer 
    INFO: [Synth 8-256] done synthesizing module 'dma_fifo__parameterized0' (272#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/dma_fifo.vhd:62]
    INFO: [Synth 8-256] done synthesizing module 'pl330_dma_fifo__parameterized1' (272#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/pl330_dma_fifo.vhd:81]
    	Parameter DATA_WIDTH bound to: 16 - type: integer 
    INFO: [Synth 8-3491] module 'tx_encoder' declared at '/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/422e/tx_encoder.vhd:56' bound to instance 'TENC' of component 'tx_encoder' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/422e/axi_spdif_tx.vhd:230]
    INFO: [Synth 8-638] synthesizing module 'tx_encoder' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/422e/tx_encoder.vhd:77]
    	Parameter DATA_WIDTH bound to: 16 - type: integer 
    INFO: [Synth 8-226] default block is never used [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/422e/tx_encoder.vhd:254]
    INFO: [Synth 8-256] done synthesizing module 'tx_encoder' (273#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/422e/tx_encoder.vhd:77]
    INFO: [Synth 8-638] synthesizing module 'axi_ctrlif__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/axi_ctrlif.vhd:84]
    	Parameter C_NUM_REG bound to: 4 - type: integer 
    	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
    	Parameter C_S_AXI_ADDR_WIDTH bound to: 16 - type: integer 
    	Parameter C_FAMILY bound to: virtex6 - type: string 
    INFO: [Synth 8-256] done synthesizing module 'axi_ctrlif__parameterized0' (273#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/axi_ctrlif.vhd:84]
    INFO: [Synth 8-256] done synthesizing module 'axi_spdif_tx' (274#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/422e/axi_spdif_tx.vhd:105]
    INFO: [Synth 8-256] done synthesizing module 'system_axi_spdif_tx_core_0' (275#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_spdif_tx_core_0/synth/system_axi_spdif_tx_core_0.vhd:93]
    INFO: [Synth 8-6157] synthesizing module 'system_axi_sysid_0_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_sysid_0_0/synth/system_axi_sysid_0_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'axi_sysid' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/6492/axi_sysid.v:3]
    	Parameter ROM_WIDTH bound to: 32 - type: integer 
    	Parameter ROM_ADDR_BITS bound to: 9 - type: integer 
    	Parameter AXI_ADDRESS_WIDTH bound to: 12 - type: integer 
    	Parameter CORE_VERSION bound to: 32'b00000000000000010000000001100001 
    	Parameter CORE_MAGIC bound to: 1398360388 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'up_axi__parameterized2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_axi.v:38]
    	Parameter AXI_ADDRESS_WIDTH bound to: 13 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'up_axi__parameterized2' (275#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/up_axi.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'axi_sysid' (276#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/6492/axi_sysid.v:3]
    INFO: [Synth 8-6155] done synthesizing module 'system_axi_sysid_0_0' (277#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_sysid_0_0/synth/system_axi_sysid_0_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'system_rom_sys_0_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_rom_sys_0_0/synth/system_rom_sys_0_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'sysid_rom' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/a6f2/sysid_rom.v:3]
    	Parameter ROM_WIDTH bound to: 32 - type: integer 
    	Parameter ROM_ADDR_BITS bound to: 9 - type: integer 
    	Parameter PATH_TO_FILE bound to: /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/mem_init_sys.txt - type: string 
    INFO: [Synth 8-3876] $readmem data file '/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/mem_init_sys.txt' is read successfully [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/a6f2/sysid_rom.v:15]
    INFO: [Synth 8-6155] done synthesizing module 'sysid_rom' (278#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/a6f2/sysid_rom.v:3]
    INFO: [Synth 8-6155] done synthesizing module 'system_rom_sys_0_0' (279#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_rom_sys_0_0/synth/system_rom_sys_0_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'system_sys_audio_clkgen_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0.v:70]
    INFO: [Synth 8-6157] synthesizing module 'system_sys_audio_clkgen_0_clk_wiz' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0_clk_wiz.v:68]
    INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV__parameterized0' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:39813]
    	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
    	Parameter CLKFBOUT_MULT_F bound to: 44.375000 - type: float 
    	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string 
    	Parameter CLKIN1_PERIOD bound to: 5.000000 - type: float 
    	Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float 
    	Parameter CLKOUT0_DIVIDE_F bound to: 80.250000 - type: float 
    	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string 
    	Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer 
    	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string 
    	Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer 
    	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string 
    	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 
    	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string 
    	Parameter CLKOUT4_CASCADE bound to: FALSE - type: string 
    	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
    	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string 
    	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
    	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string 
    	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
    	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string 
    	Parameter COMPENSATION bound to: ZHOLD - type: string 
    	Parameter DIVCLK_DIVIDE bound to: 9 - type: integer 
    	Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 
    	Parameter IS_PSEN_INVERTED bound to: 1'b0 
    	Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 
    	Parameter IS_PWRDWN_INVERTED bound to: 1'b0 
    	Parameter IS_RST_INVERTED bound to: 1'b0 
    	Parameter REF_JITTER1 bound to: 0.010000 - type: float 
    	Parameter REF_JITTER2 bound to: 0.010000 - type: float 
    	Parameter SS_EN bound to: FALSE - type: string 
    	Parameter SS_MODE bound to: CENTER_HIGH - type: string 
    	Parameter SS_MOD_PERIOD bound to: 10000 - type: integer 
    	Parameter STARTUP_WAIT bound to: FALSE - type: string 
    INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV__parameterized0' (279#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:39813]
    INFO: [Synth 8-6155] done synthesizing module 'system_sys_audio_clkgen_0_clk_wiz' (280#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0_clk_wiz.v:68]
    INFO: [Synth 8-6155] done synthesizing module 'system_sys_audio_clkgen_0' (281#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0.v:70]
    INFO: [Synth 8-6157] synthesizing module 'system_sys_concat_intc_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_concat_intc_0/synth/system_sys_concat_intc_0.v:58]
    INFO: [Synth 8-6157] synthesizing module 'xlconcat_v2_1_3_xlconcat' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/442e/hdl/xlconcat_v2_1_vl_rfs.v:14]
    	Parameter IN0_WIDTH bound to: 1 - type: integer 
    	Parameter IN1_WIDTH bound to: 1 - type: integer 
    	Parameter IN2_WIDTH bound to: 1 - type: integer 
    	Parameter IN3_WIDTH bound to: 1 - type: integer 
    	Parameter IN4_WIDTH bound to: 1 - type: integer 
    	Parameter IN5_WIDTH bound to: 1 - type: integer 
    	Parameter IN6_WIDTH bound to: 1 - type: integer 
    	Parameter IN7_WIDTH bound to: 1 - type: integer 
    	Parameter IN8_WIDTH bound to: 1 - type: integer 
    	Parameter IN9_WIDTH bound to: 1 - type: integer 
    	Parameter IN10_WIDTH bound to: 1 - type: integer 
    	Parameter IN11_WIDTH bound to: 1 - type: integer 
    	Parameter IN12_WIDTH bound to: 1 - type: integer 
    	Parameter IN13_WIDTH bound to: 1 - type: integer 
    	Parameter IN14_WIDTH bound to: 1 - type: integer 
    	Parameter IN15_WIDTH bound to: 1 - type: integer 
    	Parameter IN16_WIDTH bound to: 1 - type: integer 
    	Parameter IN17_WIDTH bound to: 1 - type: integer 
    	Parameter IN18_WIDTH bound to: 1 - type: integer 
    	Parameter IN19_WIDTH bound to: 1 - type: integer 
    	Parameter IN20_WIDTH bound to: 1 - type: integer 
    	Parameter IN21_WIDTH bound to: 1 - type: integer 
    	Parameter IN22_WIDTH bound to: 1 - type: integer 
    	Parameter IN23_WIDTH bound to: 1 - type: integer 
    	Parameter IN24_WIDTH bound to: 1 - type: integer 
    	Parameter IN25_WIDTH bound to: 1 - type: integer 
    	Parameter IN26_WIDTH bound to: 1 - type: integer 
    	Parameter IN27_WIDTH bound to: 1 - type: integer 
    	Parameter IN28_WIDTH bound to: 1 - type: integer 
    	Parameter IN29_WIDTH bound to: 1 - type: integer 
    	Parameter IN30_WIDTH bound to: 1 - type: integer 
    	Parameter IN31_WIDTH bound to: 1 - type: integer 
    	Parameter dout_width bound to: 16 - type: integer 
    	Parameter NUM_PORTS bound to: 16 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'xlconcat_v2_1_3_xlconcat' (282#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/442e/hdl/xlconcat_v2_1_vl_rfs.v:14]
    INFO: [Synth 8-6155] done synthesizing module 'system_sys_concat_intc_0' (283#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_concat_intc_0/synth/system_sys_concat_intc_0.v:58]
    INFO: [Synth 8-6157] synthesizing module 'system_sys_logic_inv_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_logic_inv_0/synth/system_sys_logic_inv_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'util_vector_logic_v2_0_1_util_vector_logic' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/2137/hdl/util_vector_logic_v2_0_vl_rfs.v:45]
    	Parameter C_OPERATION bound to: not - type: string 
    	Parameter C_SIZE bound to: 1 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'util_vector_logic_v2_0_1_util_vector_logic' (284#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/2137/hdl/util_vector_logic_v2_0_vl_rfs.v:45]
    INFO: [Synth 8-6155] done synthesizing module 'system_sys_logic_inv_0' (285#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_logic_inv_0/synth/system_sys_logic_inv_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'system_sys_ps7_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_ps7_0/synth/system_sys_ps7_0.v:60]
    INFO: [Synth 8-6157] synthesizing module 'processing_system7_v5_5_processing_system7' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_ps7_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:162]
    	Parameter C_USE_DEFAULT_ACP_USER_VAL bound to: 0 - type: integer 
    	Parameter C_S_AXI_ACP_ARUSER_VAL bound to: 31 - type: integer 
    	Parameter C_S_AXI_ACP_AWUSER_VAL bound to: 31 - type: integer 
    	Parameter C_M_AXI_GP0_THREAD_ID_WIDTH bound to: 12 - type: integer 
    	Parameter C_M_AXI_GP1_THREAD_ID_WIDTH bound to: 12 - type: integer 
    	Parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP bound to: 0 - type: integer 
    	Parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP bound to: 0 - type: integer 
    	Parameter C_M_AXI_GP0_ID_WIDTH bound to: 12 - type: integer 
    	Parameter C_M_AXI_GP1_ID_WIDTH bound to: 12 - type: integer 
    	Parameter C_S_AXI_GP0_ID_WIDTH bound to: 6 - type: integer 
    	Parameter C_S_AXI_GP1_ID_WIDTH bound to: 6 - type: integer 
    	Parameter C_S_AXI_HP0_ID_WIDTH bound to: 6 - type: integer 
    	Parameter C_S_AXI_HP1_ID_WIDTH bound to: 6 - type: integer 
    	Parameter C_S_AXI_HP2_ID_WIDTH bound to: 6 - type: integer 
    	Parameter C_S_AXI_HP3_ID_WIDTH bound to: 6 - type: integer 
    	Parameter C_S_AXI_ACP_ID_WIDTH bound to: 3 - type: integer 
    	Parameter C_S_AXI_HP0_DATA_WIDTH bound to: 64 - type: integer 
    	Parameter C_S_AXI_HP1_DATA_WIDTH bound to: 64 - type: integer 
    	Parameter C_S_AXI_HP2_DATA_WIDTH bound to: 64 - type: integer 
    	Parameter C_S_AXI_HP3_DATA_WIDTH bound to: 64 - type: integer 
    	Parameter C_INCLUDE_ACP_TRANS_CHECK bound to: 0 - type: integer 
    	Parameter C_NUM_F2P_INTR_INPUTS bound to: 16 - type: integer 
    	Parameter C_FCLK_CLK0_BUF bound to: TRUE - type: string 
    	Parameter C_FCLK_CLK1_BUF bound to: TRUE - type: string 
    	Parameter C_FCLK_CLK2_BUF bound to: TRUE - type: string 
    	Parameter C_FCLK_CLK3_BUF bound to: FALSE - type: string 
    	Parameter C_EMIO_GPIO_WIDTH bound to: 64 - type: integer 
    	Parameter C_INCLUDE_TRACE_BUFFER bound to: 0 - type: integer 
    	Parameter C_TRACE_BUFFER_FIFO_SIZE bound to: 128 - type: integer 
    	Parameter C_TRACE_BUFFER_CLOCK_DELAY bound to: 12 - type: integer 
    	Parameter USE_TRACE_DATA_EDGE_DETECTOR bound to: 0 - type: integer 
    	Parameter C_TRACE_PIPELINE_WIDTH bound to: 8 - type: integer 
    	Parameter C_PS7_SI_REV bound to: PRODUCTION - type: string 
    	Parameter C_EN_EMIO_ENET0 bound to: 0 - type: integer 
    	Parameter C_EN_EMIO_ENET1 bound to: 1 - type: integer 
    	Parameter C_EN_EMIO_TRACE bound to: 0 - type: integer 
    	Parameter C_DQ_WIDTH bound to: 32 - type: integer 
    	Parameter C_DQS_WIDTH bound to: 4 - type: integer 
    	Parameter C_DM_WIDTH bound to: 4 - type: integer 
    	Parameter C_MIO_PRIMITIVE bound to: 54 - type: integer 
    	Parameter C_PACKAGE_NAME bound to: fbg676 - type: string 
    	Parameter C_IRQ_F2P_MODE bound to: REVERSE - type: string 
    	Parameter C_TRACE_INTERNAL_WIDTH bound to: 2 - type: integer 
    	Parameter C_EN_EMIO_PJTAG bound to: 0 - type: integer 
    	Parameter C_USE_AXI_NONSECURE bound to: 0 - type: integer 
    	Parameter C_USE_S_AXI_HP0 bound to: 1 - type: integer 
    	Parameter C_USE_S_AXI_HP1 bound to: 1 - type: integer 
    	Parameter C_USE_S_AXI_HP2 bound to: 1 - type: integer 
    	Parameter C_USE_S_AXI_HP3 bound to: 0 - type: integer 
    	Parameter C_USE_M_AXI_GP0 bound to: 1 - type: integer 
    	Parameter C_USE_M_AXI_GP1 bound to: 0 - type: integer 
    	Parameter C_USE_S_AXI_GP0 bound to: 0 - type: integer 
    	Parameter C_USE_S_AXI_GP1 bound to: 0 - type: integer 
    	Parameter C_USE_S_AXI_ACP bound to: 0 - type: integer 
    	Parameter C_GP0_EN_MODIFIABLE_TXN bound to: 1 - type: integer 
    	Parameter C_GP1_EN_MODIFIABLE_TXN bound to: 1 - type: integer 
    INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_ps7_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:1348]
    INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_ps7_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:1349]
    INFO: [Synth 8-6157] synthesizing module 'BIBUF' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:722]
    INFO: [Synth 8-6155] done synthesizing module 'BIBUF' (286#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:722]
    INFO: [Synth 8-6157] synthesizing module 'PS7' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:61707]
    INFO: [Synth 8-6155] done synthesizing module 'PS7' (287#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:61707]
    INFO: [Synth 8-6155] done synthesizing module 'processing_system7_v5_5_processing_system7' (288#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_ps7_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:162]
    WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_ps7_0/synth/system_sys_ps7_0.v:978]
    INFO: [Synth 8-6155] done synthesizing module 'system_sys_ps7_0' (289#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_ps7_0/synth/system_sys_ps7_0.v:60]
    WARNING: [Synth 8-7023] instance 'sys_ps7' of module 'system_sys_ps7_0' has 275 connections declared, but only 229 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:3838]
    INFO: [Synth 8-638] synthesizing module 'system_sys_rgmii_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0.vhd:128]
    INFO: [Synth 8-3491] module 'system_sys_rgmii_0_support' declared at '/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_support.vhd:65' bound to instance 'U0' of component 'system_sys_rgmii_0_support' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0.vhd:193]
    INFO: [Synth 8-638] synthesizing module 'system_sys_rgmii_0_support' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_support.vhd:115]
    INFO: [Synth 8-3491] module 'system_sys_rgmii_0_clocking' declared at '/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocking.vhd:62' bound to instance 'i_system_sys_rgmii_0_clocking' of component 'system_sys_rgmii_0_clocking' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_support.vhd:205]
    INFO: [Synth 8-638] synthesizing module 'system_sys_rgmii_0_clocking' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocking.vhd:75]
    INFO: [Synth 8-113] binding component instance 'i_bufg_clk_in' to cell 'BUFG' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocking.vhd:92]
    	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
    	Parameter CLKFBOUT_MULT_F bound to: 5.000000 - type: float 
    	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKFBOUT_USE_FINE_PS bound to: 0 - type: bool 
    	Parameter CLKIN1_PERIOD bound to: 5.000000 - type: float 
    	Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float 
    	Parameter CLKOUT0_DIVIDE_F bound to: 8.000000 - type: float 
    	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT0_USE_FINE_PS bound to: 0 - type: bool 
    	Parameter CLKOUT1_DIVIDE bound to: 40 - type: integer 
    	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT1_USE_FINE_PS bound to: 0 - type: bool 
    	Parameter CLKOUT2_DIVIDE bound to: 100 - type: integer 
    	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT2_USE_FINE_PS bound to: 0 - type: bool 
    	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 
    	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT3_USE_FINE_PS bound to: 0 - type: bool 
    	Parameter CLKOUT4_CASCADE bound to: 0 - type: bool 
    	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
    	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT4_USE_FINE_PS bound to: 0 - type: bool 
    	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
    	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT5_USE_FINE_PS bound to: 0 - type: bool 
    	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
    	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float 
    	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float 
    	Parameter CLKOUT6_USE_FINE_PS bound to: 0 - type: bool 
    	Parameter COMPENSATION bound to: ZHOLD - type: string 
    	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 
    	Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 
    	Parameter IS_PSEN_INVERTED bound to: 1'b0 
    	Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 
    	Parameter IS_PWRDWN_INVERTED bound to: 1'b0 
    	Parameter IS_RST_INVERTED bound to: 1'b0 
    	Parameter REF_JITTER1 bound to: 0.010000 - type: float 
    	Parameter REF_JITTER2 bound to: 0.000000 - type: float 
    	Parameter SS_EN bound to: FALSE - type: string 
    	Parameter SS_MODE bound to: CENTER_HIGH - type: string 
    	Parameter SS_MOD_PERIOD bound to: 10000 - type: integer 
    	Parameter STARTUP_WAIT bound to: 0 - type: bool 
    INFO: [Synth 8-113] binding component instance 'mmcm_adv_inst' to cell 'MMCME2_ADV' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocking.vhd:96]
    	Parameter BUFR_DIVIDE bound to: 4 - type: string 
    	Parameter SIM_DEVICE bound to: 7SERIES - type: string 
    INFO: [Synth 8-113] binding component instance 'clk10_div_buf' to cell 'BUFR' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocking.vhd:164]
    INFO: [Synth 8-256] done synthesizing module 'system_sys_rgmii_0_clocking' (290#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocking.vhd:75]
    INFO: [Synth 8-3491] module 'system_sys_rgmii_0_resets' declared at '/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_resets.vhd:61' bound to instance 'i_system_sys_rgmii_0_resets' of component 'system_sys_rgmii_0_resets' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_support.vhd:226]
    INFO: [Synth 8-638] synthesizing module 'system_sys_rgmii_0_resets' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_resets.vhd:69]
    INFO: [Synth 8-3491] module 'system_sys_rgmii_0_reset_sync' declared at '/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_reset_sync.vhd:66' bound to instance 'idelayctrl_reset_gen' of component 'system_sys_rgmii_0_reset_sync' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_resets.vhd:89]
    INFO: [Synth 8-638] synthesizing module 'system_sys_rgmii_0_reset_sync' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_reset_sync.vhd:82]
    	Parameter INITIALISE bound to: 2'b11 
    	Parameter INIT bound to: 1'b1 
    INFO: [Synth 8-113] binding component instance 'reset_sync1' to cell 'FDP' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_reset_sync.vhd:111]
    	Parameter INIT bound to: 1'b1 
    INFO: [Synth 8-113] binding component instance 'reset_sync2' to cell 'FDP' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_reset_sync.vhd:122]
    	Parameter INIT bound to: 1'b1 
    INFO: [Synth 8-113] binding component instance 'reset_sync3' to cell 'FDP' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_reset_sync.vhd:133]
    	Parameter INIT bound to: 1'b1 
    INFO: [Synth 8-113] binding component instance 'reset_sync4' to cell 'FDP' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_reset_sync.vhd:144]
    	Parameter INIT bound to: 1'b1 
    INFO: [Synth 8-113] binding component instance 'reset_sync5' to cell 'FDP' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_reset_sync.vhd:155]
    	Parameter INIT bound to: 1'b1 
    INFO: [Synth 8-113] binding component instance 'reset_sync6' to cell 'FDP' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_reset_sync.vhd:166]
    INFO: [Synth 8-256] done synthesizing module 'system_sys_rgmii_0_reset_sync' (291#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_reset_sync.vhd:82]
    INFO: [Synth 8-256] done synthesizing module 'system_sys_rgmii_0_resets' (292#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_resets.vhd:69]
    	Parameter SIM_DEVICE bound to: 7SERIES - type: string 
    INFO: [Synth 8-113] binding component instance 'i_system_sys_rgmii_0_idelayctrl' to cell 'IDELAYCTRL' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_support.vhd:233]
    INFO: [Synth 8-3491] module 'system_sys_rgmii_0_block' declared at '/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_block.vhd:87' bound to instance 'i_gmii_to_rgmii_block' of component 'system_sys_rgmii_0_block' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_support.vhd:244]
    INFO: [Synth 8-638] synthesizing module 'system_sys_rgmii_0_block' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_block.vhd:136]
    	Parameter CLK_SEL_TYPE bound to: SYNC - type: string 
    INFO: [Synth 8-113] binding component instance 'i_bufgmux_gmii_clk_25m_2_5m' to cell 'BUFGMUX' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_block.vhd:207]
    	Parameter CLK_SEL_TYPE bound to: SYNC - type: string 
    INFO: [Synth 8-113] binding component instance 'i_bufgmux_gmii_clk' to cell 'BUFGMUX' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_block.vhd:215]
    	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
    	Parameter DRIVE bound to: 12 - type: integer 
    	Parameter IOSTANDARD bound to: DEFAULT - type: string 
    	Parameter SLEW bound to: SLOW - type: string 
    INFO: [Synth 8-113] binding component instance 'rgmii_txc_obuf_i' to cell 'OBUF' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_block.vhd:225]
    	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
    	Parameter DRIVE bound to: 12 - type: integer 
    	Parameter IOSTANDARD bound to: DEFAULT - type: string 
    	Parameter SLEW bound to: SLOW - type: string 
    INFO: [Synth 8-113] binding component instance 'rgmii_tx_ctl_obuf_i' to cell 'OBUF' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_block.vhd:231]
    	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
    	Parameter DRIVE bound to: 12 - type: integer 
    	Parameter IOSTANDARD bound to: DEFAULT - type: string 
    	Parameter SLEW bound to: SLOW - type: string 
    INFO: [Synth 8-113] binding component instance 'rgmii_txd_obuf_i' to cell 'OBUF' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_block.vhd:238]
    	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
    	Parameter DRIVE bound to: 12 - type: integer 
    	Parameter IOSTANDARD bound to: DEFAULT - type: string 
    	Parameter SLEW bound to: SLOW - type: string 
    INFO: [Synth 8-113] binding component instance 'rgmii_txd_obuf_i' to cell 'OBUF' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_block.vhd:238]
    	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
    	Parameter DRIVE bound to: 12 - type: integer 
    	Parameter IOSTANDARD bound to: DEFAULT - type: string 
    	Parameter SLEW bound to: SLOW - type: string 
    INFO: [Synth 8-113] binding component instance 'rgmii_txd_obuf_i' to cell 'OBUF' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_block.vhd:238]
    	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
    	Parameter DRIVE bound to: 12 - type: integer 
    	Parameter IOSTANDARD bound to: DEFAULT - type: string 
    	Parameter SLEW bound to: SLOW - type: string 
    INFO: [Synth 8-113] binding component instance 'rgmii_txd_obuf_i' to cell 'OBUF' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_block.vhd:238]
    	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
    	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
    	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
    	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
    	Parameter IOSTANDARD bound to: DEFAULT - type: string 
    INFO: [Synth 8-113] binding component instance 'rgmii_rxc_ibuf_i' to cell 'IBUF' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_block.vhd:245]
    	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
    	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
    	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
    	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
    	Parameter IOSTANDARD bound to: DEFAULT - type: string 
    INFO: [Synth 8-113] binding component instance 'rgmii_rx_ctl_ibuf_i' to cell 'IBUF' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_block.vhd:251]
    	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
    	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
    	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
    	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
    	Parameter IOSTANDARD bound to: DEFAULT - type: string 
    INFO: [Synth 8-113] binding component instance 'rgmii_rxd_ibuf_i' to cell 'IBUF' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_block.vhd:258]
    	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
    	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
    	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
    	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
    	Parameter IOSTANDARD bound to: DEFAULT - type: string 
    INFO: [Synth 8-113] binding component instance 'rgmii_rxd_ibuf_i' to cell 'IBUF' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_block.vhd:258]
    	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
    	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
    	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
    	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
    	Parameter IOSTANDARD bound to: DEFAULT - type: string 
    INFO: [Synth 8-113] binding component instance 'rgmii_rxd_ibuf_i' to cell 'IBUF' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_block.vhd:258]
    	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
    	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
    	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
    	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
    	Parameter IOSTANDARD bound to: DEFAULT - type: string 
    INFO: [Synth 8-113] binding component instance 'rgmii_rxd_ibuf_i' to cell 'IBUF' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_block.vhd:258]
    	Parameter C_RGMII_TXC_SKEW_EN bound to: 0 - type: integer 
    	Parameter C_RGMII_TXC_ODELAY_VAL bound to: 0 - type: integer 
    	Parameter C_DEVICE_TYPE bound to: 0 - type: integer 
    	Parameter C_PHYADDR bound to: 5'b01000 
    INFO: [Synth 8-3491] module 'gmii_to_rgmii_v4_0_7' declared at '/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/9a94/hdl/gmii_to_rgmii_v4_0_vhsyn_rfs.vhd:2452' bound to instance 'system_sys_rgmii_0_core' of component 'gmii_to_rgmii_v4_0_7' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_block.vhd:266]
    INFO: [Synth 8-256] done synthesizing module 'system_sys_rgmii_0_block' (300#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_block.vhd:136]
    INFO: [Synth 8-256] done synthesizing module 'system_sys_rgmii_0_support' (301#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_support.vhd:115]
    INFO: [Synth 8-256] done synthesizing module 'system_sys_rgmii_0' (302#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0.vhd:128]
    WARNING: [Synth 8-7023] instance 'sys_rgmii' of module 'system_sys_rgmii_0' has 36 connections declared, but only 27 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:4068]
    INFO: [Synth 8-638] synthesizing module 'system_sys_rgmii_rstgen_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_rstgen_0/synth/system_sys_rgmii_rstgen_0.vhd:74]
    	Parameter C_FAMILY bound to: zynq - type: string 
    	Parameter C_EXT_RST_WIDTH bound to: 1 - type: integer 
    	Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer 
    	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
    	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
    	Parameter C_NUM_BUS_RST bound to: 1 - type: integer 
    	Parameter C_NUM_PERP_RST bound to: 1 - type: integer 
    	Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer 
    	Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer 
    INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1264' bound to instance 'U0' of component 'proc_sys_reset' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_rstgen_0/synth/system_sys_rgmii_rstgen_0.vhd:129]
    INFO: [Synth 8-638] synthesizing module 'proc_sys_reset__parameterized2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323]
    	Parameter C_FAMILY bound to: zynq - type: string 
    	Parameter C_EXT_RST_WIDTH bound to: 1 - type: integer 
    	Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer 
    	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
    	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
    	Parameter C_NUM_BUS_RST bound to: 1 - type: integer 
    	Parameter C_NUM_PERP_RST bound to: 1 - type: integer 
    	Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer 
    	Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer 
    	Parameter INIT bound to: 1'b1 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1392]
    	Parameter INIT bound to: 1'b1 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1408]
    	Parameter INIT bound to: 1'b0 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1434]
    	Parameter INIT bound to: 1'b1 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1457]
    	Parameter INIT bound to: 1'b0 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1481]
    INFO: [Synth 8-638] synthesizing module 'lpf__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816]
    	Parameter C_EXT_RST_WIDTH bound to: 1 - type: integer 
    	Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer 
    	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
    	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
    INFO: [Synth 8-3491] module 'SRL16' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77684' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:868]
    INFO: [Synth 8-256] done synthesizing module 'lpf__parameterized0' (302#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816]
    INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset__parameterized2' (302#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323]
    INFO: [Synth 8-256] done synthesizing module 'system_sys_rgmii_rstgen_0' (303#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_rstgen_0/synth/system_sys_rgmii_rstgen_0.vhd:74]
    WARNING: [Synth 8-7023] instance 'sys_rgmii_rstgen' of module 'system_sys_rgmii_rstgen_0' has 10 connections declared, but only 6 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:4096]
    INFO: [Synth 8-638] synthesizing module 'system_sys_rstgen_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/synth/system_sys_rstgen_0.vhd:74]
    	Parameter C_FAMILY bound to: zynq - type: string 
    	Parameter C_EXT_RST_WIDTH bound to: 1 - type: integer 
    	Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer 
    	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
    	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
    	Parameter C_NUM_BUS_RST bound to: 1 - type: integer 
    	Parameter C_NUM_PERP_RST bound to: 1 - type: integer 
    	Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer 
    	Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer 
    INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1264' bound to instance 'U0' of component 'proc_sys_reset' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/synth/system_sys_rstgen_0.vhd:129]
    INFO: [Synth 8-256] done synthesizing module 'system_sys_rstgen_0' (304#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/synth/system_sys_rstgen_0.vhd:74]
    WARNING: [Synth 8-7023] instance 'sys_rstgen' of module 'system_sys_rstgen_0' has 10 connections declared, but only 7 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:4103]
    INFO: [Synth 8-6157] synthesizing module 'system_util_ad9361_adc_fifo_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/synth/system_util_ad9361_adc_fifo_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'util_wfifo' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/2c9a/util_wfifo.v:38]
    	Parameter NUM_OF_CHANNELS bound to: 4 - type: integer 
    	Parameter DIN_DATA_WIDTH bound to: 16 - type: integer 
    	Parameter DOUT_DATA_WIDTH bound to: 16 - type: integer 
    	Parameter DIN_ADDRESS_WIDTH bound to: 4 - type: integer 
    	Parameter M_MEM_RATIO bound to: 1 - type: integer 
    	Parameter ADDRESS_WIDTH bound to: 4 - type: integer 
    	Parameter DATA_WIDTH bound to: 64 - type: integer 
    	Parameter T_DIN_DATA_WIDTH bound to: 128 - type: integer 
    	Parameter T_DOUT_DATA_WIDTH bound to: 128 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'ad_mem__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_mem.v:38]
    	Parameter DATA_WIDTH bound to: 64 - type: integer 
    	Parameter ADDRESS_WIDTH bound to: 4 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_mem__parameterized1' (304#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/ad_mem.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'util_wfifo' (305#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/2c9a/util_wfifo.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'system_util_ad9361_adc_fifo_0' (306#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/synth/system_util_ad9361_adc_fifo_0.v:57]
    WARNING: [Synth 8-7023] instance 'util_ad9361_adc_fifo' of module 'system_util_ad9361_adc_fifo_0' has 30 connections declared, but only 27 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:4111]
    INFO: [Synth 8-6157] synthesizing module 'system_util_ad9361_adc_pack_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_pack_0/synth/system_util_ad9361_adc_pack_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'util_cpack2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/69a1/util_cpack2.v:38]
    	Parameter NUM_OF_CHANNELS bound to: 4 - type: integer 
    	Parameter SAMPLES_PER_CHANNEL bound to: 1 - type: integer 
    	Parameter SAMPLE_DATA_WIDTH bound to: 16 - type: integer 
    	Parameter CHANNEL_DATA_WIDTH bound to: 16 - type: integer 
    	Parameter REAL_NUM_OF_CHANNELS bound to: 4 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'util_cpack2_impl' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/69a1/util_cpack2_impl.v:38]
    	Parameter NUM_OF_CHANNELS bound to: 4 - type: integer 
    	Parameter SAMPLES_PER_CHANNEL bound to: 1 - type: integer 
    	Parameter SAMPLE_DATA_WIDTH bound to: 16 - type: integer 
    	Parameter TOTAL_DATA_WIDTH bound to: 64 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'ad_perfect_shuffle' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/common/ad_perfect_shuffle.v:26]
    	Parameter NUM_GROUPS bound to: 4 - type: integer 
    	Parameter WORDS_PER_GROUP bound to: 1 - type: integer 
    	Parameter WORD_WIDTH bound to: 16 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_perfect_shuffle' (307#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/common/ad_perfect_shuffle.v:26]
    INFO: [Synth 8-6157] synthesizing module 'pack_shell' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_shell.v:38]
    	Parameter NUM_OF_CHANNELS bound to: 4 - type: integer 
    	Parameter SAMPLES_PER_CHANNEL bound to: 1 - type: integer 
    	Parameter SAMPLE_DATA_WIDTH bound to: 16 - type: integer 
    	Parameter PACK bound to: 1 - type: integer 
    	Parameter NON_POWER_OF_TWO bound to: 1'b1 
    	Parameter CHANNEL_DATA_WIDTH bound to: 16 - type: integer 
    	Parameter TOTAL_DATA_WIDTH bound to: 64 - type: integer 
    	Parameter NUM_OF_SAMPLES bound to: 4 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'pack_network' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_network.v:38]
    	Parameter PORT_ADDRESS_WIDTH bound to: 2 - type: integer 
    	Parameter MUX_ORDER bound to: 2 - type: integer 
    	Parameter MIN_STAGE bound to: 0 - type: integer 
    	Parameter NUM_STAGES bound to: 1 - type: integer 
    	Parameter PACK bound to: 1 - type: integer 
    	Parameter PORT_DATA_WIDTH bound to: 16 - type: integer 
    	Parameter CTRL_WIDTH bound to: 8 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'pack_ctrl' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_ctrl.v:38]
    	Parameter PORT_ADDRESS_WIDTH bound to: 2 - type: integer 
    	Parameter MUX_ORDER bound to: 2 - type: integer 
    	Parameter MIN_STAGE bound to: 0 - type: integer 
    	Parameter NUM_STAGES bound to: 1 - type: integer 
    	Parameter PACK bound to: 1 - type: integer 
    	Parameter NUM_OF_PORTS bound to: 4 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'pack_ctrl' (308#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_ctrl.v:38]
    INFO: [Synth 8-6157] synthesizing module 'pack_interconnect' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_interconnect.v:38]
    	Parameter PORT_DATA_WIDTH bound to: 16 - type: integer 
    	Parameter PORT_ADDRESS_WIDTH bound to: 2 - type: integer 
    	Parameter MUX_ORDER bound to: 2 - type: integer 
    	Parameter NUM_STAGES bound to: 1 - type: integer 
    	Parameter PACK bound to: 1 - type: integer 
    	Parameter NUM_PORTS bound to: 4 - type: integer 
    	Parameter TOTAL_DATA_WIDTH bound to: 64 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'ad_perfect_shuffle__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/common/ad_perfect_shuffle.v:26]
    	Parameter NUM_GROUPS bound to: 1 - type: integer 
    	Parameter WORDS_PER_GROUP bound to: 4 - type: integer 
    	Parameter WORD_WIDTH bound to: 16 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_perfect_shuffle__parameterized0' (308#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/common/ad_perfect_shuffle.v:26]
    INFO: [Synth 8-6155] done synthesizing module 'pack_interconnect' (309#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_interconnect.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'pack_network' (310#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_network.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'pack_shell' (311#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_shell.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'util_cpack2_impl' (312#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/69a1/util_cpack2_impl.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'util_cpack2' (313#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/69a1/util_cpack2.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'system_util_ad9361_adc_pack_0' (314#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_pack_0/synth/system_util_ad9361_adc_pack_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'system_util_ad9361_dac_upack_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_dac_upack_0/synth/system_util_ad9361_dac_upack_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'util_upack2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d463/util_upack2.v:38]
    	Parameter NUM_OF_CHANNELS bound to: 4 - type: integer 
    	Parameter SAMPLES_PER_CHANNEL bound to: 1 - type: integer 
    	Parameter SAMPLE_DATA_WIDTH bound to: 16 - type: integer 
    	Parameter CHANNEL_DATA_WIDTH bound to: 16 - type: integer 
    	Parameter REAL_NUM_OF_CHANNELS bound to: 4 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'util_upack2_impl' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d463/util_upack2_impl.v:38]
    	Parameter NUM_OF_CHANNELS bound to: 4 - type: integer 
    	Parameter SAMPLES_PER_CHANNEL bound to: 1 - type: integer 
    	Parameter SAMPLE_DATA_WIDTH bound to: 16 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'pack_shell__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_shell.v:38]
    	Parameter NUM_OF_CHANNELS bound to: 4 - type: integer 
    	Parameter SAMPLES_PER_CHANNEL bound to: 1 - type: integer 
    	Parameter SAMPLE_DATA_WIDTH bound to: 16 - type: integer 
    	Parameter PACK bound to: 0 - type: integer 
    	Parameter NON_POWER_OF_TWO bound to: 1'b1 
    	Parameter CHANNEL_DATA_WIDTH bound to: 16 - type: integer 
    	Parameter TOTAL_DATA_WIDTH bound to: 64 - type: integer 
    	Parameter NUM_OF_SAMPLES bound to: 4 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'pack_network__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_network.v:38]
    	Parameter PORT_ADDRESS_WIDTH bound to: 3 - type: integer 
    	Parameter MUX_ORDER bound to: 2 - type: integer 
    	Parameter MIN_STAGE bound to: 0 - type: integer 
    	Parameter NUM_STAGES bound to: 1 - type: integer 
    	Parameter PACK bound to: 0 - type: integer 
    	Parameter PORT_DATA_WIDTH bound to: 16 - type: integer 
    	Parameter CTRL_WIDTH bound to: 16 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'pack_ctrl__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_ctrl.v:38]
    	Parameter PORT_ADDRESS_WIDTH bound to: 3 - type: integer 
    	Parameter MUX_ORDER bound to: 2 - type: integer 
    	Parameter MIN_STAGE bound to: 0 - type: integer 
    	Parameter NUM_STAGES bound to: 1 - type: integer 
    	Parameter PACK bound to: 0 - type: integer 
    	Parameter NUM_OF_PORTS bound to: 8 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'pack_ctrl__parameterized0' (314#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_ctrl.v:38]
    INFO: [Synth 8-6157] synthesizing module 'pack_interconnect__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_interconnect.v:38]
    	Parameter PORT_DATA_WIDTH bound to: 16 - type: integer 
    	Parameter PORT_ADDRESS_WIDTH bound to: 3 - type: integer 
    	Parameter MUX_ORDER bound to: 2 - type: integer 
    	Parameter NUM_STAGES bound to: 1 - type: integer 
    	Parameter PACK bound to: 0 - type: integer 
    	Parameter NUM_PORTS bound to: 8 - type: integer 
    	Parameter TOTAL_DATA_WIDTH bound to: 128 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'ad_perfect_shuffle__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/common/ad_perfect_shuffle.v:26]
    	Parameter NUM_GROUPS bound to: 4 - type: integer 
    	Parameter WORDS_PER_GROUP bound to: 2 - type: integer 
    	Parameter WORD_WIDTH bound to: 16 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_perfect_shuffle__parameterized1' (314#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/common/ad_perfect_shuffle.v:26]
    INFO: [Synth 8-6155] done synthesizing module 'pack_interconnect__parameterized0' (314#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_interconnect.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'pack_network__parameterized0' (314#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_network.v:38]
    INFO: [Synth 8-6157] synthesizing module 'ad_perfect_shuffle__parameterized2' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/common/ad_perfect_shuffle.v:26]
    	Parameter NUM_GROUPS bound to: 2 - type: integer 
    	Parameter WORDS_PER_GROUP bound to: 2 - type: integer 
    	Parameter WORD_WIDTH bound to: 32 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_perfect_shuffle__parameterized2' (314#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/common/ad_perfect_shuffle.v:26]
    INFO: [Synth 8-6157] synthesizing module 'pack_network__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_network.v:38]
    	Parameter PORT_ADDRESS_WIDTH bound to: 2 - type: integer 
    	Parameter MUX_ORDER bound to: 1 - type: integer 
    	Parameter MIN_STAGE bound to: 1 - type: integer 
    	Parameter NUM_STAGES bound to: 1 - type: integer 
    	Parameter PACK bound to: 0 - type: integer 
    	Parameter PORT_DATA_WIDTH bound to: 16 - type: integer 
    	Parameter CTRL_WIDTH bound to: 4 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'pack_ctrl__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_ctrl.v:38]
    	Parameter PORT_ADDRESS_WIDTH bound to: 2 - type: integer 
    	Parameter MUX_ORDER bound to: 1 - type: integer 
    	Parameter MIN_STAGE bound to: 1 - type: integer 
    	Parameter NUM_STAGES bound to: 1 - type: integer 
    	Parameter PACK bound to: 0 - type: integer 
    	Parameter NUM_OF_PORTS bound to: 4 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'pack_ctrl__parameterized1' (314#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_ctrl.v:38]
    INFO: [Synth 8-6157] synthesizing module 'pack_interconnect__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_interconnect.v:38]
    	Parameter PORT_DATA_WIDTH bound to: 16 - type: integer 
    	Parameter PORT_ADDRESS_WIDTH bound to: 2 - type: integer 
    	Parameter MUX_ORDER bound to: 1 - type: integer 
    	Parameter NUM_STAGES bound to: 1 - type: integer 
    	Parameter PACK bound to: 0 - type: integer 
    	Parameter NUM_PORTS bound to: 4 - type: integer 
    	Parameter TOTAL_DATA_WIDTH bound to: 64 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'ad_perfect_shuffle__parameterized3' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/common/ad_perfect_shuffle.v:26]
    	Parameter NUM_GROUPS bound to: 2 - type: integer 
    	Parameter WORDS_PER_GROUP bound to: 2 - type: integer 
    	Parameter WORD_WIDTH bound to: 16 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'ad_perfect_shuffle__parameterized3' (314#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/common/ad_perfect_shuffle.v:26]
    INFO: [Synth 8-6155] done synthesizing module 'pack_interconnect__parameterized1' (314#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_interconnect.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'pack_network__parameterized1' (314#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_network.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'pack_shell__parameterized0' (314#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/util_pack_common/pack_shell.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'util_upack2_impl' (315#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d463/util_upack2_impl.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'util_upack2' (316#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/d463/util_upack2.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'system_util_ad9361_dac_upack_0' (317#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_dac_upack_0/synth/system_util_ad9361_dac_upack_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'system_util_ad9361_divclk_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_0/synth/system_util_ad9361_divclk_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'util_clkdiv' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/2712/util_clkdiv.v:38]
    	Parameter SIM_DEVICE bound to: 7SERIES - type: string 
    	Parameter SEL_0_DIV bound to: 4 - type: string 
    	Parameter SEL_1_DIV bound to: 2 - type: string 
    INFO: [Synth 8-6157] synthesizing module 'BUFR' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1402]
    	Parameter BUFR_DIVIDE bound to: 4 - type: string 
    	Parameter SIM_DEVICE bound to: 7SERIES - type: string 
    INFO: [Synth 8-6155] done synthesizing module 'BUFR' (318#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1402]
    INFO: [Synth 8-6157] synthesizing module 'BUFR__parameterized0' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1402]
    	Parameter BUFR_DIVIDE bound to: 2 - type: string 
    	Parameter SIM_DEVICE bound to: 7SERIES - type: string 
    INFO: [Synth 8-6155] done synthesizing module 'BUFR__parameterized0' (318#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1402]
    INFO: [Synth 8-6157] synthesizing module 'BUFGMUX_CTRL' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1203]
    INFO: [Synth 8-6155] done synthesizing module 'BUFGMUX_CTRL' (319#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1203]
    INFO: [Synth 8-6155] done synthesizing module 'util_clkdiv' (320#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/2712/util_clkdiv.v:38]
    INFO: [Synth 8-6155] done synthesizing module 'system_util_ad9361_divclk_0' (321#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_0/synth/system_util_ad9361_divclk_0.v:57]
    INFO: [Synth 8-638] synthesizing module 'system_util_ad9361_divclk_reset_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_reset_0/synth/system_util_ad9361_divclk_reset_0.vhd:74]
    	Parameter C_FAMILY bound to: zynq - type: string 
    	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
    	Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer 
    	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
    	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
    	Parameter C_NUM_BUS_RST bound to: 1 - type: integer 
    	Parameter C_NUM_PERP_RST bound to: 1 - type: integer 
    	Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer 
    	Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer 
    INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1264' bound to instance 'U0' of component 'proc_sys_reset' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_reset_0/synth/system_util_ad9361_divclk_reset_0.vhd:129]
    INFO: [Synth 8-638] synthesizing module 'proc_sys_reset__parameterized4' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323]
    	Parameter C_FAMILY bound to: zynq - type: string 
    	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
    	Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer 
    	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
    	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
    	Parameter C_NUM_BUS_RST bound to: 1 - type: integer 
    	Parameter C_NUM_PERP_RST bound to: 1 - type: integer 
    	Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer 
    	Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer 
    	Parameter INIT bound to: 1'b1 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1392]
    	Parameter INIT bound to: 1'b1 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1408]
    	Parameter INIT bound to: 1'b0 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1434]
    	Parameter INIT bound to: 1'b1 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1457]
    	Parameter INIT bound to: 1'b0 
    	Parameter IS_C_INVERTED bound to: 1'b0 
    	Parameter IS_D_INVERTED bound to: 1'b0 
    	Parameter IS_R_INVERTED bound to: 1'b0 
    INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1481]
    INFO: [Synth 8-638] synthesizing module 'lpf__parameterized1' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816]
    	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
    	Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer 
    	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
    	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
    INFO: [Synth 8-3491] module 'SRL16' declared at '/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77684' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:868]
    INFO: [Synth 8-256] done synthesizing module 'lpf__parameterized1' (321#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816]
    INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset__parameterized4' (321#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323]
    INFO: [Synth 8-256] done synthesizing module 'system_util_ad9361_divclk_reset_0' (322#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_reset_0/synth/system_util_ad9361_divclk_reset_0.vhd:74]
    WARNING: [Synth 8-7023] instance 'util_ad9361_divclk_reset' of module 'system_util_ad9361_divclk_reset_0' has 10 connections declared, but only 7 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:4177]
    INFO: [Synth 8-6157] synthesizing module 'system_util_ad9361_divclk_sel_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_sel_0/synth/system_util_ad9361_divclk_sel_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'util_reduced_logic_v2_0_4_util_reduced_logic' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4c94/hdl/util_reduced_logic_v2_0_vl_rfs.v:73]
    	Parameter C_OPERATION bound to: and - type: string 
    	Parameter C_SIZE bound to: 2 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'util_reduced_logic_v2_0_4_util_reduced_logic' (323#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4c94/hdl/util_reduced_logic_v2_0_vl_rfs.v:73]
    INFO: [Synth 8-6155] done synthesizing module 'system_util_ad9361_divclk_sel_0' (324#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_sel_0/synth/system_util_ad9361_divclk_sel_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'system_util_ad9361_divclk_sel_concat_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_sel_concat_0/synth/system_util_ad9361_divclk_sel_concat_0.v:58]
    INFO: [Synth 8-6157] synthesizing module 'xlconcat_v2_1_3_xlconcat__parameterized0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/442e/hdl/xlconcat_v2_1_vl_rfs.v:14]
    	Parameter IN0_WIDTH bound to: 1 - type: integer 
    	Parameter IN1_WIDTH bound to: 1 - type: integer 
    	Parameter IN2_WIDTH bound to: 1 - type: integer 
    	Parameter IN3_WIDTH bound to: 1 - type: integer 
    	Parameter IN4_WIDTH bound to: 1 - type: integer 
    	Parameter IN5_WIDTH bound to: 1 - type: integer 
    	Parameter IN6_WIDTH bound to: 1 - type: integer 
    	Parameter IN7_WIDTH bound to: 1 - type: integer 
    	Parameter IN8_WIDTH bound to: 1 - type: integer 
    	Parameter IN9_WIDTH bound to: 1 - type: integer 
    	Parameter IN10_WIDTH bound to: 1 - type: integer 
    	Parameter IN11_WIDTH bound to: 1 - type: integer 
    	Parameter IN12_WIDTH bound to: 1 - type: integer 
    	Parameter IN13_WIDTH bound to: 1 - type: integer 
    	Parameter IN14_WIDTH bound to: 1 - type: integer 
    	Parameter IN15_WIDTH bound to: 1 - type: integer 
    	Parameter IN16_WIDTH bound to: 1 - type: integer 
    	Parameter IN17_WIDTH bound to: 1 - type: integer 
    	Parameter IN18_WIDTH bound to: 1 - type: integer 
    	Parameter IN19_WIDTH bound to: 1 - type: integer 
    	Parameter IN20_WIDTH bound to: 1 - type: integer 
    	Parameter IN21_WIDTH bound to: 1 - type: integer 
    	Parameter IN22_WIDTH bound to: 1 - type: integer 
    	Parameter IN23_WIDTH bound to: 1 - type: integer 
    	Parameter IN24_WIDTH bound to: 1 - type: integer 
    	Parameter IN25_WIDTH bound to: 1 - type: integer 
    	Parameter IN26_WIDTH bound to: 1 - type: integer 
    	Parameter IN27_WIDTH bound to: 1 - type: integer 
    	Parameter IN28_WIDTH bound to: 1 - type: integer 
    	Parameter IN29_WIDTH bound to: 1 - type: integer 
    	Parameter IN30_WIDTH bound to: 1 - type: integer 
    	Parameter IN31_WIDTH bound to: 1 - type: integer 
    	Parameter dout_width bound to: 2 - type: integer 
    	Parameter NUM_PORTS bound to: 2 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'xlconcat_v2_1_3_xlconcat__parameterized0' (324#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/442e/hdl/xlconcat_v2_1_vl_rfs.v:14]
    INFO: [Synth 8-6155] done synthesizing module 'system_util_ad9361_divclk_sel_concat_0' (325#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_sel_concat_0/synth/system_util_ad9361_divclk_sel_concat_0.v:58]
    INFO: [Synth 8-6157] synthesizing module 'system_util_ad9361_tdd_sync_0' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_tdd_sync_0/synth/system_util_ad9361_tdd_sync_0.v:57]
    INFO: [Synth 8-6157] synthesizing module 'util_tdd_sync' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4c54/util_tdd_sync.v:44]
    	Parameter TDD_SYNC_PERIOD bound to: 10000000 - type: integer 
    INFO: [Synth 8-6157] synthesizing module 'util_pulse_gen' [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/util_pulse_gen.v:37]
    	Parameter PULSE_WIDTH bound to: 7 - type: integer 
    	Parameter PULSE_PERIOD bound to: 10000000 - type: integer 
    INFO: [Synth 8-6155] done synthesizing module 'util_pulse_gen' (326#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/common/util_pulse_gen.v:37]
    WARNING: [Synth 8-7023] instance 'i_tdd_sync' of module 'util_pulse_gen' has 7 connections declared, but only 6 given [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4c54/util_tdd_sync.v:67]
    INFO: [Synth 8-6155] done synthesizing module 'util_tdd_sync' (327#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ipshared/4c54/util_tdd_sync.v:44]
    INFO: [Synth 8-6155] done synthesizing module 'system_util_ad9361_tdd_sync_0' (328#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_tdd_sync_0/synth/system_util_ad9361_tdd_sync_0.v:57]
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'system' (329#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/synth/system.v:2056]
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'system_wrapper' (330#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/imports/hdl/system_wrapper.v:12]
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg 
    INFO: [Synth 8-6155] done synthesizing module 'system_top' (331#1) [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/system_top.v:38]
    WARNING: [Synth 8-3917] design system_top has port hdmi_pd driven by constant 0
    WARNING: [Synth 8-3917] design system_top has port fan_pwm driven by constant 1
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In2[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In3[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In4[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In5[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In6[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In7[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In8[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In9[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In10[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In11[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In12[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In13[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In14[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In15[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In16[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In17[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In18[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In19[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In20[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In21[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In22[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In23[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In24[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In25[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In26[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In27[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In28[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In29[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In30[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat__parameterized0 has unconnected port In31[0]
    INFO: [Synth 8-3331] design cdc_sync has unconnected port prmry_aclk
    INFO: [Synth 8-3331] design cdc_sync has unconnected port prmry_resetn
    INFO: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[1]
    INFO: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[0]
    INFO: [Synth 8-3331] design cdc_sync has unconnected port scndry_resetn
    INFO: [Synth 8-3331] design pack_ctrl__parameterized1 has unconnected port rotate[1]
    INFO: [Synth 8-3331] design pack_ctrl__parameterized1 has unconnected port prefix_count[7]
    INFO: [Synth 8-3331] design pack_ctrl__parameterized1 has unconnected port prefix_count[5]
    INFO: [Synth 8-3331] design pack_ctrl__parameterized1 has unconnected port prefix_count[4]
    INFO: [Synth 8-3331] design pack_ctrl__parameterized1 has unconnected port prefix_count[3]
    INFO: [Synth 8-3331] design pack_ctrl__parameterized1 has unconnected port prefix_count[1]
    INFO: [Synth 8-3331] design pack_ctrl__parameterized1 has unconnected port prefix_count[0]
    INFO: [Synth 8-3331] design pack_ctrl__parameterized0 has unconnected port prefix_count[23]
    INFO: [Synth 8-3331] design pack_ctrl__parameterized0 has unconnected port prefix_count[22]
    INFO: [Synth 8-3331] design pack_ctrl__parameterized0 has unconnected port prefix_count[21]
    INFO: [Synth 8-3331] design pack_ctrl__parameterized0 has unconnected port prefix_count[17]
    INFO: [Synth 8-3331] design pack_ctrl__parameterized0 has unconnected port prefix_count[16]
    INFO: [Synth 8-3331] design pack_ctrl__parameterized0 has unconnected port prefix_count[15]
    INFO: [Synth 8-3331] design pack_ctrl__parameterized0 has unconnected port prefix_count[11]
    INFO: [Synth 8-3331] design pack_ctrl__parameterized0 has unconnected port prefix_count[10]
    INFO: [Synth 8-3331] design pack_ctrl__parameterized0 has unconnected port prefix_count[9]
    INFO: [Synth 8-3331] design pack_ctrl__parameterized0 has unconnected port prefix_count[5]
    INFO: [Synth 8-3331] design pack_ctrl__parameterized0 has unconnected port prefix_count[4]
    INFO: [Synth 8-3331] design pack_ctrl__parameterized0 has unconnected port prefix_count[3]
    INFO: [Synth 8-3331] design util_upack2_impl has unconnected port fifo_rd_en[3]
    INFO: [Synth 8-3331] design util_upack2_impl has unconnected port fifo_rd_en[2]
    INFO: [Synth 8-3331] design util_upack2_impl has unconnected port fifo_rd_en[1]
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_4
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_5
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_6
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_7
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_8
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_9
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_10
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_11
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_12
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_13
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_14
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_15
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_16
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_17
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_18
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_19
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_20
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_21
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_22
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_23
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_24
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_25
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_26
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_27
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_28
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_29
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_30
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_31
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_32
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_33
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_34
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_35
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_36
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_37
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_38
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_39
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_40
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_41
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_42
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_43
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_44
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_45
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_46
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_47
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_48
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_49
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_50
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_51
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_52
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_53
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_54
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_55
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_56
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_57
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_58
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_59
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_60
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_61
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_62
    INFO: [Synth 8-3331] design util_upack2 has unconnected port enable_63
    INFO: [Synth 8-3331] design util_cpack2_impl has unconnected port fifo_wr_en[3]
    INFO: [Synth 8-3331] design util_cpack2_impl has unconnected port fifo_wr_en[2]
    INFO: [Synth 8-3331] design util_cpack2_impl has unconnected port fifo_wr_en[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_4
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_5
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_6
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_7
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_8
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_9
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_10
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_11
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_12
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_13
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_14
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_15
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_16
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_17
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_18
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_19
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_20
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_21
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_22
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_23
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_24
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_25
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_26
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_27
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_28
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_29
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_30
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_31
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_32
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_33
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_34
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_35
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_36
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_37
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_38
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_39
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_40
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_41
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_42
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_43
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_44
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_45
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_46
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_47
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_48
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_49
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_50
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_51
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_52
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_53
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_54
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_55
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_56
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_57
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_58
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_59
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_60
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_61
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_62
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port enable_63
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_4[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_4[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_4[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_4[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_4[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_4[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_4[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_4[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_4[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_4[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_4[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_4[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_4[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_4[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_4[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_4[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_5[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_5[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_5[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_5[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_5[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_5[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_5[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_5[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_5[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_5[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_5[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_5[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_5[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_5[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_5[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_5[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_6[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_6[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_6[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_6[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_6[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_6[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_6[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_6[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_6[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_6[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_6[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_6[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_6[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_6[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_6[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_6[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_7[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_7[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_7[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_7[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_7[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_7[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_7[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_7[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_7[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_7[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_7[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_7[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_7[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_7[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_7[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_7[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_8[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_8[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_8[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_8[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_8[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_8[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_8[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_8[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_8[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_8[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_8[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_8[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_8[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_8[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_8[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_8[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_9[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_9[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_9[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_9[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_9[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_9[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_9[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_9[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_9[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_9[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_9[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_9[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_9[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_9[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_9[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_9[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_10[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_10[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_10[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_10[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_10[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_10[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_10[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_10[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_10[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_10[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_10[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_10[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_10[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_10[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_10[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_10[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_11[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_11[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_11[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_11[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_11[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_11[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_11[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_11[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_11[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_11[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_11[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_11[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_11[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_11[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_11[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_11[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_12[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_12[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_12[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_12[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_12[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_12[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_12[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_12[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_12[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_12[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_12[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_12[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_12[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_12[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_12[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_12[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_13[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_13[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_13[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_13[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_13[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_13[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_13[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_13[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_13[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_13[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_13[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_13[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_13[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_13[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_13[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_13[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_14[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_14[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_14[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_14[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_14[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_14[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_14[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_14[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_14[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_14[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_14[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_14[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_14[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_14[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_14[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_14[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_15[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_15[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_15[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_15[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_15[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_15[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_15[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_15[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_15[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_15[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_15[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_15[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_15[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_15[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_15[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_15[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_16[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_16[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_16[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_16[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_16[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_16[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_16[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_16[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_16[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_16[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_16[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_16[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_16[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_16[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_16[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_16[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_17[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_17[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_17[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_17[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_17[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_17[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_17[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_17[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_17[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_17[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_17[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_17[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_17[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_17[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_17[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_17[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_18[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_18[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_18[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_18[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_18[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_18[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_18[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_18[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_18[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_18[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_18[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_18[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_18[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_18[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_18[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_18[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_19[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_19[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_19[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_19[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_19[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_19[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_19[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_19[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_19[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_19[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_19[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_19[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_19[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_19[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_19[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_19[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_20[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_20[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_20[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_20[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_20[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_20[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_20[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_20[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_20[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_20[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_20[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_20[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_20[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_20[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_20[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_20[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_21[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_21[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_21[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_21[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_21[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_21[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_21[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_21[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_21[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_21[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_21[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_21[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_21[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_21[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_21[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_21[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_22[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_22[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_22[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_22[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_22[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_22[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_22[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_22[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_22[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_22[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_22[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_22[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_22[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_22[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_22[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_22[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_23[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_23[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_23[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_23[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_23[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_23[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_23[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_23[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_23[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_23[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_23[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_23[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_23[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_23[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_23[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_23[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_24[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_24[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_24[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_24[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_24[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_24[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_24[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_24[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_24[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_24[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_24[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_24[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_24[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_24[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_24[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_24[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_25[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_25[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_25[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_25[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_25[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_25[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_25[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_25[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_25[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_25[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_25[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_25[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_25[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_25[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_25[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_25[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_26[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_26[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_26[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_26[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_26[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_26[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_26[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_26[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_26[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_26[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_26[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_26[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_26[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_26[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_26[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_26[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_27[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_27[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_27[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_27[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_27[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_27[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_27[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_27[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_27[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_27[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_27[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_27[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_27[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_27[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_27[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_27[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_28[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_28[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_28[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_28[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_28[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_28[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_28[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_28[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_28[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_28[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_28[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_28[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_28[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_28[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_28[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_28[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_29[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_29[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_29[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_29[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_29[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_29[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_29[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_29[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_29[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_29[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_29[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_29[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_29[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_29[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_29[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_29[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_30[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_30[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_30[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_30[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_30[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_30[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_30[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_30[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_30[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_30[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_30[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_30[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_30[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_30[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_30[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_30[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_31[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_31[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_31[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_31[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_31[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_31[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_31[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_31[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_31[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_31[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_31[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_31[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_31[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_31[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_31[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_31[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_32[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_32[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_32[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_32[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_32[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_32[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_32[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_32[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_32[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_32[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_32[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_32[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_32[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_32[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_32[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_32[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_33[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_33[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_33[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_33[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_33[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_33[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_33[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_33[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_33[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_33[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_33[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_33[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_33[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_33[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_33[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_33[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_34[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_34[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_34[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_34[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_34[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_34[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_34[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_34[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_34[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_34[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_34[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_34[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_34[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_34[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_34[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_34[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_35[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_35[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_35[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_35[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_35[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_35[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_35[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_35[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_35[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_35[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_35[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_35[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_35[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_35[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_35[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_35[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_36[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_36[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_36[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_36[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_36[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_36[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_36[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_36[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_36[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_36[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_36[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_36[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_36[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_36[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_36[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_36[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_37[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_37[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_37[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_37[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_37[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_37[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_37[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_37[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_37[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_37[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_37[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_37[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_37[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_37[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_37[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_37[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_38[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_38[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_38[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_38[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_38[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_38[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_38[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_38[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_38[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_38[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_38[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_38[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_38[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_38[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_38[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_38[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_39[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_39[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_39[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_39[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_39[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_39[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_39[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_39[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_39[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_39[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_39[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_39[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_39[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_39[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_39[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_39[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_40[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_40[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_40[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_40[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_40[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_40[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_40[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_40[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_40[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_40[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_40[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_40[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_40[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_40[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_40[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_40[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_41[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_41[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_41[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_41[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_41[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_41[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_41[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_41[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_41[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_41[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_41[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_41[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_41[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_41[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_41[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_41[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_42[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_42[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_42[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_42[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_42[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_42[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_42[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_42[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_42[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_42[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_42[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_42[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_42[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_42[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_42[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_42[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_43[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_43[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_43[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_43[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_43[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_43[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_43[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_43[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_43[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_43[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_43[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_43[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_43[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_43[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_43[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_43[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_44[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_44[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_44[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_44[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_44[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_44[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_44[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_44[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_44[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_44[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_44[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_44[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_44[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_44[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_44[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_44[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_45[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_45[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_45[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_45[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_45[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_45[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_45[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_45[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_45[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_45[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_45[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_45[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_45[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_45[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_45[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_45[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_46[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_46[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_46[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_46[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_46[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_46[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_46[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_46[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_46[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_46[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_46[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_46[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_46[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_46[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_46[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_46[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_47[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_47[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_47[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_47[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_47[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_47[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_47[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_47[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_47[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_47[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_47[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_47[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_47[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_47[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_47[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_47[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_48[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_48[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_48[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_48[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_48[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_48[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_48[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_48[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_48[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_48[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_48[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_48[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_48[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_48[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_48[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_48[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_49[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_49[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_49[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_49[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_49[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_49[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_49[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_49[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_49[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_49[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_49[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_49[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_49[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_49[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_49[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_49[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_50[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_50[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_50[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_50[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_50[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_50[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_50[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_50[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_50[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_50[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_50[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_50[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_50[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_50[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_50[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_50[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_51[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_51[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_51[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_51[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_51[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_51[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_51[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_51[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_51[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_51[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_51[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_51[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_51[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_51[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_51[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_51[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_52[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_52[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_52[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_52[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_52[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_52[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_52[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_52[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_52[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_52[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_52[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_52[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_52[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_52[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_52[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_52[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_53[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_53[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_53[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_53[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_53[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_53[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_53[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_53[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_53[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_53[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_53[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_53[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_53[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_53[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_53[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_53[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_54[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_54[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_54[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_54[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_54[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_54[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_54[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_54[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_54[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_54[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_54[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_54[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_54[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_54[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_54[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_54[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_55[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_55[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_55[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_55[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_55[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_55[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_55[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_55[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_55[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_55[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_55[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_55[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_55[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_55[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_55[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_55[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_56[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_56[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_56[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_56[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_56[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_56[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_56[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_56[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_56[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_56[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_56[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_56[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_56[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_56[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_56[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_56[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_57[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_57[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_57[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_57[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_57[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_57[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_57[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_57[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_57[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_57[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_57[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_57[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_57[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_57[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_57[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_57[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_58[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_58[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_58[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_58[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_58[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_58[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_58[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_58[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_58[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_58[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_58[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_58[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_58[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_58[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_58[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_58[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_59[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_59[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_59[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_59[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_59[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_59[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_59[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_59[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_59[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_59[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_59[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_59[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_59[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_59[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_59[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_59[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_60[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_60[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_60[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_60[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_60[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_60[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_60[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_60[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_60[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_60[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_60[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_60[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_60[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_60[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_60[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_60[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_61[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_61[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_61[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_61[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_61[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_61[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_61[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_61[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_61[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_61[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_61[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_61[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_61[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_61[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_61[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_61[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_62[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_62[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_62[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_62[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_62[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_62[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_62[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_62[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_62[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_62[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_62[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_62[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_62[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_62[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_62[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_62[0]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_63[15]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_63[14]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_63[13]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_63[12]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_63[11]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_63[10]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_63[9]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_63[8]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_63[7]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_63[6]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_63[5]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_63[4]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_63[3]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_63[2]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_63[1]
    INFO: [Synth 8-3331] design util_cpack2 has unconnected port fifo_wr_data_63[0]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_valid_4
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_4[15]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_4[14]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_4[13]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_4[12]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_4[11]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_4[10]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_4[9]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_4[8]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_4[7]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_4[6]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_4[5]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_4[4]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_4[3]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_4[2]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_4[1]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_4[0]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_valid_5
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_5[15]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_5[14]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_5[13]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_5[12]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_5[11]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_5[10]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_5[9]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_5[8]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_5[7]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_5[6]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_5[5]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_5[4]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_5[3]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_5[2]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_5[1]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_5[0]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_valid_6
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_6[15]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_6[14]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_6[13]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_6[12]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_6[11]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_6[10]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_6[9]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_6[8]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_6[7]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_6[6]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_6[5]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_6[4]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_6[3]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_6[2]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_6[1]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_6[0]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_valid_7
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_7[15]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_7[14]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_7[13]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_7[12]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_7[11]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_7[10]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_7[9]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_7[8]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_7[7]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_7[6]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_7[5]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_7[4]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_7[3]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_7[2]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_7[1]
    INFO: [Synth 8-3331] design util_wfifo has unconnected port din_data_7[0]
    INFO: [Synth 8-3331] design reset_sync has unconnected port enable
    INFO: [Synth 8-3331] design gmii_to_rgmii_core has unconnected port speed_selection[0]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_COL
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_CRS
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RX_DV
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RX_ER
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[7]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[6]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[5]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[4]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[3]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[2]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[1]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[0]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_GP0_ARSIZE[2]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_GP0_AWSIZE[2]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_GP1_ARSIZE[2]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_GP1_AWSIZE[2]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_ACP_ARSIZE[2]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_ACP_AWSIZE[2]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP0_ARSIZE[2]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP0_AWSIZE[2]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP1_ARSIZE[2]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP1_AWSIZE[2]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP2_ARSIZE[2]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP2_AWSIZE[2]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP3_ARSIZE[2]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP3_AWSIZE[2]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FCLK_CLKTRIG3_N
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FCLK_CLKTRIG2_N
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FCLK_CLKTRIG1_N
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FCLK_CLKTRIG0_N
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[31]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[30]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[29]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[28]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[27]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[26]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[25]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[24]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[23]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[22]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[21]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[20]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[19]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[18]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[17]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[16]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[15]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[14]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[13]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[12]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[11]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[10]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[9]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[8]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[7]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[6]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[5]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[4]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[3]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[2]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[1]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[0]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_VALID
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_ATID[3]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_ATID[2]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_ATID[1]
    INFO: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_ATID[0]
    INFO: [Synth 8-3331] design util_vector_logic_v2_0_1_util_vector_logic has unconnected port Op2[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat has unconnected port In16[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat has unconnected port In17[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat has unconnected port In18[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat has unconnected port In19[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat has unconnected port In20[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat has unconnected port In21[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat has unconnected port In22[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat has unconnected port In23[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat has unconnected port In24[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat has unconnected port In25[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat has unconnected port In26[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat has unconnected port In27[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat has unconnected port In28[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat has unconnected port In29[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat has unconnected port In30[0]
    INFO: [Synth 8-3331] design xlconcat_v2_1_3_xlconcat has unconnected port In31[0]
    INFO: [Synth 8-3331] design up_axi__parameterized2 has unconnected port up_axi_awaddr[1]
    INFO: [Synth 8-3331] design up_axi__parameterized2 has unconnected port up_axi_awaddr[0]
    INFO: [Synth 8-3331] design up_axi__parameterized2 has unconnected port up_axi_wstrb[3]
    INFO: [Synth 8-3331] design up_axi__parameterized2 has unconnected port up_axi_wstrb[2]
    INFO: [Synth 8-3331] design up_axi__parameterized2 has unconnected port up_axi_wstrb[1]
    INFO: [Synth 8-3331] design up_axi__parameterized2 has unconnected port up_axi_wstrb[0]
    INFO: [Synth 8-3331] design up_axi__parameterized2 has unconnected port up_axi_araddr[1]
    INFO: [Synth 8-3331] design up_axi__parameterized2 has unconnected port up_axi_araddr[0]
    INFO: [Synth 8-3331] design axi_sysid has unconnected port s_axi_awaddr[15]
    INFO: [Synth 8-3331] design axi_sysid has unconnected port s_axi_awaddr[14]
    INFO: [Synth 8-3331] design axi_sysid has unconnected port s_axi_awaddr[13]
    INFO: [Synth 8-3331] design axi_sysid has unconnected port s_axi_awprot[2]
    INFO: [Synth 8-3331] design axi_sysid has unconnected port s_axi_awprot[1]
    INFO: [Synth 8-3331] design axi_sysid has unconnected port s_axi_awprot[0]
    INFO: [Synth 8-3331] design axi_sysid has unconnected port s_axi_araddr[15]
    INFO: [Synth 8-3331] design axi_sysid has unconnected port s_axi_araddr[14]
    INFO: [Synth 8-3331] design axi_sysid has unconnected port s_axi_araddr[13]
    INFO: [Synth 8-3331] design axi_sysid has unconnected port s_axi_arprot[2]
    INFO: [Synth 8-3331] design axi_sysid has unconnected port s_axi_arprot[1]
    INFO: [Synth 8-3331] design axi_sysid has unconnected port s_axi_arprot[0]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_awaddr[15]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_awaddr[14]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_awaddr[13]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_awaddr[12]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_awaddr[11]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_awaddr[10]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_awaddr[9]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_awaddr[8]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_awaddr[7]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_awaddr[6]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_awaddr[5]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_awaddr[4]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_awaddr[1]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_awaddr[0]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_wstrb[3]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_wstrb[2]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_wstrb[1]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_wstrb[0]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_araddr[15]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_araddr[14]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_araddr[13]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_araddr[12]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_araddr[11]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_araddr[10]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_araddr[9]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_araddr[8]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_araddr[7]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_araddr[6]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_araddr[5]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_araddr[4]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_araddr[1]
    INFO: [Synth 8-3331] design axi_ctrlif__parameterized0 has unconnected port s_axi_araddr[0]
    INFO: [Synth 8-3331] design tx_encoder has unconnected port conf_mode[3]
    INFO: [Synth 8-3331] design tx_encoder has unconnected port conf_mode[2]
    INFO: [Synth 8-3331] design tx_encoder has unconnected port conf_mode[1]
    INFO: [Synth 8-3331] design tx_encoder has unconnected port conf_mode[0]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axi_awprot[2]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axi_awprot[1]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axi_awprot[0]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axi_arprot[2]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axi_arprot[1]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axi_arprot[0]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_aclk
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_aresetn
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[31]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[30]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[29]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[28]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[27]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[26]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[25]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[24]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[23]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[22]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[21]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[20]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[19]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[18]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[17]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[16]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[15]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[14]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[13]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[12]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[11]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[10]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[9]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[8]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[7]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[6]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[5]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[4]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[3]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[2]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[1]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tdata[0]
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tlast
    INFO: [Synth 8-3331] design axi_spdif_tx has unconnected port s_axis_tvalid
    INFO: [Synth 8-3331] design util_adxcvr_xch has unconnected port qpll1_clk
    INFO: [Synth 8-3331] design util_adxcvr_xch has unconnected port qpll1_ref_clk
    INFO: [Synth 8-3331] design util_adxcvr_xch has unconnected port up_es_reset
    INFO: [Synth 8-3331] design util_adxcvr_xch has unconnected port up_tx_lpm_dfe_n
    INFO: [Synth 8-3331] design util_adxcvr_xch has unconnected port up_tx_diffctrl[4]
    INFO: [Synth 8-3331] design ad_pnmon__parameterized0 has unconnected port adc_pattern_has_zero
    INFO: [Synth 8-3331] design up_axi__parameterized1 has unconnected port up_axi_awaddr[1]
    INFO: [Synth 8-3331] design up_axi__parameterized1 has unconnected port up_axi_awaddr[0]
    INFO: [Synth 8-3331] design up_axi__parameterized1 has unconnected port up_axi_wstrb[3]
    INFO: [Synth 8-3331] design up_axi__parameterized1 has unconnected port up_axi_wstrb[2]
    INFO: [Synth 8-3331] design up_axi__parameterized1 has unconnected port up_axi_wstrb[1]
    INFO: [Synth 8-3331] design up_axi__parameterized1 has unconnected port up_axi_wstrb[0]
    INFO: [Synth 8-3331] design up_axi__parameterized1 has unconnected port up_axi_araddr[1]
    INFO: [Synth 8-3331] design up_axi__parameterized1 has unconnected port up_axi_araddr[0]
    INFO: [Synth 8-3331] design axi_xcvrlb has unconnected port s_axi_awaddr[15]
    INFO: [Synth 8-3331] design axi_xcvrlb has unconnected port s_axi_awaddr[14]
    INFO: [Synth 8-3331] design axi_xcvrlb has unconnected port s_axi_awaddr[13]
    INFO: [Synth 8-3331] design axi_xcvrlb has unconnected port s_axi_awaddr[12]
    INFO: [Synth 8-3331] design axi_xcvrlb has unconnected port s_axi_awaddr[11]
    INFO: [Synth 8-3331] design axi_xcvrlb has unconnected port s_axi_awaddr[10]
    INFO: [Synth 8-3331] design axi_xcvrlb has unconnected port s_axi_awprot[2]
    INFO: [Synth 8-3331] design axi_xcvrlb has unconnected port s_axi_awprot[1]
    INFO: [Synth 8-3331] design axi_xcvrlb has unconnected port s_axi_awprot[0]
    INFO: [Synth 8-3331] design axi_xcvrlb has unconnected port s_axi_araddr[15]
    INFO: [Synth 8-3331] design axi_xcvrlb has unconnected port s_axi_araddr[14]
    INFO: [Synth 8-3331] design axi_xcvrlb has unconnected port s_axi_araddr[13]
    INFO: [Synth 8-3331] design axi_xcvrlb has unconnected port s_axi_araddr[12]
    INFO: [Synth 8-3331] design axi_xcvrlb has unconnected port s_axi_araddr[11]
    INFO: [Synth 8-3331] design axi_xcvrlb has unconnected port s_axi_araddr[10]
    INFO: [Synth 8-3331] design axi_xcvrlb has unconnected port s_axi_arprot[2]
    INFO: [Synth 8-3331] design axi_xcvrlb has unconnected port s_axi_arprot[1]
    INFO: [Synth 8-3331] design axi_xcvrlb has unconnected port s_axi_arprot[0]
    INFO: [Synth 8-3331] design dynamic_master has unconnected port Cr[0]
    INFO: [Synth 8-3331] design dynamic_master has unconnected port Cr[1]
    INFO: [Synth 8-3331] design dynamic_master has unconnected port Cr[2]
    INFO: [Synth 8-3331] design dynamic_master has unconnected port Cr[4]
    INFO: [Synth 8-3331] design dynamic_master has unconnected port Cr[6]
    INFO: [Synth 8-3331] design dynamic_master has unconnected port Cr[7]
    INFO: [Synth 8-3331] design iic_control has unconnected port Adr[0]
    INFO: [Synth 8-3331] design iic_control has unconnected port Ten_adr[7]
    INFO: [Synth 8-3331] design iic_control has unconnected port Ten_adr[6]
    INFO: [Synth 8-3331] design iic_control has unconnected port Ten_adr[5]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_aclk
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_resetn
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[31]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[30]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[29]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[28]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[27]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[26]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[25]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[24]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[23]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[22]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[21]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[20]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[19]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[18]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[17]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[16]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[15]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[14]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[13]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[12]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[11]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[10]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[9]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[8]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[7]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[6]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[5]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[4]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[3]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[2]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[1]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port prmry_vect_in[0]
    INFO: [Synth 8-3331] design cdc_sync__parameterized0 has unconnected port scndry_resetn
    INFO: [Synth 8-3331] design debounce has unconnected port Rst
    INFO: [Synth 8-3331] design debounce has unconnected port Stable
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Addr[0]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[0]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[1]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[2]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[3]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[4]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[5]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[6]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[7]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[8]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[9]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[10]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[11]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[12]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[13]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[14]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[15]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[16]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[17]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[18]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[19]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[20]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_Data[21]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_WrCE[1]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_WrCE[3]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_WrCE[5]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_WrCE[6]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Bus2IIC_WrCE[7]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Data_i2c[0]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Data_i2c[1]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Data_i2c[2]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Data_i2c[3]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Data_i2c[4]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Data_i2c[5]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Data_i2c[6]
    INFO: [Synth 8-3331] design reg_interface has unconnected port Data_i2c[7]
    INFO: [Synth 8-3331] design reg_interface has unconnected port reg_empty
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[0]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[1]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[2]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[3]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[4]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[5]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[6]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[7]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[8]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[9]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[10]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[11]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[12]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[13]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[14]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[15]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[16]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[17]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[18]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[19]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[20]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[21]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[22]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[23]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[24]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[25]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[26]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_Data[27]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_BE[0]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_BE[1]
    INFO: [Synth 8-3331] design soft_reset has unconnected port Bus2IP_BE[2]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[1]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[2]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[3]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[4]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[5]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[6]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[7]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[8]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[9]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[10]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[11]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[12]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[13]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[14]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[15]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[16]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[17]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[18]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[19]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[20]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[21]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[22]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_data[23]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_be[1]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_be[2]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port bus2ip_be[3]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_rdce[0]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_rdce[1]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_rdce[2]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_rdce[3]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_rdce[4]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_rdce[5]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_rdce[6]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_rdce[9]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_rdce[11]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_rdce[12]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_rdce[13]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_rdce[14]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_rdce[15]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_wrce[0]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_wrce[1]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_wrce[2]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_wrce[3]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_wrce[4]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_wrce[5]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_wrce[6]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_wrce[9]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_wrce[11]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_wrce[12]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_wrce[13]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_wrce[14]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port interrupt_wrce[15]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port ipif_reg_interrupts[0]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port ipif_reg_interrupts[1]
    INFO: [Synth 8-3331] design interrupt_control has unconnected port ipif_lvl_interrupts[0]
    INFO: [Synth 8-3331] design pselect_f__parameterized17 has unconnected port A[1]
    INFO: [Synth 8-3331] design pselect_f__parameterized17 has unconnected port A[2]
    INFO: [Synth 8-3331] design pselect_f__parameterized17 has unconnected port A[3]
    INFO: [Synth 8-3331] design pselect_f__parameterized17 has unconnected port A[4]
    INFO: [Synth 8-3331] design pselect_f__parameterized17 has unconnected port A[5]
    INFO: [Synth 8-3331] design pselect_f__parameterized17 has unconnected port A[6]
    INFO: [Synth 8-3331] design pselect_f__parameterized17 has unconnected port A[7]
    INFO: [Synth 8-3331] design pselect_f__parameterized17 has unconnected port A[8]
    INFO: [Synth 8-3331] design pselect_f__parameterized16 has unconnected port A[7]
    INFO: [Synth 8-3331] design pselect_f__parameterized16 has unconnected port A[8]
    INFO: [Synth 8-3331] design pselect_f has unconnected port A[3]
    INFO: [Synth 8-3331] design pselect_f has unconnected port A[4]
    INFO: [Synth 8-3331] design pselect_f has unconnected port A[5]
    INFO: [Synth 8-3331] design pselect_f has unconnected port A[6]
    INFO: [Synth 8-3331] design pselect_f has unconnected port A[7]
    INFO: [Synth 8-3331] design pselect_f has unconnected port A[8]
    INFO: [Synth 8-3331] design address_decoder has unconnected port Bus_RNW
    INFO: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[3]
    INFO: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[2]
    INFO: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[1]
    INFO: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[0]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_awaddr[15]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_awaddr[14]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_awaddr[13]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_awaddr[12]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_awaddr[11]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_awaddr[10]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_awaddr[9]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_awaddr[8]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_awaddr[7]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_awaddr[6]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_awaddr[1]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_awaddr[0]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_wstrb[3]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_wstrb[2]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_wstrb[1]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_wstrb[0]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_araddr[15]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_araddr[14]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_araddr[13]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_araddr[12]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_araddr[11]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_araddr[10]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_araddr[9]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_araddr[8]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_araddr[7]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_araddr[6]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_araddr[1]
    INFO: [Synth 8-3331] design axi_ctrlif has unconnected port s_axi_araddr[0]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_aclk
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_aresetn
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[31]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[30]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[29]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[28]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[27]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[26]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[25]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[24]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[23]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[22]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[21]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[20]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[19]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[18]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[17]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[16]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[15]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[14]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[13]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[12]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[11]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[10]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[9]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[8]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[7]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[6]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[5]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[4]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[3]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[2]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[1]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tdata[0]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tlast
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axis_tvalid
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port m_axis_aclk
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port m_axis_tready
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axi_awprot[2]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axi_awprot[1]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axi_awprot[0]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axi_arprot[2]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axi_arprot[1]
    INFO: [Synth 8-3331] design axi_i2s_adi has unconnected port s_axi_arprot[0]
    INFO: [Synth 8-3331] design sc_util_v1_0_4_onehot_to_binary has unconnected port din[0]
    INFO: [Synth 8-3331] design sc_util_v1_0_4_pipeline__parameterized0 has unconnected port aclk
    INFO: [Synth 8-3331] design sc_util_v1_0_4_pipeline__parameterized0 has unconnected port aclken
    INFO: [Synth 8-3331] design sc_util_v1_0_4_pipeline__parameterized0 has unconnected port areset
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port sleep
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port rsta
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port regcea
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port injectsbiterra
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port injectdbiterra
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port clkb
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port regceb
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port web[0]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[100]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[99]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[98]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[97]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[96]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[95]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[94]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[93]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[92]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[91]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[90]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[89]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[88]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[87]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[86]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[85]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[84]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[83]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[82]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[81]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[80]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[79]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[78]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[77]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[76]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[75]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[74]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[73]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[72]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[71]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[70]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[69]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[68]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[67]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[66]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[65]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[64]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[63]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[62]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[61]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[60]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[59]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[58]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[57]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[56]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[55]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[54]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[53]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[52]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[51]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[50]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[49]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[48]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[47]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[46]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[45]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[44]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[43]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[42]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[41]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[40]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[39]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[38]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[37]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[36]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[35]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[34]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[33]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[32]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[31]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[30]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[29]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[28]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[27]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[26]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[25]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[24]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[23]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[22]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[21]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[20]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[19]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[18]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[17]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[16]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[15]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[14]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[13]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[12]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[11]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[10]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[9]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[8]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[7]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[6]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[5]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[4]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[3]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[2]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[1]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port dinb[0]
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port injectsbiterrb
    INFO: [Synth 8-3331] design xpm_memory_base__parameterized0 has unconnected port injectdbiterrb
    INFO: [Synth 8-3331] design sc_node_v1_0_10_reg_slice3 has unconnected port aclk
    INFO: [Synth 8-3331] design sc_node_v1_0_10_reg_slice3 has unconnected port aclken
    INFO: [Synth 8-3331] design sc_node_v1_0_10_reg_slice3 has unconnected port areset
    INFO: [Synth 8-3331] design sc_util_v1_0_4_pipeline__parameterized2 has unconnected port aclk
    INFO: [Synth 8-3331] design sc_util_v1_0_4_pipeline__parameterized2 has unconnected port aclken
    INFO: [Synth 8-3331] design sc_util_v1_0_4_pipeline__parameterized2 has unconnected port areset
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port areset
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port s_sc_req[0]
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port s_sc_info[0]
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port s_axis_arb_tvalid
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port s_axis_arb_tdata[15]
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port s_axis_arb_tdata[14]
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port s_axis_arb_tdata[13]
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port s_axis_arb_tdata[12]
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port s_axis_arb_tdata[11]
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port s_axis_arb_tdata[10]
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port s_axis_arb_tdata[9]
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port s_axis_arb_tdata[8]
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port s_axis_arb_tdata[7]
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port s_axis_arb_tdata[6]
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port s_axis_arb_tdata[5]
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port s_axis_arb_tdata[4]
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port s_axis_arb_tdata[3]
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port s_axis_arb_tdata[2]
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port s_axis_arb_tdata[1]
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port s_axis_arb_tdata[0]
    INFO: [Synth 8-3331] design sc_node_v1_0_10_si_handler__parameterized0 has unconnected port m_axis_arb_tready
    INFO: [Synth 8-3331] design sc_util_v1_0_4_axic_register_slice has unconnected port aclk
    INFO: [Synth 8-3331] design sc_util_v1_0_4_axic_register_slice has unconnected port areset
    INFO: [Synth 8-3331] design sc_util_v1_0_4_axic_register_slice has unconnected port aclken
    INFO: [Synth 8-3331] design sc_node_v1_0_10_top__parameterized0 has unconnected port m_sc_aclk
    INFO: [Synth 8-3331] design sc_node_v1_0_10_top__parameterized0 has unconnected port m_sc_aclken
    INFO: [Synth 8-3331] design sc_node_v1_0_10_top__parameterized0 has unconnected port m_sc_aresetn
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port sleep
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port rsta
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port regcea
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port injectsbiterra
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port injectdbiterra
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port clkb
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port regceb
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port web[0]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[153]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[152]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[151]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[150]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[149]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[148]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[147]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[146]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[145]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[144]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[143]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[142]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[141]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[140]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[139]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[138]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[137]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[136]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[135]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[134]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[133]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[132]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[131]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[130]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[129]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[128]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[127]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[126]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[125]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[124]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[123]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[122]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[121]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[120]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[119]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[118]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[117]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[116]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[115]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[114]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[113]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[112]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[111]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[110]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[109]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[108]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[107]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[106]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[105]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[104]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[103]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[102]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[101]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[100]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[99]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[98]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[97]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[96]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[95]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[94]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[93]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[92]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[91]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[90]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[89]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[88]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[87]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[86]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[85]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[84]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[83]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[82]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[81]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[80]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[79]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[78]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[77]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[76]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[75]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[74]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[73]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[72]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[71]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[70]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[69]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[68]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[67]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[66]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[65]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[64]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[63]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[62]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[61]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[60]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[59]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[58]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[57]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[56]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[55]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[54]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[53]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[52]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[51]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[50]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[49]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[48]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[47]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[46]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[45]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[44]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[43]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[42]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[41]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[40]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[39]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[38]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[37]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[36]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[35]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[34]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[33]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[32]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[31]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[30]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[29]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[28]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[27]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[26]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[25]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[24]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[23]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[22]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[21]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[20]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[19]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[18]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[17]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[16]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[15]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[14]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[13]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[12]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[11]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[10]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[9]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[8]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[7]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[6]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[5]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[4]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[3]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[2]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[1]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[0]
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port injectsbiterrb
    INFO: [Synth 8-3331] design xpm_memory_base has unconnected port injectdbiterrb
    INFO: [Synth 8-3331] design sc_util_v1_0_4_pipeline__parameterized1 has unconnected port aclk
    INFO: [Common 17-14] Message 'Synth 8-3331' appears 2000 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
    ---------------------------------------------------------------------------------
    Finished RTL Elaboration : Time (s): cpu = 00:00:55 ; elapsed = 00:01:17 . Memory (MB): peak = 2278.785 ; gain = 562.453 ; free physical = 294 ; free virtual = 1620
    ---------------------------------------------------------------------------------
    
    Report Check Netlist: 
    +------+------------------+-------+---------+-------+------------------+
    |      |Item              |Errors |Warnings |Status |Description       |
    +------+------------------+-------+---------+-------+------------------+
    |1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
    +------+------------------+-------+---------+-------+------------------+
    ---------------------------------------------------------------------------------
    Start Handling Custom Attributes
    ---------------------------------------------------------------------------------
    ---------------------------------------------------------------------------------
    Finished Handling Custom Attributes : Time (s): cpu = 00:00:59 ; elapsed = 00:01:22 . Memory (MB): peak = 2290.660 ; gain = 574.328 ; free physical = 339 ; free virtual = 1677
    ---------------------------------------------------------------------------------
    ---------------------------------------------------------------------------------
    Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:59 ; elapsed = 00:01:22 . Memory (MB): peak = 2290.660 ; gain = 574.328 ; free physical = 339 ; free virtual = 1677
    ---------------------------------------------------------------------------------
    INFO: [Netlist 29-17] Analyzing 297 Unisim elements for replacement
    INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
    INFO: [Project 1-570] Preparing netlist for logic optimization
    
    Processing XDC Constraints
    Initializing timing engine
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_ps7_0/system_sys_ps7_0.xdc] for cell 'i_system_wrapper/system_i/sys_ps7/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_ps7_0/system_sys_ps7_0.xdc] for cell 'i_system_wrapper/system_i/sys_ps7/inst'
    INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_ps7_0/system_sys_ps7_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_top_propImpl.xdc].
    Resolution: To avoid this warning, move constraints listed in [.Xil/system_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_iic_main_0/system_axi_iic_main_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_iic_main/U0'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_iic_main_0/system_axi_iic_main_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_iic_main/U0'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/system_sys_rstgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_rstgen/U0'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/system_sys_rstgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_rstgen/U0'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/system_sys_rstgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_rstgen/U0'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/system_sys_rstgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_rstgen/U0'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/axi_ad9361_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/axi_ad9361_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_tdd_sync_0/util_tdd_sync_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_tdd_sync/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_tdd_sync_0/util_tdd_sync_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_tdd_sync/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_reset_0/system_util_ad9361_divclk_reset_0_board.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_divclk_reset/U0'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_reset_0/system_util_ad9361_divclk_reset_0_board.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_divclk_reset/U0'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_reset_0/system_util_ad9361_divclk_reset_0.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_divclk_reset/U0'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_reset_0/system_util_ad9361_divclk_reset_0.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_divclk_reset/U0'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_adc_fifo/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_adc_fifo/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_fifo_0/util_rfifo_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_fifo_0/util_rfifo_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_1/bd_31bd_psr_aclk_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/clk_map/psr_aclk/U0'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_1/bd_31bd_psr_aclk_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/clk_map/psr_aclk/U0'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_1/bd_31bd_psr_aclk_0.xdc] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/clk_map/psr_aclk/U0'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_1/bd_31bd_psr_aclk_0.xdc] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/clk_map/psr_aclk/U0'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_1/bd_c0fd_psr_aclk_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/clk_map/psr_aclk/U0'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_1/bd_c0fd_psr_aclk_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/clk_map/psr_aclk/U0'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_1/bd_c0fd_psr_aclk_0.xdc] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/clk_map/psr_aclk/U0'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_1/bd_c0fd_psr_aclk_0.xdc] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/clk_map/psr_aclk/U0'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii/U0'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii/U0'
    INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_top_propImpl.xdc].
    Resolution: To avoid this warning, move constraints listed in [.Xil/system_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_rstgen_0/system_sys_rgmii_rstgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii_rstgen/U0'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_rstgen_0/system_sys_rgmii_rstgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii_rstgen/U0'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_rstgen_0/system_sys_rgmii_rstgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii_rstgen/U0'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_rstgen_0/system_sys_rgmii_rstgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii_rstgen/U0'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hdmi_core_0/axi_hdmi_tx_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hdmi_core_0/axi_hdmi_tx_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_spdif_tx_core_0/axi_spdif_tx_constr.xdc] for cell 'i_system_wrapper/system_i/axi_spdif_tx_core/U0'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_spdif_tx_core_0/axi_spdif_tx_constr.xdc] for cell 'i_system_wrapper/system_i/axi_spdif_tx_core/U0'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_1/bd_a17c_psr_aclk_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/clk_map/psr_aclk/U0'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_1/bd_a17c_psr_aclk_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/clk_map/psr_aclk/U0'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_1/bd_a17c_psr_aclk_0.xdc] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/clk_map/psr_aclk/U0'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hp0_interconnect_0/bd_0/ip/ip_1/bd_a17c_psr_aclk_0.xdc] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/clk_map/psr_aclk/U0'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_pz_xcvrlb_0/axi_xcvrlb_constr.xdc] for cell 'i_system_wrapper/system_i/axi_pz_xcvrlb/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_pz_xcvrlb_0/axi_xcvrlb_constr.xdc] for cell 'i_system_wrapper/system_i/axi_pz_xcvrlb/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc] for cell 'i_system_wrapper/system_i/axi_gpreg/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc] for cell 'i_system_wrapper/system_i/axi_gpreg/inst'
    INFO: [Timing 38-2] Deriving generated clocks
    write_xdc: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 3098.668 ; gain = 20.812 ; free physical = 127 ; free virtual = 689
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc]
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc]
    INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nicole/adi/hdl/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_top_propImpl.xdc].
    Resolution: To avoid this warning, move constraints listed in [.Xil/system_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc]
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc]
    INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nicole/adi/hdl/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_top_propImpl.xdc].
    Resolution: To avoid this warning, move constraints listed in [.Xil/system_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/common/ccfmc_constr.xdc]
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/common/ccfmc_constr.xdc]
    INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nicole/adi/hdl/projects/adrv9361z7035/common/ccfmc_constr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_top_propImpl.xdc].
    Resolution: To avoid this warning, move constraints listed in [.Xil/system_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.runs/synth_1/dont_touch.xdc]
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.runs/synth_1/dont_touch.xdc]
    INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_top_propImpl.xdc].
    Resolution: To avoid this warning, move constraints listed in [.Xil/system_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
    INFO: [Timing 38-2] Deriving generated clocks
    write_xdc: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 3098.668 ; gain = 0.000 ; free physical = 120 ; free virtual = 686
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/system_axi_ad9361_0_pps_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/system_axi_ad9361_0_pps_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_0/util_clkdiv_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_divclk/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_0/util_clkdiv_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_divclk/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_adc_dma_0/system_axi_ad9361_adc_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_adc_dma/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_adc_dma_0/system_axi_ad9361_adc_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_adc_dma/inst'
    INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_adc_dma_0/system_axi_ad9361_adc_dma_0_constr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_top_propImpl.xdc].
    Resolution: To avoid this warning, move constraints listed in [.Xil/system_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_dma_0/system_axi_ad9361_dac_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_dac_dma/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_dma_0/system_axi_ad9361_dac_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_dac_dma/inst'
    INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_dma_0/system_axi_ad9361_dac_dma_0_constr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_top_propImpl.xdc].
    Resolution: To avoid this warning, move constraints listed in [.Xil/system_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii/U0'
    INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'system_sys_rgmii_0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:7]
    WARNING: [Designutils 20-1567] Use of 'set_false_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:20]
    WARNING: [Designutils 20-1567] Use of 'set_false_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:21]
    WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:24]
    WARNING: [Designutils 20-1567] Use of 'set_false_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:32]
    WARNING: [Designutils 20-1567] Use of 'set_false_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc:33]
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc] for cell 'i_system_wrapper/system_i/sys_rgmii/U0'
    INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_rgmii_0/synth/system_sys_rgmii_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_top_propImpl.xdc].
    Resolution: To avoid this warning, move constraints listed in [.Xil/system_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hdmi_dma_0/system_axi_hdmi_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_dma/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_hdmi_dma_0/system_axi_hdmi_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_dma/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0_late.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0_late.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_i2s_adi_0/axi_i2s_adi_constr.xdc] for cell 'i_system_wrapper/system_i/axi_i2s_adi/U0'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_i2s_adi_0/axi_i2s_adi_constr.xdc] for cell 'i_system_wrapper/system_i/axi_i2s_adi/U0'
    INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_i2s_adi_0/axi_i2s_adi_constr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_top_propImpl.xdc].
    Resolution: To avoid this warning, move constraints listed in [.Xil/system_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
    Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_gpreg_0/system_axi_gpreg_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_gpreg/inst'
    Finished Parsing XDC File [/home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_gpreg_0/system_axi_gpreg_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_gpreg/inst'
    Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
    Finished Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
    Finished Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
    Finished Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
    Finished Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp0_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
    Finished Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp2_interconnect/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
    Finished Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3]
    Finished Sourcing Tcl File [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'i_system_wrapper/system_i/axi_hp1_interconnect/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
    INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_top_propImpl.xdc].
    Resolution: To avoid this warning, move constraints listed in [.Xil/system_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
    Completed Processing XDC Constraints
    
    Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3101.637 ; gain = 0.000 ; free physical = 102 ; free virtual = 670
    INFO: [Project 1-111] Unisim Transformation Summary:
      A total of 220 instances were transformed.
      BUFGMUX => BUFGCTRL (inverted pins: CE0): 2 instances
      BUFGMUX_CTRL => BUFGCTRL (inverted pins: S0): 1 instances
      DSP48E => DSP48E1: 24 instances
      FD => FDRE: 24 instances
      FDP => FDPE: 42 instances
      FDR => FDRE: 87 instances
      FDRSE => FDRSE (FDRE, LUT4, VCC): 5 instances
      IBUFGDS => IBUFDS: 1 instances
      IOBUF => IOBUF (IBUF, OBUFT): 3 instances
      IODELAYE1 => IDELAYE2: 5 instances
      MUXCY_L => MUXCY: 12 instances
      OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS, OBUFDS): 8 instances
      SRL16 => SRL16E: 6 instances
    
    Constraint Validation Runtime : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3101.637 ; gain = 0.000 ; free physical = 108 ; free virtual = 666
    ---------------------------------------------------------------------------------
    Finished Constraint Validation : Time (s): cpu = 00:02:28 ; elapsed = 00:02:47 . Memory (MB): peak = 3101.637 ; gain = 1385.305 ; free physical = 984 ; free virtual = 1551
    ---------------------------------------------------------------------------------
    ---------------------------------------------------------------------------------
    Start Loading Part and Timing Information
    ---------------------------------------------------------------------------------
    Loading part: xc7z035ifbg676-2L
    ---------------------------------------------------------------------------------
    Finished Loading Part and Timing Information : Time (s): cpu = 00:02:28 ; elapsed = 00:02:47 . Memory (MB): peak = 3101.637 ; gain = 1385.305 ; free physical = 984 ; free virtual = 1552
    ---------------------------------------------------------------------------------
    ---------------------------------------------------------------------------------
    Start Applying 'set_property' XDC Constraints
    ---------------------------------------------------------------------------------
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_up_adc_channel/i_xfer_cntrl/up_xfer_state_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_cntrl/up_xfer_state_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_cntrl/up_xfer_state_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_cntrl/up_xfer_state_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_cntrl/up_xfer_state_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_cntrl/up_xfer_state_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_cntrl/up_xfer_state_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_control/up_xfer_state_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_control/up_xfer_state_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_control/up_xfer_state_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_control/up_xfer_state_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_control/up_xfer_state_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_control/up_xfer_state_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_counter_values/up_xfer_state_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_counter_values/up_xfer_state_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_counter_values/up_xfer_state_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_counter_values/up_xfer_state_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_counter_values/up_xfer_state_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_counter_values/up_xfer_state_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_0/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_0/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_0/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_0/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_0/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_0/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_1/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_1/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_1/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_1/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_1/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_1/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_2/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_2/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_2/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_2/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_2/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_2/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_3/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_3/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_3/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_3/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_3/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_3/i_up_dac_channel/i_xfer_cntrl/up_xfer_state_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_cntrl/up_xfer_state_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_cntrl/up_xfer_state_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_cntrl/up_xfer_state_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_cntrl/up_xfer_state_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_cntrl/up_xfer_state_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_cntrl/up_xfer_state_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_up_adc_channel/i_xfer_cntrl/d_xfer_toggle_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_up_adc_channel/i_xfer_cntrl/d_xfer_toggle_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_up_adc_channel/i_xfer_cntrl/d_xfer_toggle_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_up_adc_channel/i_xfer_cntrl/d_xfer_toggle_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_up_adc_channel/i_xfer_cntrl/d_xfer_toggle_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_up_adc_channel/i_xfer_cntrl/d_xfer_toggle_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_up_adc_channel/i_xfer_cntrl/d_xfer_toggle_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_up_adc_channel/i_xfer_cntrl/d_xfer_toggle_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_up_adc_channel/i_xfer_cntrl/d_xfer_toggle_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_up_adc_channel/i_xfer_cntrl/d_xfer_toggle_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_up_adc_channel/i_xfer_cntrl/d_xfer_toggle_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_up_adc_channel/i_xfer_cntrl/d_xfer_toggle_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_cntrl/d_xfer_toggle_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_cntrl/d_xfer_toggle_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_cntrl/d_xfer_toggle_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_control/d_xfer_toggle_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_control/d_xfer_toggle_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_control/d_xfer_toggle_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_counter_values/d_xfer_toggle_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_counter_values/d_xfer_toggle_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_counter_values/d_xfer_toggle_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_0/i_up_dac_channel/i_xfer_cntrl/d_xfer_toggle_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_0/i_up_dac_channel/i_xfer_cntrl/d_xfer_toggle_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_0/i_up_dac_channel/i_xfer_cntrl/d_xfer_toggle_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_1/i_up_dac_channel/i_xfer_cntrl/d_xfer_toggle_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_1/i_up_dac_channel/i_xfer_cntrl/d_xfer_toggle_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_1/i_up_dac_channel/i_xfer_cntrl/d_xfer_toggle_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_2/i_up_dac_channel/i_xfer_cntrl/d_xfer_toggle_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_2/i_up_dac_channel/i_xfer_cntrl/d_xfer_toggle_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_2/i_up_dac_channel/i_xfer_cntrl/d_xfer_toggle_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_3/i_up_dac_channel/i_xfer_cntrl/d_xfer_toggle_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_3/i_up_dac_channel/i_xfer_cntrl/d_xfer_toggle_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_tx_channel_3/i_up_dac_channel/i_xfer_cntrl/d_xfer_toggle_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_cntrl/d_xfer_toggle_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_cntrl/d_xfer_toggle_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_cntrl/d_xfer_toggle_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_delay_cntrl/i_delay_rst_reg/rst_async_d1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_delay_cntrl/i_delay_rst_reg/rst_async_d2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_core_rst_reg/rst_async_d1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_core_rst_reg/rst_async_d2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_mmcm_rst_reg/rst_async_d1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_mmcm_rst_reg/rst_async_d2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_delay_cntrl/i_delay_rst_reg/rst_async_d1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_delay_cntrl/i_delay_rst_reg/rst_async_d2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_core_rst_reg/rst_async_d1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_core_rst_reg/rst_async_d2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_mmcm_rst_reg/rst_async_d1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_mmcm_rst_reg/rst_async_d2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_delay_cntrl/i_delay_rst_reg/rst_sync_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc, line 5).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_core_rst_reg/rst_sync_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc, line 5).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_mmcm_rst_reg/rst_sync_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc, line 5).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_delay_cntrl/i_delay_rst_reg/rst_sync_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc, line 5).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_core_rst_reg/rst_sync_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc, line 5).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_mmcm_rst_reg/rst_sync_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc, line 5).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_up_adc_channel/i_xfer_status/d_xfer_state_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_up_adc_channel/i_xfer_status/d_xfer_state_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_up_adc_channel/i_xfer_status/d_xfer_state_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_up_adc_channel/i_xfer_status/d_xfer_state_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_up_adc_channel/i_xfer_status/d_xfer_state_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_up_adc_channel/i_xfer_status/d_xfer_state_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_up_adc_channel/i_xfer_status/d_xfer_state_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_up_adc_channel/i_xfer_status/d_xfer_state_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_up_adc_channel/i_xfer_status/d_xfer_state_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_up_adc_channel/i_xfer_status/d_xfer_state_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_up_adc_channel/i_xfer_status/d_xfer_state_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_up_adc_channel/i_xfer_status/d_xfer_state_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_status/d_xfer_state_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_status/d_xfer_state_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_status/d_xfer_state_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_status/d_xfer_state_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_status/d_xfer_state_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_status/d_xfer_state_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_status/d_xfer_state_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_status/d_xfer_state_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_status/d_xfer_state_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m3_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_0/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m3_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_1/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m3_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_2/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m3_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_rx_channel_3/i_up_adc_channel/i_xfer_status/up_xfer_toggle_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_status/up_xfer_toggle_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_status/up_xfer_toggle_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_status/up_xfer_toggle_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_status/up_xfer_toggle_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_status/up_xfer_toggle_m3_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_xfer_status/up_xfer_toggle_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_status/up_xfer_toggle_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_status/up_xfer_toggle_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_status/up_xfer_toggle_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_status/up_xfer_toggle_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_status/up_xfer_toggle_m3_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_up_tdd_cntrl/i_xfer_tdd_status/up_xfer_toggle_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_status/up_xfer_toggle_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_status/up_xfer_toggle_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_status/up_xfer_toggle_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_status/up_xfer_toggle_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_status/up_xfer_toggle_m3_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_xfer_status/up_xfer_toggle_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_count_running_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_count_running_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_count_running_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_count_running_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_count_running_m3_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_count_running_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_count_running_m1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_count_running_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_count_running_m2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_count_running_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_count_running_m3_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_count_running_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/d_count_run_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/d_count_run_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/d_count_run_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/d_count_run_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/d_count_run_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/d_count_run_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/i_clock_mon/up_d_count_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_dev_if/enable_up_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/axi_ad9361_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_dev_if/enable_up_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/axi_ad9361_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_dev_if/txnrx_up_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/axi_ad9361_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_dev_if/txnrx_up_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/axi_ad9361_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_tdd_control/tdd_sync_d1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/axi_ad9361_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_tdd_control/tdd_sync_d2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/axi_ad9361_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_tdd_control/tdd_sync_d3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/axi_ad9361_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/util_ad9361_tdd_sync/inst/sync_mode_d1_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_tdd_sync_0/util_tdd_sync_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/util_ad9361_tdd_sync/inst/sync_mode_d1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_tdd_sync_0/util_tdd_sync_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/util_ad9361_tdd_sync/inst/sync_mode_d2_i. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_tdd_sync_0/util_tdd_sync_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/util_ad9361_tdd_sync/inst/sync_mode_d2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_tdd_sync_0/util_tdd_sync_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_enable_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_enable_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_enable_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_enable_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_enable_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_enable_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_enable_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_enable_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_req_t_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_req_t_m2_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/dout_req_t_m3_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc, line 3).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/util_ad9361_adc_fifo/inst/din_ovf_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc, line 4).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_enable_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_fifo_0/util_rfifo_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_enable_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_fifo_0/util_rfifo_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_enable_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_fifo_0/util_rfifo_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_enable_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_fifo_0/util_rfifo_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_enable_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_fifo_0/util_rfifo_constr.xdc, line 2).
    Applied set_property ASYNC_REG = true for i_system_wrapper/system_i/axi_ad9361_dac_fifo/inst/din_enable_m1_reg. (constraint file  /home/nicole/adi/hdl/projects/adrv9361z7035/ccfmc_lvds/adrv9361z7035_ccfmc_lvds.srcs/