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ADRV9009 ZCU102 HDL for 2 lanes

Hello Team,

I have configured on no-os, adrv9008-2 successfully on zcu102 eval board using reference hdl design of ADI.

Now for one of my application, I am ok with 245.76MHz sample rate. So,i want to generate HDL for 2 lanes so that my data interface comes to 16 bit width.

I have seen some discussions regarding this topic and did the following steps to generate HDL.

In adrv9009_bd.tcl,

set tx_number_lanes  2

set dac_data_width  64

set dac_dma_data_width  64 and in system_top.v, i changed tx_data from 4 lines to 2 lines.

Then I generated bitstream succesfully.While Configuring on no-os,Link is stuck in CGS phase.

While generating profiles from talise_profile_wizard,Tx_sample rate =122.88 MHz,

Primary BW = 75 MHz, Lane rate is 4915.2MHz.

Have attached talise_config.c and error log for reference.

/**
 * \file talise_config.c
 * \brief Contains Talise configuration settings for the Talise API
 *
 * Copyright 2015-2017 Analog Devices Inc.
 * Released under the AD9378-AD9379 API license, for more information see the "LICENSE.txt" file in this zip file.
 *
 * The top level structure taliseDevice_t talDevice uses keyword
 * extern to allow the application layer main() to have visibility
 * to these settings.
 *
 * This file may not be fully complete for the end user application and 
 * may need to updated for AGC, GPIO, and DAC full scale settings. 
 * To create a full initialisation routine, the user should also refer to the 
 * Iron Python initialisation routine generated by the GUI, and also the Talise User Guide.
 *
 */

#include "talise_types.h"
#include "talise_config.h"
#include "talise_error.h"
#include "talise_agc.h"
#ifdef ADI_ZYNQ_PLATFORM
#include "zynq_platform.h"
#endif

int16_t txFirCoefs[80] = {0, 0, 0, 1, 0, -3, 1, 7, -3, -13, 7, 25, -14, -42, 27, 69, -46, -107, 74, 160, -115, -229, 184, 336, -264, -468, 382, 653, -538, -904, 754, 1269, -1056, -1842, 1486, 2879, -2031, -4846, 3817, 16221, 16221, 3817, -4846, -2031, 2879, 1486, -1842, -1056, 1269, 754, -904, -538, 653, 382, -468, -264, 336, 184, -229, -115, 160, 74, -107, -46, 69, 27, -42, -14, 25, 7, -13, -3, 7, 1, -3, 0, 1, 0, 0, 0};

int16_t rxFirCoefs[72] = {0, -1, 2, 3, -4, -7, 10, 16, -21, -31, 40, 56, -71, -96, 119, 157, -187, -241, 288, 363, -431, -538, 622, 772, -891, -1105, 1264, 1582, -1819, -2335, 2710, 3697, -4461, -7201, 9397, 31111, 31111, 9397, -7201, -4461, 3697, 2710, -2335, -1819, 1582, 1264, -1105, -891, 772, 622, -538, -431, 363, 288, -241, -187, 157, 119, -96, -71, 56, 40, -31, -21, 16, 10, -7, -4, 3, 2, -1, 0};

int16_t obsrxFirCoefs[72] = {0, -1, 2, 2, -4, -6, 10, 13, -20, -26, 38, 47, -66, -81, 110, 133, -172, -205, 265, 309, -395, -460, 566, 661, -809, -947, 1138, 1331, -1683, -2008, 2490, 3163, -4146, -6051, 9721, 29849, 29849, 9721, -6051, -4146, 3163, 2490, -2008, -1683, 1331, 1138, -947, -809, 661, 566, -460, -395, 309, 265, -205, -172, 133, 110, -81, -66, 47, 38, -26, -20, 13, 10, -6, -4, 2, 2, -1, 0};

#ifdef ADI_ZYNQ_PLATFORM /** < Insert Customer Platform HAL State Container here>*/
/*
 * Platform Layer SPI settings - this structure is specific to ADI's platform layer code.
 * User should replace with their own structure or settings for their hardware
 */
zynqSpiSettings_t spiDev1 =
{
	.chipSelectIndex = 1,
	.writeBitPolarity = 0,
	.longInstructionWord = 1,
	.CPHA = 0,
	.CPOL = 0,
	.mode = 0,
	.spiClkFreq_Hz = 25000000
};

/*
 * Platform Layer settings - this structure is specific to ADI's platform layer code.
 * User should replace with their own structure or settings for their hardware
 * The structure is held in taliseDevice_t below as a void pointer, allowing
 * the customer to pass any information for their specific hardware down to the
 * hardware layer code.
 */
zynqAdiDev_t talDevHalInfo =
{
	.devIndex = 1,
	.spiSettings = &spiDev1,
	.spiErrCode = 0,
	.timerErrCode = 0,
	.gpioErrCode = 0,
	.logLevel = ADIHAL_LOG_ALL
};
#endif
/**
 *  TalDevice a structure used by the Talise API to hold the platform hardware
 *  structure information, as well as an internal Talise API state container
 *  (devStateInfo) of runtime information used by the API.
 **/
taliseDevice_t talDevice =
{
#ifdef ADI_ZYNQ_PLATFORM
    /* Void pointer of users platform HAL settings to pass to HAL layer calls
     * Talise API does not use the devHalInfo member */
	.devHalInfo = &talDevHalInfo,
#else
	.devHalInfo = NULL,     /*/** < Insert Customer Platform HAL State Container here>*/
#endif
	/* devStateInfo is maintained internal to the Talise API, just create the memory */
	.devStateInfo = {0}

};

taliseInit_t talInit =
{
	/* SPI settings */
    .spiSettings =
    {
		.MSBFirst            = 1,  /* 1 = MSBFirst, 0 = LSBFirst */
		.enSpiStreaming      = 0,  /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */
		.autoIncAddrUp       = 1,  /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr=addr-1 */
		.fourWireMode        = 1,  /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */
		.cmosPadDrvStrength  = TAL_CMOSPAD_DRV_2X /* Drive strength of CMOS pads when used as outputs (SDIO, SDO, GP_INTERRUPT, GPIO 1, GPIO 0) */
	},
	
    /* Rx settings */
    .rx = 
    {
        .rxProfile =
        {
            .rxFir = 
            {
                .gain_dB = -6,                /* filter gain */
                .numFirCoefs = 72,            /* number of coefficients in the FIR filter */
                .coefs = &rxFirCoefs[0]
            },
            .rxFirDecimation = 2,            /* Rx FIR decimation (1,2,4) */
            .rxDec5Decimation = 4,            /* Decimation of Dec5 or Dec4 filter (5,4) */
            .rhb1Decimation = 2,            /* RX Half band 1 decimation (1 or 2) */
            .rxOutputRate_kHz = 122880,            /* Rx IQ data rate in kHz */
            .rfBandwidth_Hz = 100000000,    /* The Rx RF passband bandwidth for the profile */
            .rxBbf3dBCorner_kHz = 100000,    /* Rx BBF 3dB corner in kHz */
            .rxAdcProfile = {265, 146, 181, 90, 1280, 366, 1257, 27, 1258, 17, 718, 39, 48, 46, 27, 161, 0, 0, 0, 0, 40, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},            /* pointer to custom ADC profile */
            .rxDdcMode = TAL_RXDDC_BYPASS,   /* Rx DDC mode */
            .rxNcoShifterCfg =
            {
                .bandAInputBandWidth_kHz = 0,
                .bandAInputCenterFreq_kHz = 0,
                .bandANco1Freq_kHz = 0,
                .bandANco2Freq_kHz = 0,
                .bandBInputBandWidth_kHz = 0,
                .bandBInputCenterFreq_kHz = 0,
                .bandBNco1Freq_kHz = 0,
                .bandBNco2Freq_kHz = 0
            }
        },
        .framerSel = TAL_FRAMER_A,            /* Rx JESD204b framer configuration */
        .rxGainCtrl = 
        {
            .gainMode = TAL_MGC,            /* taliserxGainMode_t gainMode */
            .rx1GainIndex = 255,            /* uint8_t rx1GainIndex */
            .rx2GainIndex = 255,            /* uint8_t rx2GainIndex */
            .rx1MaxGainIndex = 255,            /* uint8_t rx1MaxGainIndex */
            .rx1MinGainIndex = 195,            /* uint8_t rx1MinGainIndex */
            .rx2MaxGainIndex = 255,            /* uint8_t rx2MaxGainIndex */
            .rx2MinGainIndex = 195            /* uint8_t rx2MinGainIndex */
        },
        .rxChannels = TAL_RX1RX2,                /* The desired Rx Channels to enable during initialization */
    },


    /* Tx settings */
    .tx = 
    {
        .txProfile =
        {
            .dacDiv = 1,                        /* The divider used to generate the DAC clock */
            .txFir = 
            {
                .gain_dB = 6,                        /* filter gain */
                .numFirCoefs = 80,                    /* number of coefficients in the FIR filter */
                .coefs = &txFirCoefs[0]
            },
            .txFirInterpolation = 2,                    /* The Tx digital FIR filter interpolation (1,2,4) */
            .thb1Interpolation = 2,                    /* Tx Halfband1 filter interpolation (1,2) */
            .thb2Interpolation = 2,                    /* Tx Halfband2 filter interpolation (1,2)*/
            .thb3Interpolation = 2,                    /* Tx Halfband3 filter interpolation (1,2)*/
            .txInt5Interpolation = 1,                    /* Tx Int5 filter interpolation (1,5) */
            .txInputRate_kHz = 122880,                    /* Primary Signal BW */
            .primarySigBandwidth_Hz = 50000000,    /* The Rx RF passband bandwidth for the profile */
            .rfBandwidth_Hz = 100000000,            /* The Tx RF passband bandwidth for the profile */
            .txDac3dBCorner_kHz = 187000,                /* The DAC filter 3dB corner in kHz */
            .txBbf3dBCorner_kHz = 56000,                /* The BBF 3dB corner in kHz */
            .loopBackAdcProfile = {265, 146, 181, 90, 1280, 366, 1257, 27, 1258, 17, 718, 39, 48, 46, 27, 161, 0, 0, 0, 0, 40, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905}
        },
        .deframerSel = TAL_DEFRAMER_A,                    /* Talise JESD204b deframer config for the Tx data path */
        .txChannels = TAL_TX1TX2,                            /* The desired Tx channels to enable during initialization */
        .txAttenStepSize = TAL_TXATTEN_0P05_DB,            /* Tx Attenuation step size */
        .tx1Atten_mdB = 0,                            /* Initial Tx1 Attenuation */
        .tx2Atten_mdB = 0,                            /* Initial Tx2 Attenuation */
        .disTxDataIfPllUnlock = TAL_TXDIS_TX_RAMP_DOWN_TO_ZERO    /* Options to disable the transmit data when the RFPLL unlocks. */
    },


    /* ObsRx settings */
    .obsRx = 
    {
        .orxProfile =
        {
            .rxFir = 
            {
                .gain_dB = -6,                /* filter gain */
                .numFirCoefs = 72,            /* number of coefficients in the FIR filter */
                .coefs = &obsrxFirCoefs[0]
            },
            .rxFirDecimation = 2,            /* Rx FIR decimation (1,2,4) */
            .rxDec5Decimation = 4,            /* Decimation of Dec5 or Dec4 filter (5,4) */
            .rhb1Decimation = 2,            /* RX Half band 1 decimation (1 or 2) */
            .orxOutputRate_kHz = 122880,            /* Rx IQ data rate in kHz */
            .rfBandwidth_Hz = 100000000,    /* The Rx RF passband bandwidth for the profile */
            .rxBbf3dBCorner_kHz = 225000,    /* Rx BBF 3dB corner in kHz */
            .orxLowPassAdcProfile = {265, 146, 181, 90, 1280, 366, 1257, 27, 1258, 17, 718, 39, 48, 46, 27, 161, 0, 0, 0, 0, 40, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},
            .orxBandPassAdcProfile = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
            .orxDdcMode = TAL_ORXDDC_DISABLED,   /* ORx DDC mode */
            .orxMergeFilter  = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
        },
        .orxGainCtrl = 
        {
            .gainMode = TAL_MGC,
            .orx1GainIndex = 255,
            .orx2GainIndex = 255,
            .orx1MaxGainIndex = 255,
            .orx1MinGainIndex = 195,
            .orx2MaxGainIndex = 255,
            .orx2MinGainIndex = 195
        },
        .framerSel = TAL_FRAMER_B,                /* ObsRx JESD204b framer configuration */
        .obsRxChannelsEnable = TAL_ORX1ORX2,        /* The desired ObsRx Channels to enable during initialization */
        .obsRxLoSource = TAL_OBSLO_RF_PLL                /* The ORx mixers can use the TX_PLL */
    },

    /* Digital Clock Settings */
    .clocks = 
    {
        .deviceClock_kHz = 245760,            /* CLKPLL and device reference clock frequency in kHz */
        .clkPllVcoFreq_kHz = 9830400,        /* CLKPLL VCO frequency in kHz */
        .clkPllHsDiv = TAL_HSDIV_2P5,            /* CLKPLL high speed clock divider */
        .rfPllUseExternalLo = 0,                /* 1= Use external LO for RF PLL, 0 = use internal LO generation for RF PLL */
        .rfPllPhaseSyncMode = TAL_RFPLLMCS_NOSYNC                /* RFPLL MCS (Phase sync) mode */
    },

    /* JESD204B settings */
    .jesd204Settings = 
    {
        /* Framer A settings */
        .framerA = 
        {
            .bankId = 1,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
            .deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
            .lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
            .M = 4,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
            .K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
            .F = 4,                            /* F (number of bytes per frame) */
            .Np = 16,                            /* Np (converter sample resolution) */
            .scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
            .externalSysref = 1,            /* 0=use internal SYSREF, 1= use external SYSREF */
            .serializerLanesEnabled = 0x03,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
            .serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
            .lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
            .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
            .syncbInSelect = 0,                /* syncbInSelect; */
            .overSample = 0,                    /* 1=overSample, 0=bitRepeat */
            .syncbInLvdsMode = 1,
            .syncbInLvdsPnInvert = 0,
            .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
        },
        /* Framer B settings */
        .framerB = 
        {
            .bankId = 0,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
            .deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
            .lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
            .M = 4,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
            .K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
            .F = 4,                            /* F (number of bytes per frame) */
            .Np = 16,                            /* Np (converter sample resolution) */
            .scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
            .externalSysref = 1,            /* 0=use internal SYSREF, 1= use external SYSREF */
            .serializerLanesEnabled = 0x0C,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
            .serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
            .lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
            .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
            .syncbInSelect = 1,                /* syncbInSelect; */
            .overSample = 0,                    /* 1=overSample, 0=bitRepeat */
            .syncbInLvdsMode = 1,
            .syncbInLvdsPnInvert = 0,
            .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
        },
        /* Deframer A settings */
        .deframerA = 
        {
            .bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
            .deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
            .lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
            .M = 4,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
            .K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
            .scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
            .externalSysref = 1,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
            .deserializerLanesEnabled = 0x09,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
            .deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
            .lmfcOffset = 17,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
            .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
            .syncbOutSelect = 0,                /* SYNCBOUT0/1 select */
            .Np = 16,                /* Np (converter sample resolution) */
            .syncbOutLvdsMode = 1,
            .syncbOutLvdsPnInvert = 0,
            .syncbOutCmosSlewRate = 0,
            .syncbOutCmosDriveLevel = 0,
            .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
        },
        /* Deframer B settings */
        .deframerB = 
        {
            .bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
            .deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
            .lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
            .M = 0,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
            .K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
            .scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
            .externalSysref = 1,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
            .deserializerLanesEnabled = 0x00,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
            .deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
            .lmfcOffset = 0,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
            .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
            .syncbOutSelect = 1,                /* SYNCBOUT0/1 select */
            .Np = 16,                /* Np (converter sample resolution) */
            .syncbOutLvdsMode = 1,
            .syncbOutLvdsPnInvert = 0,
            .syncbOutCmosSlewRate = 0,
            .syncbOutCmosDriveLevel = 0,
            .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
        },
        .serAmplitude = 15,                    /* Serializer amplitude setting. Default = 15. Range is 0..15 */
        .serPreEmphasis = 1,                /* Serializer pre-emphasis setting. Default = 1 Range is 0..4 */
        .serInvertLanePolarity = 0,            /* Serializer Lane PN inversion select. Default = 0. Where, bit[0] = 1 will invert lane [0], bit[1] = 1 will invert lane 1, etc. */
        .desInvertLanePolarity = 0,            /* Deserializer Lane PN inversion select.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc */
        .desEqSetting = 1,                    /* Deserializer Equalizer setting. Applied to all deserializer lanes. Range is 0..4 */
        .sysrefLvdsMode = 1,                /* Use LVDS inputs on Talise for SYSREF */
        .sysrefLvdsPnInvert = 0              /*0= Do not PN invert SYSREF */
    }
};

//Only needs to be called if user wants to setup AGC parameters
static taliseAgcCfg_t rxAgcCtrl =
{
    4,
    255,
    195,
    255,
    195,
    30720,  /* AGC gain update time in us (125us-250us - based on IQ data rate - set for 125us @ 245.76 Mhz) */
    10,
    10,
    16,
    0,
    1,
    0,
    0,
    0,
    1,
    31,
    246,
    4,
    1,          /*!<1- bit field to enable the multiple time constants in AGC loop for fast attack and fast recovery to max gain. */
    /* agcPower */
    {
        1,      /*!<1-bit field, enables the Rx power measurement block. */
        1,      /*!<1-bit field, allows using Rx PFIR for power measurement. */
        0,      /*!<1-bit field, allows to use the output of the second digital offset block in the Rx datapath for power measurement. */
        9,      /*!<AGC power measurement detect lower 0 threshold. Default = -12dBFS == 5, 7-bit register value where max = 0x7F, min = 0x00 */
        2,      /*!<AGC power measurement detect lower 1 threshold. Default = (offset) 4dB == 0, 4-bit register value where  max = 0xF, min = 0x00 */
        4,      /*!<AGC power measurement detect lower 0 recovery gain step. Default = 2dB - based on gain table step  size, 5-bit register value where max = 0x1F, min = 0x00 */
        4,      /*!<AGC power measurement detect lower 1 recovery gain step. Default = 4dB - based on gain table step size, 5-bit register value where max = 0x1F, min = 0x00 */
        5,      /*!< power measurement duration used by the decimated power block. Default = 0x05, 5-bit register value where max = 0x1F, min = 0x00 */
        5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
        1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
        5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
        1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
        2,      /*!<Default value should be 2*/
        0,
        0
    },
    /* agcPeak */
    {
        205,        /*!<1st update interval for the multiple time constant in AGC loop mode, Default:205. */
        2,          /*!<sets the 2nd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of  agcUnderRangeLowInterval  , Default: 4 */
        4,          /*!<sets the 3rd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of agcUnderRangeMidInterval and agcUnderRangeLowInterval, Default: 4 */
        39,         /*!<AGC APD high threshold. Default=0x1F, 6-bit register value where max=0x3F, min =0x00 */
        49,         /*!<AGC APD peak detect high threshold. default = 0x1F, 6-bit register value where max = 0x3F, min = 0x00.  Set to 3dB below apdHighThresh */
        23,         /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max =0x3F, min = 0x00 */
        19,         /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max = 0x3F, min = 0x00 . Set to 3dB below apdLowThresh  */
        6,          /*!<AGC APD peak detect upper threshold count. Default = 0x06 8-bit register value where max = 0xFF, min = 0x20  */
        3,          /*!<AGC APD peak detect lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00  */
        4,          /*!<AGC APD peak detect attack gain step. Default = 2dB step - based on gain table step size, 5-bit register  value, where max = 0x1F, min = 0x00  */
        2,          /*!<AGC APD gain index step size. Recommended to be same as hb2GainStepRecovery. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00  */
        1,          /*!<1-bit field, enables or disables the HB2 overload detector.  */
        1,          /*!<3-bit field. Sets the window of clock cycles (at the HB2 output rate) to meet the overload count. */
        1,          /*!<4-bit field. Sets the number of actual overloads required to trigger the overload signal.  */
        181,        /*!<AGC decimator output high threshold. Default = 0xB5, 8-bit register value where max = 0xFF, min = 0x00 */
        45,         /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
        90,         /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
        128,        /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
        6,          /*!<AGC HB2 output upper threshold count. Default = 0x06, 8-bit register value where max = 0xFF, min =  0x20 */
        3,          /*!<AGC HB2 output lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00 */
        2,          /*!<AGC decimator gain index step size. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00 */
        4,          /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 0 triggers a programmable number  of times. Default = 0x08, 5-bit register value where max = 0x1F, min = 0x00 */
        8,          /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 1 triggers a programmable number of times. Default = 0x04, 5-bit register value where max = 0x1F, min = 0x00 */
        4,          /*!<AGC decimator output attack gain step. Default = 2dB step - based on gain table step size, 5-bit register value, where max = 0x1F, min = 0x00 */
        1,
        0,
        0
    }
};

Thanks

Deepika



font
[edited by: Dheeru@3 at 9:47 AM (GMT -4) on 21 Oct 2021]
Parents
  • Hello,

    Can you check if the two lanes you enabled in ADRV9009 are the same that are connected to the FPGA ?

    If you use these two for ORX:

    https://github.com/analogdevicesinc/hdl/blob/master/projects/adrv9009/zcu102/system_constr.xdc#L8-L11

    and these two for TX:

    https://github.com/analogdevicesinc/hdl/blob/master/projects/adrv9009/zcu102/system_constr.xdc#L16-L19

    Then indeed lanes 0 and 3 should be enabled in talise_config.c.

    Otherwise, do you have a git branch with your modifications ?

    Regards,

    Adrian

  • Hello Adrian

    Thanks so much for the reply.

    I have connected TX and ORX lines as per the constraint files you have shared.

    I have attached modified adrv9009_bd.tcl,system_top.v and constraints file.

    #adrv9009_bd.tcl
    # TX parameters
    set TX_NUM_OF_LANES 2      ; # L
    set TX_NUM_OF_CONVERTERS 4 ; # M
    set TX_SAMPLES_PER_FRAME 1 ; # S
    set TX_SAMPLE_WIDTH 16     ; # N/NP
    
    set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / \
                                    ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
    
    # RX parameters
    set RX_NUM_OF_LANES 2      ; # L
    set RX_NUM_OF_CONVERTERS 4 ; # M
    set RX_SAMPLES_PER_FRAME 1 ; # S
    set RX_SAMPLE_WIDTH 16     ; # N/NP
    
    set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / \
                                    ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
    
    # RX Observation parameters
    set RX_OS_NUM_OF_LANES 2      ; # L
    set RX_OS_NUM_OF_CONVERTERS 2 ; # M
    set RX_OS_SAMPLES_PER_FRAME 1 ; # S
    set RX_OS_SAMPLE_WIDTH 16     ; # N/NP
    
    set RX_OS_SAMPLES_PER_CHANNEL [expr $RX_OS_NUM_OF_LANES * 32 / \
                                       ($RX_OS_NUM_OF_CONVERTERS * $RX_OS_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
    
    set dac_fifo_name axi_adrv9009_dacfifo
    set dac_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL]
    set dac_dma_data_width 64
    
    source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
    source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl
    
    # adrv9009
    
    create_bd_port -dir I dac_fifo_bypass
    create_bd_port -dir I adc_fir_filter_active
    create_bd_port -dir I dac_fir_filter_active
    
    # dac peripherals
    
    ad_ip_instance axi_clkgen axi_adrv9009_tx_clkgen
    ad_ip_parameter axi_adrv9009_tx_clkgen CONFIG.ID 2
    ad_ip_parameter axi_adrv9009_tx_clkgen CONFIG.CLKIN_PERIOD 4
    ad_ip_parameter axi_adrv9009_tx_clkgen CONFIG.VCO_DIV 1
    ad_ip_parameter axi_adrv9009_tx_clkgen CONFIG.VCO_MUL 4
    ad_ip_parameter axi_adrv9009_tx_clkgen CONFIG.CLK0_DIV 4
    
    ad_ip_instance axi_adxcvr axi_adrv9009_tx_xcvr
    ad_ip_parameter axi_adrv9009_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
    ad_ip_parameter axi_adrv9009_tx_xcvr CONFIG.QPLL_ENABLE 1
    ad_ip_parameter axi_adrv9009_tx_xcvr CONFIG.TX_OR_RX_N 1
    ad_ip_parameter axi_adrv9009_tx_xcvr CONFIG.SYS_CLK_SEL 3
    ad_ip_parameter axi_adrv9009_tx_xcvr CONFIG.OUT_CLK_SEL 3
    
    adi_axi_jesd204_tx_create axi_adrv9009_tx_jesd $TX_NUM_OF_LANES
    
    ad_ip_instance util_upack2 util_adrv9009_tx_upack [list \
      NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
      SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
      SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \
    ]
    
    ad_add_interpolation_filter "tx_fir_interpolator" 8 $TX_NUM_OF_CONVERTERS 2 {122.88} {15.36} \
                                 "$ad_hdl_dir/library/util_fir_int/coefile_int.coe"
    
    
    adi_tpl_jesd204_tx_create tx_adrv9009_tpl_core $TX_NUM_OF_LANES \
                                                   $TX_NUM_OF_CONVERTERS \
                                                   $TX_SAMPLES_PER_FRAME \
                                                   $TX_SAMPLE_WIDTH
    
    ad_ip_instance axi_dmac axi_adrv9009_tx_dma
    ad_ip_parameter axi_adrv9009_tx_dma CONFIG.DMA_TYPE_SRC 0
    ad_ip_parameter axi_adrv9009_tx_dma CONFIG.DMA_TYPE_DEST 1
    ad_ip_parameter axi_adrv9009_tx_dma CONFIG.CYCLIC 1
    ad_ip_parameter axi_adrv9009_tx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
    ad_ip_parameter axi_adrv9009_tx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
    ad_ip_parameter axi_adrv9009_tx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
    ad_ip_parameter axi_adrv9009_tx_dma CONFIG.DMA_2D_TRANSFER 0
    ad_ip_parameter axi_adrv9009_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width
    ad_ip_parameter axi_adrv9009_tx_dma CONFIG.MAX_BYTES_PER_BURST 256
    ad_ip_parameter axi_adrv9009_tx_dma CONFIG.AXI_SLICE_DEST true
    ad_ip_parameter axi_adrv9009_tx_dma CONFIG.AXI_SLICE_SRC true
    
    ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
    
    # adc peripherals
    
    ad_ip_instance axi_clkgen axi_adrv9009_rx_clkgen
    ad_ip_parameter axi_adrv9009_rx_clkgen CONFIG.ID 2
    ad_ip_parameter axi_adrv9009_rx_clkgen CONFIG.CLKIN_PERIOD 4
    ad_ip_parameter axi_adrv9009_rx_clkgen CONFIG.VCO_DIV 1
    ad_ip_parameter axi_adrv9009_rx_clkgen CONFIG.VCO_MUL 4
    ad_ip_parameter axi_adrv9009_rx_clkgen CONFIG.CLK0_DIV 4
    
    ad_ip_instance axi_adxcvr axi_adrv9009_rx_xcvr
    ad_ip_parameter axi_adrv9009_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
    ad_ip_parameter axi_adrv9009_rx_xcvr CONFIG.QPLL_ENABLE 0
    ad_ip_parameter axi_adrv9009_rx_xcvr CONFIG.TX_OR_RX_N 0
    ad_ip_parameter axi_adrv9009_rx_xcvr CONFIG.SYS_CLK_SEL 0
    ad_ip_parameter axi_adrv9009_rx_xcvr CONFIG.OUT_CLK_SEL 3
    
    adi_axi_jesd204_rx_create axi_adrv9009_rx_jesd $RX_NUM_OF_LANES
    
    ad_ip_instance util_cpack2 util_adrv9009_rx_cpack [list \
      NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
      SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
      SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
      ]
    
    adi_tpl_jesd204_rx_create rx_adrv9009_tpl_core $RX_NUM_OF_LANES \
                                                   $RX_NUM_OF_CONVERTERS \
                                                   $RX_SAMPLES_PER_FRAME \
                                                   $RX_SAMPLE_WIDTH
    
    ad_add_decimation_filter "rx_fir_decimator" 8 $RX_NUM_OF_CONVERTERS 1 {122.88} {122.88} \
                              "$ad_hdl_dir/library/util_fir_int/coefile_int.coe"
    
    ad_ip_instance axi_dmac axi_adrv9009_rx_dma
    ad_ip_parameter axi_adrv9009_rx_dma CONFIG.DMA_TYPE_SRC 2
    ad_ip_parameter axi_adrv9009_rx_dma CONFIG.DMA_TYPE_DEST 0
    ad_ip_parameter axi_adrv9009_rx_dma CONFIG.CYCLIC 0
    ad_ip_parameter axi_adrv9009_rx_dma CONFIG.SYNC_TRANSFER_START 1
    ad_ip_parameter axi_adrv9009_rx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
    ad_ip_parameter axi_adrv9009_rx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
    ad_ip_parameter axi_adrv9009_rx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
    ad_ip_parameter axi_adrv9009_rx_dma CONFIG.DMA_2D_TRANSFER 0
    ad_ip_parameter axi_adrv9009_rx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $RX_SAMPLE_WIDTH * \
                                                                        $RX_NUM_OF_CONVERTERS * \
                                                                        $RX_SAMPLES_PER_CHANNEL]
    ad_ip_parameter axi_adrv9009_rx_dma CONFIG.MAX_BYTES_PER_BURST 256
    ad_ip_parameter axi_adrv9009_rx_dma CONFIG.AXI_SLICE_DEST true
    ad_ip_parameter axi_adrv9009_rx_dma CONFIG.AXI_SLICE_SRC true
    
    # adc-os peripherals
    
    ad_ip_instance axi_clkgen axi_adrv9009_rx_os_clkgen
    ad_ip_parameter axi_adrv9009_rx_os_clkgen CONFIG.ID 2
    ad_ip_parameter axi_adrv9009_rx_os_clkgen CONFIG.CLKIN_PERIOD 4
    ad_ip_parameter axi_adrv9009_rx_os_clkgen CONFIG.VCO_DIV 1
    ad_ip_parameter axi_adrv9009_rx_os_clkgen CONFIG.VCO_MUL 4
    ad_ip_parameter axi_adrv9009_rx_os_clkgen CONFIG.CLK0_DIV 4
    
    ad_ip_instance axi_adxcvr axi_adrv9009_rx_os_xcvr
    ad_ip_parameter axi_adrv9009_rx_os_xcvr CONFIG.NUM_OF_LANES $RX_OS_NUM_OF_LANES
    ad_ip_parameter axi_adrv9009_rx_os_xcvr CONFIG.QPLL_ENABLE 0
    ad_ip_parameter axi_adrv9009_rx_os_xcvr CONFIG.TX_OR_RX_N 0
    ad_ip_parameter axi_adrv9009_rx_os_xcvr CONFIG.SYS_CLK_SEL 0
    ad_ip_parameter axi_adrv9009_rx_os_xcvr CONFIG.OUT_CLK_SEL 3
    
    adi_axi_jesd204_rx_create axi_adrv9009_rx_os_jesd $RX_OS_NUM_OF_LANES
    
    ad_ip_instance util_cpack2 util_adrv9009_rx_os_cpack [list \
      NUM_OF_CHANNELS $RX_OS_NUM_OF_CONVERTERS \
      SAMPLES_PER_CHANNEL $RX_OS_SAMPLES_PER_CHANNEL\
      SAMPLE_DATA_WIDTH $RX_OS_SAMPLE_WIDTH \
    ]
    
    adi_tpl_jesd204_rx_create rx_os_adrv9009_tpl_core $RX_OS_NUM_OF_LANES \
                                                      $RX_OS_NUM_OF_CONVERTERS \
                                                      $RX_OS_SAMPLES_PER_FRAME \
                                                      $RX_OS_SAMPLE_WIDTH
    
    ad_ip_instance axi_dmac axi_adrv9009_rx_os_dma
    ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.DMA_TYPE_SRC 2
    ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.DMA_TYPE_DEST 0
    ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.CYCLIC 0
    ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.SYNC_TRANSFER_START 1
    ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.ASYNC_CLK_DEST_REQ 1
    ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.ASYNC_CLK_SRC_DEST 1
    ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.ASYNC_CLK_REQ_SRC 1
    ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.DMA_2D_TRANSFER 0
    ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $RX_OS_SAMPLE_WIDTH * \
                                                                           $RX_OS_NUM_OF_CONVERTERS * \
                                                                           $RX_OS_SAMPLES_PER_CHANNEL];
    ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.MAX_BYTES_PER_BURST 256
    ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.AXI_SLICE_DEST true
    ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.AXI_SLICE_SRC true
    
    # common cores
    
    
    ad_ip_instance util_adxcvr util_adrv9009_xcvr
    ad_ip_parameter util_adrv9009_xcvr CONFIG.RX_NUM_OF_LANES [expr $RX_NUM_OF_LANES+$RX_OS_NUM_OF_LANES]
    ad_ip_parameter util_adrv9009_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
    ad_ip_parameter util_adrv9009_xcvr CONFIG.TX_OUT_DIV 1
    ad_ip_parameter util_adrv9009_xcvr CONFIG.CPLL_FBDIV 4
    ad_ip_parameter util_adrv9009_xcvr CONFIG.CPLL_FBDIV_4_5 5
    ad_ip_parameter util_adrv9009_xcvr CONFIG.RX_CLK25_DIV 10
    ad_ip_parameter util_adrv9009_xcvr CONFIG.TX_CLK25_DIV 10
    ad_ip_parameter util_adrv9009_xcvr CONFIG.RX_PMA_CFG 0x001E7080
    ad_ip_parameter util_adrv9009_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020
    ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_FBDIV 0x080
    
    # xcvr interfaces
    
    set tx_ref_clk     tx_ref_clk_0
    set rx_ref_clk     rx_ref_clk_0
    set rx_obs_ref_clk rx_ref_clk_$RX_NUM_OF_LANES
    
    create_bd_port -dir I $tx_ref_clk
    create_bd_port -dir I $rx_ref_clk
    create_bd_port -dir I $rx_obs_ref_clk
    ad_connect  $sys_cpu_resetn util_adrv9009_xcvr/up_rstn
    ad_connect  $sys_cpu_clk util_adrv9009_xcvr/up_clk
    
    # Tx
    ad_connect adrv9009_tx_device_clk axi_adrv9009_tx_clkgen/clk_0
    ad_xcvrcon util_adrv9009_xcvr axi_adrv9009_tx_xcvr axi_adrv9009_tx_jesd {0 1} adrv9009_tx_device_clk
    ad_connect util_adrv9009_xcvr/tx_out_clk_0 axi_adrv9009_tx_clkgen/clk
    ad_xcvrpll $tx_ref_clk util_adrv9009_xcvr/qpll_ref_clk_0
    ad_xcvrpll axi_adrv9009_tx_xcvr/up_pll_rst util_adrv9009_xcvr/up_qpll_rst_0
    
    # Rx
    ad_connect adrv9009_rx_device_clk axi_adrv9009_rx_clkgen/clk_0
    ad_xcvrcon  util_adrv9009_xcvr axi_adrv9009_rx_xcvr axi_adrv9009_rx_jesd {} adrv9009_rx_device_clk
    ad_connect util_adrv9009_xcvr/rx_out_clk_0 axi_adrv9009_rx_clkgen/clk
    for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} {
      set ch [expr $i]
      ad_xcvrpll  $rx_ref_clk util_adrv9009_xcvr/cpll_ref_clk_$ch
      ad_xcvrpll  axi_adrv9009_rx_xcvr/up_pll_rst util_adrv9009_xcvr/up_cpll_rst_$ch
    }
    
    # Rx - OBS
    ad_connect adrv9009_rx_os_device_clk axi_adrv9009_rx_os_clkgen/clk_0
    ad_xcvrcon util_adrv9009_xcvr axi_adrv9009_rx_os_xcvr axi_adrv9009_rx_os_jesd {} adrv9009_rx_os_device_clk
    ad_connect util_adrv9009_xcvr/rx_out_clk_$RX_NUM_OF_LANES axi_adrv9009_rx_os_clkgen/clk
    for {set i 0} {$i < $RX_OS_NUM_OF_LANES} {incr i} {
      # channel indexing starts from the last RX
      set ch [expr $RX_NUM_OF_LANES + $i]
      ad_xcvrpll  $rx_obs_ref_clk util_adrv9009_xcvr/cpll_ref_clk_$ch
      ad_xcvrpll  axi_adrv9009_rx_os_xcvr/up_pll_rst util_adrv9009_xcvr/up_cpll_rst_$ch
    }
    
    # connections (dac)
    
    ad_connect  axi_adrv9009_tx_clkgen/clk_0 tx_adrv9009_tpl_core/link_clk
    ad_connect  axi_adrv9009_tx_jesd/tx_data tx_adrv9009_tpl_core/link
    
    ad_connect  axi_adrv9009_tx_clkgen/clk_0 util_adrv9009_tx_upack/clk
    ad_connect  adrv9009_tx_device_clk_rstgen/peripheral_reset util_adrv9009_tx_upack/reset
    
    ad_ip_instance util_vector_logic logic_or [list \
      C_OPERATION {or} \
      C_SIZE 1]
    
    ad_connect  logic_or/Op1  tx_fir_interpolator/valid_out_0
    ad_connect  logic_or/Op2  tx_fir_interpolator/valid_out_2
    ad_connect  logic_or/Res  util_adrv9009_tx_upack/fifo_rd_en
    
    ad_connect tx_fir_interpolator/aclk axi_adrv9009_tx_clkgen/clk_0
    for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
      ad_connect  tx_adrv9009_tpl_core/dac_enable_$i  tx_fir_interpolator/dac_enable_$i
      ad_connect  tx_adrv9009_tpl_core/dac_valid_$i  tx_fir_interpolator/dac_valid_$i
    
      ad_connect  util_adrv9009_tx_upack/fifo_rd_data_$i  tx_fir_interpolator/data_in_${i}
      ad_connect  util_adrv9009_tx_upack/enable_$i  tx_fir_interpolator/enable_out_${i}
    
      ad_connect  tx_fir_interpolator/data_out_${i}  tx_adrv9009_tpl_core/dac_data_$i
    }
    
    ad_connect  tx_fir_interpolator/active dac_fir_filter_active
    
    ad_connect  axi_adrv9009_tx_clkgen/clk_0 axi_adrv9009_dacfifo/dac_clk
    ad_connect  adrv9009_tx_device_clk_rstgen/peripheral_reset axi_adrv9009_dacfifo/dac_rst
    
    # TODO: Add streaming AXI interface for DAC FIFO
    ad_connect  util_adrv9009_tx_upack/s_axis_valid VCC
    ad_connect  util_adrv9009_tx_upack/s_axis_ready axi_adrv9009_dacfifo/dac_valid
    ad_connect  util_adrv9009_tx_upack/s_axis_data axi_adrv9009_dacfifo/dac_data
    
    ad_connect  $sys_dma_clk axi_adrv9009_dacfifo/dma_clk
    ad_connect  $sys_dma_reset axi_adrv9009_dacfifo/dma_rst
    ad_connect  $sys_dma_clk axi_adrv9009_tx_dma/m_axis_aclk
    ad_connect  axi_adrv9009_dacfifo/dma_valid axi_adrv9009_tx_dma/m_axis_valid
    ad_connect  axi_adrv9009_dacfifo/dma_data axi_adrv9009_tx_dma/m_axis_data
    ad_connect  axi_adrv9009_dacfifo/dma_ready axi_adrv9009_tx_dma/m_axis_ready
    ad_connect  axi_adrv9009_dacfifo/dma_xfer_req axi_adrv9009_tx_dma/m_axis_xfer_req
    ad_connect  axi_adrv9009_dacfifo/dma_xfer_last axi_adrv9009_tx_dma/m_axis_last
    ad_connect  axi_adrv9009_dacfifo/dac_dunf tx_adrv9009_tpl_core/dac_dunf
    ad_connect  axi_adrv9009_dacfifo/bypass dac_fifo_bypass
    ad_connect  $sys_dma_resetn axi_adrv9009_tx_dma/m_src_axi_aresetn
    
    # connections (adc)
    
    ad_connect  axi_adrv9009_rx_clkgen/clk_0 rx_adrv9009_tpl_core/link_clk
    ad_connect  axi_adrv9009_rx_jesd/rx_sof rx_adrv9009_tpl_core/link_sof
    ad_connect  axi_adrv9009_rx_jesd/rx_data_tdata rx_adrv9009_tpl_core/link_data
    ad_connect  axi_adrv9009_rx_jesd/rx_data_tvalid rx_adrv9009_tpl_core/link_valid
    ad_connect  axi_adrv9009_rx_clkgen/clk_0 util_adrv9009_rx_cpack/clk
    ad_connect  adrv9009_rx_device_clk_rstgen/peripheral_reset util_adrv9009_rx_cpack/reset
    
    ad_connect rx_fir_decimator/aclk axi_adrv9009_rx_clkgen/clk_0
    
    for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
      ad_connect  rx_adrv9009_tpl_core/adc_valid_$i rx_fir_decimator/valid_in_$i
      ad_connect  rx_adrv9009_tpl_core/adc_enable_$i rx_fir_decimator/enable_in_$i
      ad_connect  rx_adrv9009_tpl_core/adc_data_$i rx_fir_decimator/data_in_${i}
    
      ad_connect  rx_fir_decimator/enable_out_$i util_adrv9009_rx_cpack/enable_$i
      ad_connect  rx_fir_decimator/data_out_${i} util_adrv9009_rx_cpack/fifo_wr_data_$i
    }
    
    ad_connect rx_fir_decimator/active adc_fir_filter_active
    
    ad_connect  rx_fir_decimator/valid_out_0 util_adrv9009_rx_cpack/fifo_wr_en
    ad_connect  rx_adrv9009_tpl_core/adc_dovf util_adrv9009_rx_cpack/fifo_wr_overflow
    
    ad_connect  axi_adrv9009_rx_clkgen/clk_0 axi_adrv9009_rx_dma/fifo_wr_clk
    ad_connect  util_adrv9009_rx_cpack/packed_fifo_wr axi_adrv9009_rx_dma/fifo_wr
    ad_connect  $sys_dma_resetn axi_adrv9009_rx_dma/m_dest_axi_aresetn
    
    # connections (adc-os)
    
    ad_connect  axi_adrv9009_rx_os_clkgen/clk_0 rx_os_adrv9009_tpl_core/link_clk
    ad_connect  axi_adrv9009_rx_os_jesd/rx_sof rx_os_adrv9009_tpl_core/link_sof
    ad_connect  axi_adrv9009_rx_os_jesd/rx_data_tdata rx_os_adrv9009_tpl_core/link_data
    ad_connect  axi_adrv9009_rx_os_jesd/rx_data_tvalid rx_os_adrv9009_tpl_core/link_valid
    ad_connect  axi_adrv9009_rx_os_clkgen/clk_0 util_adrv9009_rx_os_cpack/clk
    ad_connect  adrv9009_rx_os_device_clk_rstgen/peripheral_reset util_adrv9009_rx_os_cpack/reset
    ad_connect  axi_adrv9009_rx_os_clkgen/clk_0 axi_adrv9009_rx_os_dma/fifo_wr_clk
    
    ad_connect  rx_os_adrv9009_tpl_core/adc_valid_0 util_adrv9009_rx_os_cpack/fifo_wr_en
    for {set i 0} {$i < $RX_OS_NUM_OF_CONVERTERS} {incr i} {
      ad_connect  rx_os_adrv9009_tpl_core/adc_enable_$i util_adrv9009_rx_os_cpack/enable_$i
      ad_connect  rx_os_adrv9009_tpl_core/adc_data_$i util_adrv9009_rx_os_cpack/fifo_wr_data_$i
    }
    ad_connect  rx_os_adrv9009_tpl_core/adc_dovf util_adrv9009_rx_os_cpack/fifo_wr_overflow
    ad_connect  util_adrv9009_rx_os_cpack/packed_fifo_wr axi_adrv9009_rx_os_dma/fifo_wr
    
    ad_connect  $sys_dma_resetn axi_adrv9009_rx_os_dma/m_dest_axi_aresetn
    
    # interconnect (cpu)
    
    ad_cpu_interconnect 0x44A00000 rx_adrv9009_tpl_core
    ad_cpu_interconnect 0x44A04000 tx_adrv9009_tpl_core
    ad_cpu_interconnect 0x44A08000 rx_os_adrv9009_tpl_core
    ad_cpu_interconnect 0x44A80000 axi_adrv9009_tx_xcvr
    ad_cpu_interconnect 0x43C00000 axi_adrv9009_tx_clkgen
    ad_cpu_interconnect 0x44A90000 axi_adrv9009_tx_jesd
    ad_cpu_interconnect 0x7c420000 axi_adrv9009_tx_dma
    ad_cpu_interconnect 0x44A60000 axi_adrv9009_rx_xcvr
    ad_cpu_interconnect 0x43C10000 axi_adrv9009_rx_clkgen
    ad_cpu_interconnect 0x44AA0000 axi_adrv9009_rx_jesd
    ad_cpu_interconnect 0x7c400000 axi_adrv9009_rx_dma
    ad_cpu_interconnect 0x44A50000 axi_adrv9009_rx_os_xcvr
    ad_cpu_interconnect 0x43C20000 axi_adrv9009_rx_os_clkgen
    ad_cpu_interconnect 0x44AB0000 axi_adrv9009_rx_os_jesd
    ad_cpu_interconnect 0x7c440000 axi_adrv9009_rx_os_dma
    
    # gt uses hp0, and 100MHz clock for both DRP and AXI4
    
    ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9009_rx_xcvr/m_axi
    ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9009_rx_os_xcvr/m_axi
    
    # interconnect (mem/dac)
    
    ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1
    ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9009_rx_os_dma/m_dest_axi
    ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
    ad_mem_hp2_interconnect $sys_dma_clk axi_adrv9009_rx_dma/m_dest_axi
    ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3
    ad_mem_hp3_interconnect $sys_dma_clk axi_adrv9009_tx_dma/m_src_axi
    
    # interrupts
    
    ad_cpu_interrupt ps-8 mb-8 axi_adrv9009_rx_os_jesd/irq
    ad_cpu_interrupt ps-9 mb-7 axi_adrv9009_tx_jesd/irq
    ad_cpu_interrupt ps-10 mb-15 axi_adrv9009_rx_jesd/irq
    ad_cpu_interrupt ps-11 mb-14 axi_adrv9009_rx_os_dma/irq
    ad_cpu_interrupt ps-12 mb-13- axi_adrv9009_tx_dma/irq
    ad_cpu_interrupt ps-13 mb-12 axi_adrv9009_rx_dma/irq
    
    

    system_constraints

    # adrv9009
    
    set_property  -dict {PACKAGE_PIN  G27} [get_ports ref_clk0_p]                                          ; ## D04  FMC_HPC1_GBTCLK0_M2C_C_P (NC)
    set_property  -dict {PACKAGE_PIN  G28} [get_ports ref_clk0_n]                                          ; ## D05  FMC_HPC1_GBTCLK0_M2C_C_N (NC)
    set_property  -dict {PACKAGE_PIN  E27} [get_ports ref_clk1_p]                                          ; ## B20  FMC_HPC1_GBTCLK1_M2C_C_P
    set_property  -dict {PACKAGE_PIN  E28} [get_ports ref_clk1_n]                                          ; ## B21  FMC_HPC1_GBTCLK1_M2C_C_N
    set_property  -dict {PACKAGE_PIN  D33} [get_ports rx_data_p[0]]                                        ; ## A02  FMC_HPC1_DP1_M2C_P
    set_property  -dict {PACKAGE_PIN  D34} [get_ports rx_data_n[0]]                                        ; ## A03  FMC_HPC1_DP1_M2C_N
    set_property  -dict {PACKAGE_PIN  C31} [get_ports rx_data_p[1]]                                        ; ## A06  FMC_HPC1_DP2_M2C_P
    set_property  -dict {PACKAGE_PIN  C32} [get_ports rx_data_n[1]]                                        ; ## A07  FMC_HPC1_DP2_M2C_N
    set_property  -dict {PACKAGE_PIN  E31} [get_ports rx_data_p[2]]                                        ; ## C06  FMC_HPC1_DP0_M2C_P
    set_property  -dict {PACKAGE_PIN  E32} [get_ports rx_data_n[2]]                                        ; ## C07  FMC_HPC1_DP0_M2C_N
    set_property  -dict {PACKAGE_PIN  B33} [get_ports rx_data_p[3]]                                        ; ## A10  FMC_HPC1_DP3_M2C_P
    set_property  -dict {PACKAGE_PIN  B34} [get_ports rx_data_n[3]]                                        ; ## A11  FMC_HPC1_DP3_M2C_N
    set_property  -dict {PACKAGE_PIN  D29} [get_ports tx_data_p[0]]                                        ; ## A22  FMC_HPC1_DP1_C2M_P (tx_data_p[0])
    set_property  -dict {PACKAGE_PIN  D30} [get_ports tx_data_n[0]]                                        ; ## A23  FMC_HPC1_DP1_C2M_N (tx_data_n[0])
    set_property  -dict {PACKAGE_PIN  B29} [get_ports tx_data_p[1]]                                        ; ## A26  FMC_HPC1_DP2_C2M_P (tx_data_p[3])
    set_property  -dict {PACKAGE_PIN  B30} [get_ports tx_data_n[1]]                                        ; ## A27  FMC_HPC1_DP2_C2M_N (tx_data_n[3])
    
    
    set_property  -dict {PACKAGE_PIN  AH1  IOSTANDARD LVDS} [get_ports rx_sync_p]                          ; ## G09  FMC_HPC1_LA03_P
    set_property  -dict {PACKAGE_PIN  AJ1  IOSTANDARD LVDS} [get_ports rx_sync_n]                          ; ## G10  FMC_HPC1_LA03_N
    set_property  -dict {PACKAGE_PIN  AE10 IOSTANDARD LVDS} [get_ports rx_os_sync_p]                       ; ## G27  FMC_HPC1_LA25_P (Sniffer)
    set_property  -dict {PACKAGE_PIN  AF10 IOSTANDARD LVDS} [get_ports rx_os_sync_n]                       ; ## G28  FMC_HPC1_LA25_N (Sniffer)
    set_property  -dict {PACKAGE_PIN  AD2  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_p]   ; ## H07  FMC_HPC1_LA02_P
    set_property  -dict {PACKAGE_PIN  AD1  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_n]   ; ## H08  FMC_HPC1_LA02_N
    set_property  -dict {PACKAGE_PIN  AE5  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref_p]    ; ## G06  FMC_HPC1_LA00_CC_P
    set_property  -dict {PACKAGE_PIN  AF5  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref_n]    ; ## G07  FMC_HPC1_LA00_CC_N
    set_property  -dict {PACKAGE_PIN  AH12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_1_p] ; ## H28  FMC_HPC1_LA24_P
    set_property  -dict {PACKAGE_PIN  AH11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_1_n] ; ## H29  FMC_HPC1_LA24_N
    set_property  -dict {PACKAGE_PIN  AJ6  IOSTANDARD LVDS } [get_ports sysref_out_p]                      ; ## D08  FMC_HPC1_LA01_CC_P
    set_property  -dict {PACKAGE_PIN  AJ5  IOSTANDARD LVDS } [get_ports sysref_out_n]                      ; ## D09  FMC_HPC1_LA01_CC_N
    
    set_property  -dict {PACKAGE_PIN  AE1  IOSTANDARD LVCMOS18} [get_ports spi_csn_ad9528]                 ; ## D15  FMC_HPC1_LA09_N
    set_property  -dict {PACKAGE_PIN  AE2  IOSTANDARD LVCMOS18} [get_ports spi_csn_adrv9009]               ; ## D14  FMC_HPC1_LA09_P
    set_property  -dict {PACKAGE_PIN  AD4  IOSTANDARD LVCMOS18} [get_ports spi_clk]                        ; ## H13  FMC_HPC1_LA07_P
    set_property  -dict {PACKAGE_PIN  AE4  IOSTANDARD LVCMOS18} [get_ports spi_mosi]                       ; ## H14  FMC_HPC1_LA07_N
    set_property  -dict {PACKAGE_PIN  AE3  IOSTANDARD LVCMOS18} [get_ports spi_miso]                       ; ## G12  FMC_HPC1_LA08_P
    
    set_property  -dict {PACKAGE_PIN  T12  IOSTANDARD LVCMOS18} [get_ports ad9528_reset_b]                 ; ## D26  FMC_HPC1_LA26_P
    set_property  -dict {PACKAGE_PIN  R12  IOSTANDARD LVCMOS18} [get_ports ad9528_sysref_req]              ; ## D27  FMC_HPC1_LA26_N
    set_property  -dict {PACKAGE_PIN  AG8  IOSTANDARD LVCMOS18} [get_ports adrv9009_tx1_enable]            ; ## D17  FMC_HPC1_LA13_P
    set_property  -dict {PACKAGE_PIN  AH7  IOSTANDARD LVCMOS18} [get_ports adrv9009_tx2_enable]            ; ## C18  FMC_HPC1_LA14_P
    set_property  -dict {PACKAGE_PIN  AH8  IOSTANDARD LVCMOS18} [get_ports adrv9009_rx1_enable]            ; ## D18  FMC_HPC1_LA13_N
    set_property  -dict {PACKAGE_PIN  AH6  IOSTANDARD LVCMOS18} [get_ports adrv9009_rx2_enable]            ; ## C19  FMC_HPC1_LA14_N
    set_property  -dict {PACKAGE_PIN  AE8  IOSTANDARD LVCMOS18} [get_ports adrv9009_test]                  ; ## H16  FMC_HPC1_LA11_P
    #set_property  -dict {PACKAGE_PIN  AG3  IOSTANDARD LVCMOS18} [get_ports adrv9009_test]                  ; ## D11  FMC_HPC1_LA05_P
    set_property  -dict {PACKAGE_PIN  AF2  IOSTANDARD LVCMOS18} [get_ports adrv9009_reset_b]               ; ## H10  FMC_HPC1_LA04_P
    set_property  -dict {PACKAGE_PIN  AF1  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpint]                 ; ## H11  FMC_HPC1_LA04_N
    
    set_property  -dict {PACKAGE_PIN  AD10 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_00]               ; ## H19  FMC_HPC1_LA15_P
    set_property  -dict {PACKAGE_PIN  AE9  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_01]               ; ## H20  FMC_HPC1_LA15_N
    set_property  -dict {PACKAGE_PIN  AG10 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_02]               ; ## G18  FMC_HPC1_LA16_P
    set_property  -dict {PACKAGE_PIN  AG9  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_03]               ; ## G19  FMC_HPC1_LA16_N
    set_property  -dict {PACKAGE_PIN  AC12 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_04]               ; ## H25  FMC_HPC1_LA21_P
    set_property  -dict {PACKAGE_PIN  AC11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_05]               ; ## H26  FMC_HPC1_LA21_N
    set_property  -dict {PACKAGE_PIN  Y8   IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_06]               ; ## C22  FMC_HPC1_LA18_CC_P
    set_property  -dict {PACKAGE_PIN  Y7   IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_07]               ; ## C23  FMC_HPC1_LA18_CC_N
    set_property  -dict {PACKAGE_PIN  AG11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_08]               ; ## G25  FMC_HPC1_LA22_N     (LVDS Pairs?)
    set_property  -dict {PACKAGE_PIN  AA11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_09]               ; ## H22  FMC_HPC1_LA19_P     (LVDS Pairs?)
    set_property  -dict {PACKAGE_PIN  AA10 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_10]               ; ## H23  FMC_HPC1_LA19_N     (LVDS Pairs?)
    set_property  -dict {PACKAGE_PIN  AB11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_11]               ; ## G21  FMC_HPC1_LA20_P     (LVDS Pairs?)
    set_property  -dict {PACKAGE_PIN  AB10 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_12]               ; ## G22  FMC_HPC1_LA20_N     (LVDS Pairs?)
    set_property  -dict {PACKAGE_PIN  AD6  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_13]               ; ## G16  FMC_HPC1_LA12_N (LVDS Pairs?)
    set_property  -dict {PACKAGE_PIN  AD7  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_14]               ; ## G15  FMC_HPC1_LA12_P (LVDS Pairs?)
    #set_property  -dict {PACKAGE_PIN  W11  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_13]               ; ## G31  FMC_HPC1_LA29_N     (LVDS Pairs?)
    #set_property  -dict {PACKAGE_PIN  W12  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_14]               ; ## G30  FMC_HPC1_LA29_P     (LVDS Pairs?)
    set_property  -dict {PACKAGE_PIN  AF11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_15]               ; ## G24  FMC_HPC1_LA22_P     (LVDS Pairs?)
    set_property  -dict {PACKAGE_PIN  AJ2  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_16]               ; ## C11  FMC_HPC1_LA06_N (LVDS Pairs?)
    set_property  -dict {PACKAGE_PIN  AH2  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_17]               ; ## C10  FMC_HPC1_LA06_P (LVDS Pairs?)
    set_property  -dict {PACKAGE_PIN  AF8  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_18]               ; ## H17  FMC_HPC1_LA11_N
    #set_property  -dict {PACKAGE_PIN  P9   IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_16]               ; ## G03  FMC_HPC1_CLK1_M2C_N (LVDS Pairs?)
    #set_property  -dict {PACKAGE_PIN  P10  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_17]               ; ## G02  FMC_HPC1_CLK1_M2C_P (LVDS Pairs?)
    #set_property  -dict {PACKAGE_PIN  AH3  IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_18]               ; ## D12  FMC_HPC1_LA05_N
    
    # clocks
    
    create_clock -name tx_ref_clk     -period  4.00 [get_ports ref_clk0_p]
    create_clock -name rx_ref_clk     -period  4.00 [get_ports ref_clk1_p]
    create_clock -name tx_div_clk     -period  4.00 [get_pins i_system_wrapper/system_i/util_adrv9009_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK]
    create_clock -name rx_div_clk     -period  4.00 [get_pins i_system_wrapper/system_i/util_adrv9009_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
    create_clock -name rx_os_div_clk  -period  4.00 [get_pins i_system_wrapper/system_i/util_adrv9009_xcvr/inst/i_xch_2/i_gthe4_channel/RXOUTCLK]
    

    system_top

    // ***************************************************************************
    // ***************************************************************************
    // Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
    //
    // In this HDL repository, there are many different and unique modules, consisting
    // of various HDL (Verilog or VHDL) components. The individual modules are
    // developed independently, and may be accompanied by separate and unique license
    // terms.
    //
    // The user should read each of these license terms, and understand the
    // freedoms and responsibilities that he or she has by using this source/core.
    //
    // This core is distributed in the hope that it will be useful, but WITHOUT ANY
    // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
    // A PARTICULAR PURPOSE.
    //
    // Redistribution and use of source or resulting binaries, with or without modification
    // of this file, are permitted under one of the following two license terms:
    //
    //   1. The GNU General Public License version 2 as published by the
    //      Free Software Foundation, which can be found in the top level directory
    //      of this repository (LICENSE_GPL2), and also online at:
    //      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
    //
    // OR
    //
    //   2. An ADI specific BSD license, which can be found in the top level directory
    //      of this repository (LICENSE_ADIBSD), and also on-line at:
    //      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
    //      This will allow to generate bit files and not release the source code,
    //      as long as it attaches to an ADI device.
    //
    // ***************************************************************************
    // ***************************************************************************
    
    `timescale 1ns/100ps
    
    module system_top (
    
      input       [12:0]      gpio_bd_i,
      output      [ 7:0]      gpio_bd_o,
    
      inout                   iic_scl,
      inout                   iic_sda,
    
      input                   ref_clk0_p,
      input                   ref_clk0_n,
      input                   ref_clk1_p,
      input                   ref_clk1_n,
      input       [ 3:0]      rx_data_p,
      input       [ 3:0]      rx_data_n,
      output      [ 1:0]      tx_data_p,
      output      [ 1:0]      tx_data_n,
      output                  rx_sync_p,
      output                  rx_sync_n,
      output                  rx_os_sync_p,
      output                  rx_os_sync_n,
      input                   tx_sync_p,
      input                   tx_sync_n,
      input                   tx_sync_1_p,
      input                   tx_sync_1_n,
      input                   sysref_p,
      input                   sysref_n,
    
      output                  sysref_out_p,
      output                  sysref_out_n,
    
      output                  spi_csn_ad9528,
      output                  spi_csn_adrv9009,
      output                  spi_clk,
      output                  spi_mosi,
      input                   spi_miso,
    
      inout                   ad9528_reset_b,
      inout                   ad9528_sysref_req,
      inout                   adrv9009_tx1_enable,
      inout                   adrv9009_tx2_enable,
      inout                   adrv9009_rx1_enable,
      inout                   adrv9009_rx2_enable,
      inout                   adrv9009_test,
      inout                   adrv9009_reset_b,
      inout                   adrv9009_gpint,
    
      inout                   adrv9009_gpio_00,
      inout                   adrv9009_gpio_01,
      inout                   adrv9009_gpio_02,
      inout                   adrv9009_gpio_03,
      inout                   adrv9009_gpio_04,
      inout                   adrv9009_gpio_05,
      inout                   adrv9009_gpio_06,
      inout                   adrv9009_gpio_07,
      inout                   adrv9009_gpio_15,
      inout                   adrv9009_gpio_08,
      inout                   adrv9009_gpio_09,
      inout                   adrv9009_gpio_10,
      inout                   adrv9009_gpio_11,
      inout                   adrv9009_gpio_12,
      inout                   adrv9009_gpio_14,
      inout                   adrv9009_gpio_13,
      inout                   adrv9009_gpio_17,
      inout                   adrv9009_gpio_16,
      inout                   adrv9009_gpio_18);
    
      // internal signals
    
      wire        [94:0]      gpio_i;
      wire        [94:0]      gpio_o;
      wire        [94:0]      gpio_t;
      wire        [20:0]      gpio_bd;
      wire        [ 2:0]      spi_csn;
      wire                    ref_clk0;
      wire                    ref_clk1;
      wire                    rx_sync;
      wire                    rx_os_sync;
      wire                    tx_sync;
      wire                    sysref;
    
      assign gpio_i[94:60] = gpio_o[94:60];
      assign gpio_i[31:21] = gpio_o[31:21];
    
      assign sysref_out = 0;
    
      // instantiations
    
      IBUFDS_GTE4 i_ibufds_rx_ref_clk (
        .CEB (1'd0),
        .I (ref_clk0_p),
        .IB (ref_clk0_n),
        .O (ref_clk0),
        .ODIV2 ());
    
      IBUFDS_GTE4 i_ibufds_ref_clk1 (
        .CEB (1'd0),
        .I (ref_clk1_p),
        .IB (ref_clk1_n),
        .O (ref_clk1),
        .ODIV2 ());
    
      OBUFDS i_obufds_rx_sync (
        .I (rx_sync),
        .O (rx_sync_p),
        .OB (rx_sync_n));
    
      OBUFDS i_obufds_rx_os_sync (
        .I (rx_os_sync),
        .O (rx_os_sync_p),
        .OB (rx_os_sync_n));
    
      OBUFDS i_obufds_sysref_out (
        .I (sysref_out),
        .O (sysref_out_p),
        .OB (sysref_out_n));
    
      IBUFDS i_ibufds_tx_sync (
        .I (tx_sync_p),
        .IB (tx_sync_n),
        .O (tx_sync));
    
      IBUFDS i_ibufds_tx_sync_1 (
        .I (tx_sync_1_p),
        .IB (tx_sync_1_n),
        .O (tx_sync_1));
    
      IBUFDS i_ibufds_sysref (
        .I (sysref_p),
        .IB (sysref_n),
        .O (sysref));
    
      ad_iobuf #(.DATA_WIDTH(28)) i_iobuf (
        .dio_t ({gpio_t[59:32]}),
        .dio_i ({gpio_o[59:32]}),
        .dio_o ({gpio_i[59:32]}),
        .dio_p ({ ad9528_reset_b,       // 59
                  ad9528_sysref_req,    // 58
                  adrv9009_tx1_enable,  // 57
                  adrv9009_tx2_enable,  // 56
                  adrv9009_rx1_enable,  // 55
                  adrv9009_rx2_enable,  // 54
                  adrv9009_test,        // 53
                  adrv9009_reset_b,     // 52
                  adrv9009_gpint,       // 51
                  adrv9009_gpio_00,     // 50
                  adrv9009_gpio_01,     // 49
                  adrv9009_gpio_02,     // 48
                  adrv9009_gpio_03,     // 47
                  adrv9009_gpio_04,     // 46
                  adrv9009_gpio_05,     // 45
                  adrv9009_gpio_06,     // 44
                  adrv9009_gpio_07,     // 43
                  adrv9009_gpio_15,     // 42
                  adrv9009_gpio_08,     // 41
                  adrv9009_gpio_09,     // 40
                  adrv9009_gpio_10,     // 39
                  adrv9009_gpio_11,     // 38
                  adrv9009_gpio_12,     // 37
                  adrv9009_gpio_14,     // 36
                  adrv9009_gpio_13,     // 35
                  adrv9009_gpio_17,     // 34
                  adrv9009_gpio_16,     // 33
                  adrv9009_gpio_18}));  // 32
    
      assign gpio_i[ 7: 0] = gpio_o[ 7: 0];
      assign gpio_i[20: 8] = gpio_bd_i;
      assign gpio_bd_o = gpio_o[ 7: 0];
    
      assign spi_csn_ad9528 =  spi_csn[0];
      assign spi_csn_adrv9009 =  spi_csn[1];
    
      system_wrapper i_system_wrapper (
        .dac_fifo_bypass (gpio_o[60]),
        .adc_fir_filter_active (gpio_o[61]),
        .dac_fir_filter_active (gpio_o[62]),
        .gpio_i (gpio_i),
        .gpio_o (gpio_o),
        .gpio_t (gpio_t),
        .rx_data_0_n (rx_data_n[0]),
        .rx_data_0_p (rx_data_p[0]),
        .rx_data_1_n (rx_data_n[1]),
        .rx_data_1_p (rx_data_p[1]),
        .rx_data_2_n (rx_data_n[2]),
        .rx_data_2_p (rx_data_p[2]),
        .rx_data_3_n (rx_data_n[3]),
        .rx_data_3_p (rx_data_p[3]),
        .rx_ref_clk_0 (ref_clk1),
        .rx_ref_clk_2 (ref_clk1),
        .rx_sync_0 (rx_sync),
        .rx_sync_2 (rx_os_sync),
        .rx_sysref_0 (sysref),
        .rx_sysref_2 (sysref),
        .spi0_sclk (spi_clk),
        .spi0_csn (spi_csn),
        .spi0_miso (spi_miso),
        .spi0_mosi (spi_mosi),
        .spi1_sclk (),
        .spi1_csn (),
        .spi1_miso (1'b0),
        .spi1_mosi (),
        .tx_data_0_n (tx_data_n[0]),
        .tx_data_0_p (tx_data_p[0]),
        .tx_data_1_n (tx_data_n[1]),
        .tx_data_1_p (tx_data_p[1]),
        .tx_ref_clk_0 (ref_clk1),
        .tx_sync_0 (tx_sync),
        .tx_sysref_0 (sysref));
    
    endmodule
    
    // ***************************************************************************
    // ***************************************************************************
    

    Thanks

    Deepika

  • Hello Deepika,

    I see you have enabled also the lanes for RX, so the system should work as it was initially.

    Did you use the 2019_r2 branches for both HDL and No_OS ?

    Regards,

    Adrian 

  • Hello Adrian

    Thanks for reply.

    I used 2019_r2 branches for both HDL and No_os from this link Releases · analogdevicesinc/hdl · GitHub.

    Sorry, i forgot to mention the RX part being used.

    Anything else i can try to make this work as it matches my requirement.

    Regards

    Deepika

  • Hello Deepika,

    We're trying to reproduce your setup on our side.

    Regards,

    Adrian

  • In the meantime, can you try using a profile with 245.76Msps ?

    Have you used the guide https://wiki.analog.com/resources/eval/user-guides/adrv9009/no-os-setup to create the No-OS project?

    Regards,

    Adrian

Reply Children
  • Thanks Adrian for reply.

    I tried using a profile of 245.76 MSPS. Now tx is in ILAS and orx is in CGS phase.

    Profile details and talise_config.c I have attached for the response.

    /**
     * \file talise_config.c
     * \brief Contains Talise configuration settings for the Talise API
     *
     * Copyright 2015-2017 Analog Devices Inc.
     * Released under the AD9378-AD9379 API license, for more information see the "LICENSE.txt" file in this zip file.
     *
     * The top level structure taliseDevice_t talDevice uses keyword
     * extern to allow the application layer main() to have visibility
     * to these settings.
     *
     * This file may not be fully complete for the end user application and 
     * may need to updated for AGC, GPIO, and DAC full scale settings. 
     * To create a full initialisation routine, the user should also refer to the 
     * Iron Python initialisation routine generated by the GUI, and also the Talise User Guide.
     *
     */
    
    #include "talise_types.h"
    #include "talise_config.h"
    #include "talise_error.h"
    #include "talise_agc.h"
    #ifdef ADI_ZYNQ_PLATFORM
    #include "zynq_platform.h"
    #endif
    
    int16_t txFirCoefs[40] = {-14, 5, -9, 6, -4, 19, -29, 27, -30, 46, -63, 77, -103, 150, -218, 337, -599, 1266, -2718, 19537, -2718, 1266, -599, 337, -218, 150, -103, 77, -63, 46, -30, 27, -29, 19, -4, 6, -9, 5, -14, 0};
    
    int16_t rxFirCoefs[48] = {-2, 23, 46, -17, -104, 10, 208, 23, -370, -97, 607, 240, -942, -489, 1407, 910, -2065, -1637, 3058, 2995, -4912, -6526, 9941, 30489, 30489, 9941, -6526, -4912, 2995, 3058, -1637, -2065, 910, 1407, -489, -942, 240, 607, -97, -370, 23, 208, 10, -104, -17, 46, 23, -2};
    
    int16_t obsrxFirCoefs[24] = {-10, 7, -10, -12, 6, -12, 16, -16, 1, 63, -431, 17235, -431, 63, 1, -16, 16, -12, 6, -12, -10, 7, -10, 0};
    
    #ifdef ADI_ZYNQ_PLATFORM /** < Insert Customer Platform HAL State Container here>*/
    /*
     * Platform Layer SPI settings - this structure is specific to ADI's platform layer code.
     * User should replace with their own structure or settings for their hardware
     */
    zynqSpiSettings_t spiDev1 =
    {
    	.chipSelectIndex = 1,
    	.writeBitPolarity = 0,
    	.longInstructionWord = 1,
    	.CPHA = 0,
    	.CPOL = 0,
    	.mode = 0,
    	.spiClkFreq_Hz = 25000000
    };
    
    /*
     * Platform Layer settings - this structure is specific to ADI's platform layer code.
     * User should replace with their own structure or settings for their hardware
     * The structure is held in taliseDevice_t below as a void pointer, allowing
     * the customer to pass any information for their specific hardware down to the
     * hardware layer code.
     */
    zynqAdiDev_t talDevHalInfo =
    {
    	.devIndex = 1,
    	.spiSettings = &spiDev1,
    	.spiErrCode = 0,
    	.timerErrCode = 0,
    	.gpioErrCode = 0,
    	.logLevel = ADIHAL_LOG_ALL
    };
    #endif
    /**
     *  TalDevice a structure used by the Talise API to hold the platform hardware
     *  structure information, as well as an internal Talise API state container
     *  (devStateInfo) of runtime information used by the API.
     **/
    taliseDevice_t talDevice =
    {
    #ifdef ADI_ZYNQ_PLATFORM
        /* Void pointer of users platform HAL settings to pass to HAL layer calls
         * Talise API does not use the devHalInfo member */
    	.devHalInfo = &talDevHalInfo,
    #else
    	.devHalInfo = NULL,     /*/** < Insert Customer Platform HAL State Container here>*/
    #endif
    	/* devStateInfo is maintained internal to the Talise API, just create the memory */
    	.devStateInfo = {0}
    
    };
    
    taliseInit_t talInit =
    {
    	/* SPI settings */
        .spiSettings =
        {
    		.MSBFirst            = 1,  /* 1 = MSBFirst, 0 = LSBFirst */
    		.enSpiStreaming      = 0,  /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */
    		.autoIncAddrUp       = 1,  /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr=addr-1 */
    		.fourWireMode        = 1,  /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */
    		.cmosPadDrvStrength  = TAL_CMOSPAD_DRV_2X /* Drive strength of CMOS pads when used as outputs (SDIO, SDO, GP_INTERRUPT, GPIO 1, GPIO 0) */
    	},
    	
        /* Tx settings */
        .tx = 
        {
            .txProfile =
            {
                .dacDiv = 1,                        /* The divider used to generate the DAC clock */
                .txFir = 
                {
                    .gain_dB = 6,                        /* filter gain */
                    .numFirCoefs = 40,                    /* number of coefficients in the FIR filter */
                    .coefs = &txFirCoefs[0]
                },
                .txFirInterpolation = 1,                    /* The Tx digital FIR filter interpolation (1,2,4) */
                .thb1Interpolation = 2,                    /* Tx Halfband1 filter interpolation (1,2) */
                .thb2Interpolation = 2,                    /* Tx Halfband2 filter interpolation (1,2)*/
                .thb3Interpolation = 2,                    /* Tx Halfband3 filter interpolation (1,2)*/
                .txInt5Interpolation = 1,                    /* Tx Int5 filter interpolation (1,5) */
                .txInputRate_kHz = 245760,                    /* Primary Signal BW */
                .primarySigBandwidth_Hz = 100000000,    /* The Rx RF passband bandwidth for the profile */
                .rfBandwidth_Hz = 225000000,            /* The Tx RF passband bandwidth for the profile */
                .txDac3dBCorner_kHz = 225000,                /* The DAC filter 3dB corner in kHz */
                .txBbf3dBCorner_kHz = 113000,                /* The BBF 3dB corner in kHz */
                .loopBackAdcProfile = {212, 140, 175, 90, 1280, 699, 1304, 59, 1343, 33, 913, 27, 48, 48, 34, 192, 0, 0, 0, 0, 48, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905}
            },
            .deframerSel = TAL_DEFRAMER_A,                    /* Talise JESD204b deframer config for the Tx data path */
            .txChannels = TAL_TX1TX2,                            /* The desired Tx channels to enable during initialization */
            .txAttenStepSize = TAL_TXATTEN_0P05_DB,            /* Tx Attenuation step size */
            .tx1Atten_mdB = 0,                            /* Initial Tx1 Attenuation */
            .tx2Atten_mdB = 0,                            /* Initial Tx2 Attenuation */
            .disTxDataIfPllUnlock = TAL_TXDIS_TX_RAMP_DOWN_TO_ZERO    /* Options to disable the transmit data when the RFPLL unlocks. */
        },
    
    
        /* ObsRx settings */
        .obsRx = 
        {
            .orxProfile =
            {
                .rxFir = 
                {
                    .gain_dB = 6,                /* filter gain */
                    .numFirCoefs = 24,            /* number of coefficients in the FIR filter */
                    .coefs = &obsrxFirCoefs[0]
                },
                .rxFirDecimation = 1,            /* Rx FIR decimation (1,2,4) */
                .rxDec5Decimation = 4,            /* Decimation of Dec5 or Dec4 filter (5,4) */
                .rhb1Decimation = 2,            /* RX Half band 1 decimation (1 or 2) */
                .orxOutputRate_kHz = 245760,            /* Rx IQ data rate in kHz */
                .rfBandwidth_Hz = 200000000,    /* The Rx RF passband bandwidth for the profile */
                .rxBbf3dBCorner_kHz = 225000,    /* Rx BBF 3dB corner in kHz */
                .orxLowPassAdcProfile = {185, 141, 172, 90, 1280, 942, 1332, 90, 1368, 46, 1016, 19, 48, 48, 37, 208, 0, 0, 0, 0, 52, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},
                .orxBandPassAdcProfile = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
                .orxDdcMode = TAL_ORXDDC_DISABLED,   /* ORx DDC mode */
                .orxMergeFilter  = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
            },
            .orxGainCtrl = 
            {
                .gainMode = TAL_MGC,
                .orx1GainIndex = 255,
                .orx2GainIndex = 255,
                .orx1MaxGainIndex = 255,
                .orx1MinGainIndex = 195,
                .orx2MaxGainIndex = 255,
                .orx2MinGainIndex = 195
            },
            .framerSel = TAL_FRAMER_B,                /* ObsRx JESD204b framer configuration */
            .obsRxChannelsEnable = TAL_ORX1,        /* The desired ObsRx Channels to enable during initialization */
            .obsRxLoSource = TAL_OBSLO_RF_PLL                /* The ORx mixers can use the TX_PLL */
        },
    
        /* Digital Clock Settings */
        .clocks = 
        {
            .deviceClock_kHz = 122880,            /* CLKPLL and device reference clock frequency in kHz */
            .clkPllVcoFreq_kHz = 9830400,        /* CLKPLL VCO frequency in kHz */
            .clkPllHsDiv = TAL_HSDIV_2P5,            /* CLKPLL high speed clock divider */
            .rfPllUseExternalLo = 0,                /* 1= Use external LO for RF PLL, 0 = use internal LO generation for RF PLL */
            .rfPllPhaseSyncMode = TAL_RFPLLMCS_NOSYNC                /* RFPLL MCS (Phase sync) mode */
        },
    
        /* JESD204B settings */
        .jesd204Settings = 
        {
            /* Framer B settings */
            .framerB = 
            {
                .bankId = 0,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
                .deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
                .lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
                .M = 2,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
                .K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
                .F = 2,                            /* F (number of bytes per frame) */
                .Np = 16,                            /* Np (converter sample resolution) */
                .scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
                .externalSysref = 1,            /* 0=use internal SYSREF, 1= use external SYSREF */
                .serializerLanesEnabled = 0x0C,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
                .serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
                .lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
                .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
                .syncbInSelect = 1,                /* syncbInSelect; */
                .overSample = 0,                    /* 1=overSample, 0=bitRepeat */
                .syncbInLvdsMode = 1,
                .syncbInLvdsPnInvert = 0,
                .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
            },
            /* Framer A settings */
            .framerA = 
            {
                .bankId = 0,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
                .deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
                .lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
                .M = 2,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
                .K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
                .F = 0,                            /* F (number of bytes per frame) */
                .Np = 16,                            /* Np (converter sample resolution) */
                .scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
                .externalSysref = 1,            /* 0=use internal SYSREF, 1= use external SYSREF */
                .serializerLanesEnabled = 0x0C,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
                .serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
                .lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
                .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
                .syncbInSelect = 1,                /* syncbInSelect; */
                .overSample = 0,                    /* 1=overSample, 0=bitRepeat */
                .syncbInLvdsMode = 1,
                .syncbInLvdsPnInvert = 0,
                .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
            },
            /* Deframer A settings */
            .deframerA = 
            {
                .bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
                .deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
                .lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
                .M = 4,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
                .K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
                .scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
                .externalSysref = 1,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
                .deserializerLanesEnabled = 0x09,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
                .deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
                .lmfcOffset = 17,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
                .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
                .syncbOutSelect = 0,                /* SYNCBOUT0/1 select */
                .Np = 16,                /* Np (converter sample resolution) */
                .syncbOutLvdsMode = 1,
                .syncbOutLvdsPnInvert = 0,
                .syncbOutCmosSlewRate = 0,
                .syncbOutCmosDriveLevel = 0,
                .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
            },
            /* Deframer B settings */
            .deframerB = 
            {
                .bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
                .deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
                .lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
                .M = 0,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
                .K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
                .scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
                .externalSysref = 1,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
                .deserializerLanesEnabled = 0x00,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
                .deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
                .lmfcOffset = 0,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
                .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
                .syncbOutSelect = 1,                /* SYNCBOUT0/1 select */
                .Np = 16,                /* Np (converter sample resolution) */
                .syncbOutLvdsMode = 1,
                .syncbOutLvdsPnInvert = 0,
                .syncbOutCmosSlewRate = 0,
                .syncbOutCmosDriveLevel = 0,
                .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
            },
            .serAmplitude = 15,                    /* Serializer amplitude setting. Default = 15. Range is 0..15 */
            .serPreEmphasis = 1,                /* Serializer pre-emphasis setting. Default = 1 Range is 0..4 */
            .serInvertLanePolarity = 0,            /* Serializer Lane PN inversion select. Default = 0. Where, bit[0] = 1 will invert lane [0], bit[1] = 1 will invert lane 1, etc. */
            .desInvertLanePolarity = 0,            /* Deserializer Lane PN inversion select.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc */
            .desEqSetting = 1,                    /* Deserializer Equalizer setting. Applied to all deserializer lanes. Range is 0..4 */
            .sysrefLvdsMode = 1,                /* Use LVDS inputs on Talise for SYSREF */
            .sysrefLvdsPnInvert = 0              /*0= Do not PN invert SYSREF */
        }
    };
    
    //Only needs to be called if user wants to setup AGC parameters
    static taliseAgcCfg_t rxAgcCtrl =
    {
        4,
        255,
        195,
        255,
        195,
        30720,  /* AGC gain update time in us (125us-250us - based on IQ data rate - set for 125us @ 245.76 Mhz) */
        10,
        10,
        16,
        0,
        1,
        0,
        0,
        0,
        1,
        31,
        246,
        4,
        1,          /*!<1- bit field to enable the multiple time constants in AGC loop for fast attack and fast recovery to max gain. */
        /* agcPower */
        {
            1,      /*!<1-bit field, enables the Rx power measurement block. */
            1,      /*!<1-bit field, allows using Rx PFIR for power measurement. */
            0,      /*!<1-bit field, allows to use the output of the second digital offset block in the Rx datapath for power measurement. */
            9,      /*!<AGC power measurement detect lower 0 threshold. Default = -12dBFS == 5, 7-bit register value where max = 0x7F, min = 0x00 */
            2,      /*!<AGC power measurement detect lower 1 threshold. Default = (offset) 4dB == 0, 4-bit register value where  max = 0xF, min = 0x00 */
            4,      /*!<AGC power measurement detect lower 0 recovery gain step. Default = 2dB - based on gain table step  size, 5-bit register value where max = 0x1F, min = 0x00 */
            4,      /*!<AGC power measurement detect lower 1 recovery gain step. Default = 4dB - based on gain table step size, 5-bit register value where max = 0x1F, min = 0x00 */
            5,      /*!< power measurement duration used by the decimated power block. Default = 0x05, 5-bit register value where max = 0x1F, min = 0x00 */
            5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
            1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
            5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
            1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
            2,      /*!<Default value should be 2*/
            0,
            0
        },
        /* agcPeak */
        {
            205,        /*!<1st update interval for the multiple time constant in AGC loop mode, Default:205. */
            2,          /*!<sets the 2nd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of  agcUnderRangeLowInterval  , Default: 4 */
            4,          /*!<sets the 3rd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of agcUnderRangeMidInterval and agcUnderRangeLowInterval, Default: 4 */
            39,         /*!<AGC APD high threshold. Default=0x1F, 6-bit register value where max=0x3F, min =0x00 */
            49,         /*!<AGC APD peak detect high threshold. default = 0x1F, 6-bit register value where max = 0x3F, min = 0x00.  Set to 3dB below apdHighThresh */
            23,         /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max =0x3F, min = 0x00 */
            19,         /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max = 0x3F, min = 0x00 . Set to 3dB below apdLowThresh  */
            6,          /*!<AGC APD peak detect upper threshold count. Default = 0x06 8-bit register value where max = 0xFF, min = 0x20  */
            3,          /*!<AGC APD peak detect lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00  */
            4,          /*!<AGC APD peak detect attack gain step. Default = 2dB step - based on gain table step size, 5-bit register  value, where max = 0x1F, min = 0x00  */
            2,          /*!<AGC APD gain index step size. Recommended to be same as hb2GainStepRecovery. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00  */
            1,          /*!<1-bit field, enables or disables the HB2 overload detector.  */
            1,          /*!<3-bit field. Sets the window of clock cycles (at the HB2 output rate) to meet the overload count. */
            1,          /*!<4-bit field. Sets the number of actual overloads required to trigger the overload signal.  */
            181,        /*!<AGC decimator output high threshold. Default = 0xB5, 8-bit register value where max = 0xFF, min = 0x00 */
            45,         /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
            90,         /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
            128,        /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
            6,          /*!<AGC HB2 output upper threshold count. Default = 0x06, 8-bit register value where max = 0xFF, min =  0x20 */
            3,          /*!<AGC HB2 output lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00 */
            2,          /*!<AGC decimator gain index step size. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00 */
            4,          /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 0 triggers a programmable number  of times. Default = 0x08, 5-bit register value where max = 0x1F, min = 0x00 */
            8,          /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 1 triggers a programmable number of times. Default = 0x04, 5-bit register value where max = 0x1F, min = 0x00 */
            4,          /*!<AGC decimator output attack gain step. Default = 2dB step - based on gain table step size, 5-bit register value, where max = 0x1F, min = 0x00 */
            1,
            0,
            0
        }
    };

    Regarding creation of No-os project, I have copied all the files specified in readme under src folder and build using SDK gui. And when I generate new profiles,i copy talise_config.c on to the src folder and rebuild. This way it was all working fine with ADI ref design with 4 lanes.

    Thanks and Regards

    Deepika

  • Hello Deepika,

    I managed to fix the link status on the TX lanes, the only thing I changed was in NO-OS in the /projects/adrv9009/src/app/app_jesd.c script I changed the octets_per_frame to 4, as you can see in the picture.

     I used your talise_config.c profile with Tx_sample rate =122.88 MHz and this is the log that I received.

    Best regards!

    Filip.

  • Thanks so much Filip for trying out my requirement at your end.

    I will confirm this on my setup and let you know.

    Regards

    Deepika

  • Hello Fillip,

    Just FYI, i was able to push sin_lut samples successfully on no-os using 2 lanes.

    Regards

    Deepika

  •   ,

    I have exactly the same problem. I would like to set TX path to 64bits instead of 128bits....

    Well, I could get things running, the only problem is that the jesd204 link status gets stuck at CGS state and something I noticed is that when tx jesd204 is at data state, the Sync info is de-asserted.

    Could you please tell how you managed to get out of the CGS state ? I have tried what  suggested but nothing changed.

    Thanks,