FPGA simulation

Hello:

I downloaded the AD9434 project that you officially provided. Thank you for providing such a reference design. I extracted the AD9434 source-synchronous interface code separately from the project. I encountered a problem when I used the built-in simulation tool of vivado when the logic function was simulated.The errors prompted by the simulation are as follows:

ERROR: [VRFC 10-2987] 'dma_fifo' is not compiled in library 'work' [C:/Users/Administrator/Desktop/verilog/axi_streaming_dma_tx_fifo.vhd:40]

ERROR: [VRFC 10-3782] unit 'axi_streaming_dma_tx_fifo' ignored due to previous errors [C:/Users/Administrator/Desktop/verilog/axi_streaming_dma_tx_fifo.vhd:42]

Frank