| SLA Status | Assignee | Support Status |
|---|---|---|
| SLA Closed. | Open | |
We're experiencing an issue trying to synchronize multiple JESD-204B ADC boards. Each board has several JESD-204B converters (AD6676) connected to a Xilinx Zynq FPGA with axi_jesd204_rx IPcore.
There's a clock distribution network that feeds each board with phase-synchronized clock references and sysref. Then, each board has its own clock generator/distributor with JESD204B support which is used to clock the converters and send sysref to the FPGA and the converters.
Our boards start from an internal clock reference. They boot independently, configure the clocks and bring up the converters, sending a sysref clock pulse to the FPGA which starts the receiver's state machine. This all happens before Linux boots, so that the JESD interface is up and running and the drivers probe correctly.
Then, once everything is up, the master clock board boots, configures and aligns its clocks, and notifies the ADC boards which setup their clock generators to take the reference clock from the master clock board and accept alignment pulses. An alignment pulse is sent from the master board and all the clocks get phase aligned among all boards (we verified).
Then we set the clock distributors to distribute sysref to the converter/FPGA, we arm the converters to accept sysref and we finally send two sysref pulses from the master board, which arrive synchronously to the rest of the boards.
The intra-board alignment (among converters connected to the same FPGA) is always perfect. We check by sending a pulsed RF signal and doing a synchronous capture (we have also a capture trigger signal distributed synchronously to all boards for capture synchronization). The "rising" and "falling" edges of the digitized pulsed signal start misaligned but the sysref synchronization pulses bring them together 100% of the times.
Inter-board (between different boards with different FPGAs) things are different, however, and we almost never get a perfect synchronization. There's a delay between the "rising" and "falling" edges of the digitized signal (i.e. several clock cycles of sampling point delay) which remains constant between power-ups but changes every time we restart the boards and synchronize them. Sometimes the delay is 0 and all boards get synced, but this is normally not the case.
So, to recap:
Step 1: Board startup + clock config + clock alignment => synchronous (triggered) capture of a pulsed RF signal =>digitized signal edges all over the place (as expected)
Step 2: Arm ADCs to accept sysref + send sysref pulses => ADCs accept sysref pulses => ADCs within a board get perfectly synchronized, but boards are not synchronized between them.
We have tested and it looks like axi_jesd204_rx is ignoring sysref. We are sure that sysref gets there and it gets there synchronously, but it doesn't seem to do anything.
To our understanding, receiving a Sysref pulse outside the LMFC window should align LMFC's and trigger a link resynchronization (i.e. SYNC goes low and the converters send alignment sequence and such). However, sending sysrefs to the FPGA never triggers a link resynhronization event (SYNC remains high), so it's like it's ignored. SYSREF status register (0x108) always reads 0x01. The only way to resynchronize the link is to reset the ipcore, but then it brings itself back immediately and still reports having captured a SYSREF, even when we haven't sent any sysref pulse.
Any clue on what might be happening? Do we need to clear register 0x108 to "arm" the ipcore to accept a new sysref (like we do with AD6676)?
