EVAL-ADAQ400X HDL low sampling rate

Hi,

Could you please tell me the exact CS period that you measured with the scope? Could you measure the SCLK period as well?

After that, please edit this line in the script

https://github.com/analogdevicesinc/hdl/blob/7ed4955661271deec149901d2cc84272e2dfafb1/projects/ad40xx_fmc/common/ad40xx_bd.tcl#L52

to this: ad_ip_parameter trigger_gen CONFIG.PULSE_PERIOD 93

then build and see if anything changes.

it things look the same try changing the line to about half. and by this i mean depending on the CS period that you measured with the scope it should be 93*558/(measured period)

~Sergiu

Hello sarpadi,

I tried your suggestions, but there's no improvement.

I first hard-coded CONFIG.PULSE_PERIOD to 93 as you suggested, but the resulting CS period and sampling rate are same as before.

Next, I tried halving it as you suggested (changing the line to about half), so I set CONFIG.PULSE_PERIOD to 46 in the TCL script.  Is this way correct?  Anyway, after compiling the hdl with this change and rebuilding petalinux for the images, the CS period and sampling rate are still the same as before.

I suspect that your new hardware was not copied to the sd card correctly, or was overwritten somehow since it is impossible for it to behave the same way.

besides that, i suspect that the zynq 166MHz clock output is somehow changed to 83MHz since both the CS and the SCLK seem to move at half their speed. Please try to build the HDL from this branch

https://github.com/sarpadi/hdl/tree/debug_adaq40xx

I have added an ip which will tell us the actual value for the frequency. You will need to start the zedboard with this HDL and use memtool to read its registers

https://manpages.ubuntu.com/manpages/xenial/man8/memtool.8.html

the address that we are interested in is 0x41330040

once the value is read this formula must be applied to it to get the frequency

F = (regval * 100000000 + 0x7FFF) >> 16)

F should be 166

Let me know if there are any questions regarding this procedure.

~Sergiu

Thanks sarpadi.  I'm on the process of trying and testing out your steps.

One question though.  I noticed that the tcl scripts in debug_adaq40xx branch sets Vivado to version 2021.1.  Does it have to be Vivado 2021.1 or will Vivado 2020.2 or 2020.1 be alright to use to build it?  My latest Vivado is 2020.2 and so far the HDL command-line build via make successfully completed.  On the other hand, ADI's latest meta-adi and petalinux is for 2020.1 and I'm worried whether there will be version compatibility issues.  The previous days' builds were done on 2020.1 (after modifying the script that set it to higher Vivado versions).

I'm on my way to test the HDL build done by Vivado 2020.2 with my Zedboard meta-adi Linux.

Hello Sergiu sarpadi,

I tried the hdl branch you've given me, built it with Vivado 2020.2, and used it with meta-adi Petalinux.  Here is the value from the register you've asked me to read, which I read via devmem:

The register value is 0x1AAAB.

When I used this regval to the equation you gave me, (F = (regval * 100000000 + 0x7FFF) >> 16)), F is computed to be 166667175.

Hi Sergiu sarpadi,

Is this new HDL supposed to set my ADAQ400X CS period to ~560ns or 1.8MSPS sampling rate?  I'm still getting the same 900KSPS sampling rate as before.

I'm trying to rebuild everything in the SW including the petalinux part.

this line will tell you the supported Vivado version for that particular commit

github.com/.../adi_project_xilinx.tcl

could you be more specific regarding those tcl scripts?

using a different vivado version should generate a fail with a wrong version warning

you can make the tool ignore that warning and it might build with a different version but it is generally not recommended. we support one version at a time.

our master is currently at 2021.1 so we can upgrade if needed or we can stick to 2020.2, the project will build the same.

this line will tell you the supported Vivado version for that particular commit

github.com/.../adi_project_xilinx.tcl

could you be more specific regarding those tcl scripts?

using a different vivado version should generate a fail with a wrong version warning

you can make the tool ignore that warning and it might build with a different version but it is generally not recommended. we support one version at a time.

our master is currently at 2021.1 so we can upgrade if needed or we can stick to 2020.2, the project will build the same.

Hello sarpadi

During the previous builds from the previous days, I did change these two files to accomodate Vivado 2020.1:

hdl/project/scripts/adi_project_xilinx.tcl

hdl/library/scripts/adi_ip_xilinx.tcl

For the latest HDL build, the one you just shared (https://github.com/sarpadi/hdl/tree/debug_adaq40xx), I didn't change anything there and built it as it is.  I used Vivado 2020.2 during its first and only build.  2020.2 seems to work with it (unlike 2020.1) so I'm sticking with 2020.2 for now.  The HDL built by 2020.2 also didn't encounter compatibility issues with my ADI petalinux, so another reason to stick with 2020.2.