Post Go back to editing

EVAL-ADAQ400X HDL low sampling rate


I'm working on a new project now involving ADAQ4003 and Zedboard.  Compared to a previous thread, I decided to do everything and not rely on other personnel here in my company.  I posted this new question as I think my concern is more on the HDL side than a Linux driver one.

I'm using the EVAL-ADAQ4003 board with Zedboard and petalinux meta-adi 2020.1, as well as very recent ADI HDL checkout (hash ID 1fe0d5f8e00b119a5a389213cf05e9db4646c86a) for ad400x, I think the project name is ad40xx_fmc.  I think the default settings of this HDL project is for AD4020 eval board (which I worked with before very recently).  The HDL project has a constraint file for ADAQ400X which connects the board to a PMOD connector JA1, not FMC.  So I made the following change to the project's system_bd.tcl and system_project.tcl files:

## Please select which eval board do you want to use
##    1 - EVAL-AD40XX-FMCZ
##    0 - EVAL-ADAQ400x
set AD40XX_ADAQ400X_N [get_env_param AD40XX_ADAQ400X_N 0]

# specify ADC resolution -- supported resolutions 16/18/20 bits
set ADC_RESOLUTION [get_env_param ADC_RESOLUTION 18]

I modified the default parameters in the tcl file and built it with the "make" command in the command-line (not through Vivado IDE).  I also set the compatible string to "ad4003" in the device tree in Linux.

Overall, it works - Linux can get ADC values from the HDL and ADC, and it also works with libiio.  However, the actual sampling rate is just around ~900000 samples per second.  I didn't modify the sampling_rate parameter in the TCL files so I expected it to be 1800000 samples per second but it's just 900000 (I'm measuring it using oscilloscope).  Whereas when the project was left in its default state to support AD4020 eval board, I've verified that indeed actual sampling rate is ~1800000 per second (sampling period is ~562ns) so the default project is okay.

There must be something I'm missing here.  I'm not very experienced in HDL so I'm very reliant on ADI user guides or this forum.

Added hash of adi-hdl git checkout branch for identification
[edited by: ubermensch at 8:07 AM (GMT -4) on 24 Sep 2021]
Parents Reply Children
  • Hello Sergiu @sarpadi,

    As you inquired, here are my measured CS period and SCLK.

    CS period is around 1.13us, so sampling rate is around ~900KSPS.

    SCLK period is around 24 ns.

    Let me know what do you think of it.

    I'm on the process of executing your suggested change at ad40xx_bd.tcl.  I will check and get back here once I have a result.

  • Hello ,

    I tried your suggestions, but there's no improvement.

    I first hard-coded CONFIG.PULSE_PERIOD to 93 as you suggested, but the resulting CS period and sampling rate are same as before.

    Next, I tried halving it as you suggested (changing the line to about half), so I set CONFIG.PULSE_PERIOD to 46 in the TCL script.  Is this way correct?  Anyway, after compiling the hdl with this change and rebuilding petalinux for the images, the CS period and sampling rate are still the same as before.

  • I suspect that your new hardware was not copied to the sd card correctly, or was overwritten somehow since it is impossible for it to behave the same way.

    besides that, i suspect that the zynq 166MHz clock output is somehow changed to 83MHz since both the CS and the SCLK seem to move at half their speed. Please try to build the HDL from this branch

    I have added an ip which will tell us the actual value for the frequency. You will need to start the zedboard with this HDL and use memtool to read its registers

    the address that we are interested in is 0x41330040

    once the value is read this formula must be applied to it to get the frequency

    F = (regval * 100000000 + 0x7FFF) >> 16)

    F should be 166

    Let me know if there are any questions regarding this procedure.


  • Thanks .  I'm on the process of trying and testing out your steps.

    One question though.  I noticed that the tcl scripts in debug_adaq40xx branch sets Vivado to version 2021.1.  Does it have to be Vivado 2021.1 or will Vivado 2020.2 or 2020.1 be alright to use to build it?  My latest Vivado is 2020.2 and so far the HDL command-line build via make successfully completed.  On the other hand, ADI's latest meta-adi and petalinux is for 2020.1 and I'm worried whether there will be version compatibility issues.  The previous days' builds were done on 2020.1 (after modifying the script that set it to higher Vivado versions).

    I'm on my way to test the HDL build done by Vivado 2020.2 with my Zedboard meta-adi Linux.

  • Hello Sergiu ,

    I tried the hdl branch you've given me, built it with Vivado 2020.2, and used it with meta-adi Petalinux.  Here is the value from the register you've asked me to read, which I read via devmem:

    The register value is 0x1AAAB.

    When I used this regval to the equation you gave me, (F = (regval * 100000000 + 0x7FFF) >> 16)), F is computed to be 166667175.

  • Hi Sergiu ,

    Is this new HDL supposed to set my ADAQ400X CS period to ~560ns or 1.8MSPS sampling rate?  I'm still getting the same 900KSPS sampling rate as before.

    I'm trying to rebuild everything in the SW including the petalinux part.

  • this line will tell you the supported Vivado version for that particular commit

    could you be more specific regarding those tcl scripts?

    using a different vivado version should generate a fail with a wrong version warning

    you can make the tool ignore that warning and it might build with a different version but it is generally not recommended. we support one version at a time.

    our master is currently at 2021.1 so we can upgrade if needed or we can stick to 2020.2, the project will build the same.

  • Hello

    During the previous builds from the previous days, I did change these two files to accomodate Vivado 2020.1:



    For the latest HDL build, the one you just shared (, I didn't change anything there and built it as it is.  I used Vivado 2020.2 during its first and only build.  2020.2 seems to work with it (unlike 2020.1) so I'm sticking with 2020.2 for now.  The HDL built by 2020.2 also didn't encounter compatibility issues with my ADI petalinux, so another reason to stick with 2020.2.

  • Hello ,

    I've already created a new meta-adi petalinux project so I can rebuild Linux from scratch.  It uses the latest HDL from your git branch you just sent me.  Despite all these, sampling rate is still 900KSPS.

    The register value from 0x41330040 is still 0x0001AAAB, so calculating F still yields 166667175.

  • Hello Sergiu

    Any new updates in here or new ideas that I can try?  Still stuck in this.  So far I've tried looking at the clk_div and the SPI engine instruction (set by the SW) for clues and discrepancies between ADAQ4003 and AD4020.  However, both of them use almost the same instructions and values (except the data width of course).  It seems this was a wrong angle to search as the clk_div only concerns the SCLK when the sampling rate problem encompass the CS period as well.

    I'm trying to learn using ILA as well as the no-OS FW in Zedboard.  Have you tried out your git branch into no-OS?  Also, any internal signals in spi-engine that I can tap for debugging or gaining insight on what determines sampling rate?