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AD9467 FMC voltage level

Thread Summary

The user is experiencing high gain in the AD9467 FMC + FPGA reference design, where 1Vp-p equals 100 and 0.5Vp-p equals 50. The final answer suggests using the amplifier at J102 to adjust the gain, requiring the connection/disconnection of the default to amp path. The system needs to operate with low voltages between 2 to 20mV.
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Hi,
I have an issue with using the AD9467 FMC + FPGA reference design seems to be 1v=100 and 0.5v=50. Figure 1 below shows the signal that captures using 1Vp-p with 25 kHz that mean its multiply by 100 times. My system has to work with a low voltage between 2 to 20mV.
How do I change the gain? Please help.

Figure 1: sinewave signal 1vp-p, 25 KHz