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AD9467 FMC + FPGA reference design, change the gain, change the voltage level

Thread Summary

The user is experiencing an issue with the AD9467 FMC + FPGA reference design where the voltage gain seems to be 1V=100 and 0.5V=50, making it unsuitable for their low-voltage signals (2 to 20mV). The final answer suggests continuing the discussion on the provided forum link for further assistance. No specific gain adjustment solution is provided in the final answer.
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Hi,
I have an issue with using the AD9467 FMC + FPGA reference design seems to be 1v=100 and 0.5v=50. Figure 1 below shows the signal that captures using 1Vp-p with 25 kHz that mean its multiply by 100 times. My system has to work with a low voltage between 2 to 20mV.
How do I change the gain? Please help.

  Figure 1: sinewave signal 1vp-p, 25 KHz

Figure 1: sinewave signal 1vp-p, 25 KHz