AD9467 FMC, FPGA , ZEDBOARD

Hi,

I can't see the images/figures you mentioned.
Have you provided the external clock( or sampling clock) https://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467?

Andrei

DOCX

Hi Dear, I had uploaded all the details and pictures to this document. yes, I used a 250MSPS clock from AWG to the ADC. However, the capturing was different on the oscilloscope as shown in the document.

Thanks Andrei for the reply. 
I'm not sure which memory you're referring to. 

In the reference design, the ADC block connects to AXI bus and then  moved to main memory with DMA. 
Say that we have 4 samples, each of them are 16-bit and the DMA target base address is 0x80_0000, what we think the memory arrangement is: 
0x80_0000: sample1(16-bit)
0x80_0002: sample2(16-bit)
0x80_0004: sample3(16-bit)
0x80_0006: sample4(16-bit)

From your "the memory is 32-bit aligned, are you saying the arrangement is below? 
0x80_0000:  0x0000 & sample1(16-bit)
0x80_0004: 0x0000 & sample2(16-bit)
0x80_0008: 0x0000 & sample3(16-bit)
0x80_000C: 0x0000 & sample4(16-bit)
 
iwan

Hi,

Your setup is ok, I presumed the dma driver accepts number of samples instead of bytes. Sorry about that.
The arrangement is like you described it. This is how I look at it:
0x80_0000:  {sample2(16-bit),  sample1(16-bit)}
0x80_0004:  {sample4(16-bit),  sample3(16-bit)}
0x80_0008: ...
Same thing.

I made a setup(as you described), to determine if there is a bug, I did not found one.

Attached you can find the data I captured. capture_ch1.txt

In my UART console I get "ad9467_core: Successfully initialized (250000000 Hz)" do you get half?

What release are you using and have you made other changes?

I would suggest, testing with linux also. Use IIO-Oscilloscope to capture data, set it to FFT and use markers.

Andrei

Hi Andrei, 

Thanks for your reply. We actually only get "ad9467_core: Successfully initialized (125013732 Hz)".

So we have problem here. We supply 250MHz to the input clock connector and we expect that the ADC will use that clock. It seems that there's an internal divider(?) or the clock source completely from something else?

Best regards, 

Iwan

Hi Iwan,

Can you check the schematic and the components on your board.
You want to check that the external clock path is connected to the ADC device, as expected, or it is routed through AD9517(see the description on wiki)
Are C209 and C210 populated on your board?

Andrei

Hi Andrei, 
We found the issue is in our local setup. We have made some basic mistake in our signal generator and measurements.

Really thank you for your response. They're really helpful.

Hello brother, can you inform me about your Vivado and the release version you used for this process...? 

By the way, I use Vivado /SDK 2019.1 and release version No-OS (2019_R2). 

Hi Abbas047 ,

I you don't find a solutions on old EZ threes, please open a new one and describe your issue.

Andrei

 Hi Dear. Abbas

yes, I used Vivado /SDK 2019.1. it working with no issues.

Abdulwahhab

Hi Abdulwahhab ,

Thank you brother, now it works fine with me in Vivado/ Vitis 2021.2.

Abbas Ali
FPGA Engineer 

Hi Dear. Brother Abbas Ali

That's great and sorry for the late replay.

Abdulwahhab Essa
FPGA Engineer

Hi Dear. Brother Abbas Ali

That's great and sorry for the late replay.

Abdulwahhab Essa
FPGA Engineer