AD9467 FMC, FPGA , ZEDBOARD

Hi,

I can't see the images/figures you mentioned.
Have you provided the external clock( or sampling clock) https://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467?

Andrei

DOCX

Hi Dear, I had uploaded all the details and pictures to this document. yes, I used a 250MSPS clock from AWG to the ADC. However, the capturing was different on the oscilloscope as shown in the document.

I guess you mean periods when you say waveforms.
At the rate difference between your signal and the sampling rate you will get a period of the sine in 10000 samples, and you are capturing 12500. Nothing wrong here.

If you want to compare with your Oscilloscope calculate the total number of samples you get for the sampling frequency of the oscilloscope and the number of samples per division.

Andrei

Hi, 
I working with Abdul in this project and the issue that the AD9467 FMC + FPGA reference design seems to sample the data at 125MS/s even though the sampling frequency is 250MHz.

The way we confirm it: 
1. We check the sampling frequency is 250MHz by connecting it to scope. 
2. we generate 25kHz sinusoidal signal and then sample it using AD9467 + FPGA. We do DMA 12500 samples by executing axi_dmac_transfer(ad9467_dmac, BASE_ADDR, 12500 * 2); // *2 because 1 sample = 2byte
3. We read the result and store it to computer.
4. The expectation is at 250MS/s sampling rate and 12500 samples, we will see 50us of total sampling time. With 25kHz sinusoidal input (40us period), we will see about 1.25 of sinusoidal signal. 

5. What we observe when we plot the result in Excel. We see 2.5 of sinusoidal signal. This indicate that the sampling rate is only 125MS/s. 
6. We double check our 25kHz input and the sampling clock to the oscilloscope, and it's correct.

Can anyone confirm that this is not the expected behavior?
I'm thinking if there is any configuration that we might need to change, perhaps the width of the bus in the reference design, etc? Please help. 
 

the issue that the AD9467 FMC + FPGA reference design seems to sample the data at 125MS/s even though the sampling frequency is 250MHz.

The way we confirm it: 
1. We check the sampling frequency is 250MHz by connecting it to scope. 
2. we generate 25kHz sinusoidal signal and then sample it using AD9467 + FPGA. We do DMA 12500 samples by executing axi_dmac_transfer(ad9467_dmac, BASE_ADDR, 12500 * 2); // *2 because 1 sample = 2byte
3. We read the result and store it to computer.
4. The expectation is at 250MS/s sampling rate and 12500 samples, we will see 50us of total sampling time. With 25kHz sinusoidal input (40us period), we will see about 1.25 of sinusoidal signal. 

5. What we observe when we plot the result in Excel. We see 2.5 of sinusoidal signal. This indicate that the sampling rate is only 125MS/s. 
6. We double check our 25kHz input and the sampling clock to the oscilloscope, and it's correct.

Can anyone confirm that this is not the expected behavior?
I'm thinking if there is any configuration that we might need to change, perhaps the width of the bus in the reference design, etc? Please help. 

Hi,

Sorry for the delayed reply.
The memory is word(32 bit) aligned not byte aligned. So you are capturing double required the samples.

Andrei

Thanks Andrei for the reply. 
I'm not sure which memory you're referring to. 

In the reference design, the ADC block connects to AXI bus and then  moved to main memory with DMA. 
Say that we have 4 samples, each of them are 16-bit and the DMA target base address is 0x80_0000, what we think the memory arrangement is: 
0x80_0000: sample1(16-bit)
0x80_0002: sample2(16-bit)
0x80_0004: sample3(16-bit)
0x80_0006: sample4(16-bit)

From your "the memory is 32-bit aligned, are you saying the arrangement is below? 
0x80_0000:  0x0000 & sample1(16-bit)
0x80_0004: 0x0000 & sample2(16-bit)
0x80_0008: 0x0000 & sample3(16-bit)
0x80_000C: 0x0000 & sample4(16-bit)
 
iwan

Thanks Andrei for the reply. 
I'm not sure which memory you're referring to. 

In the reference design, the ADC block connects to AXI bus and then  moved to main memory with DMA. 
Say that we have 4 samples, each of them are 16-bit and the DMA target base address is 0x80_0000, what we think the memory arrangement is: 
0x80_0000: sample1(16-bit)
0x80_0002: sample2(16-bit)
0x80_0004: sample3(16-bit)
0x80_0006: sample4(16-bit)

From your "the memory is 32-bit aligned, are you saying the arrangement is below? 
0x80_0000:  0x0000 & sample1(16-bit)
0x80_0004: 0x0000 & sample2(16-bit)
0x80_0008: 0x0000 & sample3(16-bit)
0x80_000C: 0x0000 & sample4(16-bit)
 
iwan

Hi,

Your setup is ok, I presumed the dma driver accepts number of samples instead of bytes. Sorry about that.
The arrangement is like you described it. This is how I look at it:
0x80_0000:  {sample2(16-bit),  sample1(16-bit)}
0x80_0004:  {sample4(16-bit),  sample3(16-bit)}
0x80_0008: ...
Same thing.

I made a setup(as you described), to determine if there is a bug, I did not found one.

Attached you can find the data I captured. capture_ch1.txt

In my UART console I get "ad9467_core: Successfully initialized (250000000 Hz)" do you get half?

What release are you using and have you made other changes?

I would suggest, testing with linux also. Use IIO-Oscilloscope to capture data, set it to FFT and use markers.

Andrei

Hi Andrei, 

Thanks for your reply. We actually only get "ad9467_core: Successfully initialized (125013732 Hz)".

So we have problem here. We supply 250MHz to the input clock connector and we expect that the ADC will use that clock. It seems that there's an internal divider(?) or the clock source completely from something else?

Best regards, 

Iwan

Hi Iwan,

Can you check the schematic and the components on your board.
You want to check that the external clock path is connected to the ADC device, as expected, or it is routed through AD9517(see the description on wiki)
Are C209 and C210 populated on your board?

Andrei

Hi Andrei, 
We found the issue is in our local setup. We have made some basic mistake in our signal generator and measurements.

Really thank you for your response. They're really helpful.