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AD9467 FMC, FPGA , ZEDBOARD

Hi,
I am new to this forum and I just purchased AD9467 FMC card and connect to my Xilinx Zed Board.
I'm trying to build an application and I follow these links:
1- wiki.analog.com/.../build.
2- To run the no-OS application need to:
I had cloned the no-OS repository: github.com/.../no-OS
in addition, I had followed the steps from wiki.analog.com/.../software_setup and add the no-OS project's sources located in no-OS/projects/ad9467/src in the SDK Application Project under the src folder as shown here: wiki.analog.com/.../empty_project.png either by drag and drop or by import sources.
After the system worked as shown in the figure below, I had modified it to capture 12500 simple :
1- To capture the signal by AD9467 FMC card and SoC Board, We used signal generator 1v, 25khz signal
2- I modify the c code from SDK software to capture 12500 simple and send to PC to display.
/* Set the simpling capture per time */
axi_dmac_transfer(ad9467_dmac, (BASE1 + 12500 * 2 * i), 12500 * 2);
3- sampling rate of the ADC is 250MSPS.
/* Set the channel 3 frequency to 250Mhz */
ad9517_frequency(ad9517_device, 3, 250000000);
However, I’m capturing the sine wave signal under the same condition using an oscilloscope and AD9467 FMC card. where the capturing signal was two waveforms in the (oscilloscope figure2_b) and one waveform signal by using AD9467 FMC card.
Please could you help me with capturing the signal under 250MSPS by using AD9467 FMC card and zedboard?

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  • Hi,

    I can't see the images/figures you mentioned.
    Have you provided the external clock( or sampling clock) https://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467?

    Andrei

  • DOCX

    Hi Dear, I had uploaded all the details and pictures to this document. yes, I used a 250MSPS clock from AWG to the ADC. However, the capturing was different on the oscilloscope as shown in the document.

  • I guess you mean periods when you say waveforms.
    At the rate difference between your signal and the sampling rate you will get a period of the sine in 10000 samples, and you are capturing 12500. Nothing wrong here.

    If you want to compare with your Oscilloscope calculate the total number of samples you get for the sampling frequency of the oscilloscope and the number of samples per division.

    Andrei

  • Hi, 
    I working with Abdul in this project and the issue that the AD9467 FMC + FPGA reference design seems to sample the data at 125MS/s even though the sampling frequency is 250MHz.

    The way we confirm it: 
    1. We check the sampling frequency is 250MHz by connecting it to scope. 
    2. we generate 25kHz sinusoidal signal and then sample it using AD9467 + FPGA. We do DMA 12500 samples by executing axi_dmac_transfer(ad9467_dmac, BASE_ADDR, 12500 * 2); // *2 because 1 sample = 2byte
    3. We read the result and store it to computer.

    4. The expectation is at 250MS/s sampling rate and 12500 samples, we will see 50us of total sampling time. With 25kHz sinusoidal input (40us period), we will see about 1.25 of sinusoidal signal.
     

    5. What we observe when we plot the result in Excel. We see 2.5 of sinusoidal signal. This indicate that the sampling rate is only 125MS/s. 
    6. We double check our 25kHz input and the sampling clock to the oscilloscope, and it's correct.

    Can anyone confirm that this is not the expected behavior?
    I'm thinking if there is any configuration that we might need to change, perhaps the width of the bus in the reference design, etc? Please help. 
     

      

Reply
  • Hi, 
    I working with Abdul in this project and the issue that the AD9467 FMC + FPGA reference design seems to sample the data at 125MS/s even though the sampling frequency is 250MHz.

    The way we confirm it: 
    1. We check the sampling frequency is 250MHz by connecting it to scope. 
    2. we generate 25kHz sinusoidal signal and then sample it using AD9467 + FPGA. We do DMA 12500 samples by executing axi_dmac_transfer(ad9467_dmac, BASE_ADDR, 12500 * 2); // *2 because 1 sample = 2byte
    3. We read the result and store it to computer.

    4. The expectation is at 250MS/s sampling rate and 12500 samples, we will see 50us of total sampling time. With 25kHz sinusoidal input (40us period), we will see about 1.25 of sinusoidal signal.
     

    5. What we observe when we plot the result in Excel. We see 2.5 of sinusoidal signal. This indicate that the sampling rate is only 125MS/s. 
    6. We double check our 25kHz input and the sampling clock to the oscilloscope, and it's correct.

    Can anyone confirm that this is not the expected behavior?
    I'm thinking if there is any configuration that we might need to change, perhaps the width of the bus in the reference design, etc? Please help. 
     

      

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