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Enable DDC in FMCDAQ2 + kc705


I am using KC705 & FMCDAQ2 combo. I would finally move to ZC706 + FMCDAQ2

I would like enable DDC in AD9680. My preferred configuration is given in ""Table 23. DDC Example Configurations"" Chip decimation ratio is 16 ie no of virtual converters 8.
I have referred to below link.

In case of HDL design, ""you could modify the design to M=8 ""

Does that mean I need to edit projects\daq2\common\daq2_bd.tcl? What are the other parameters to change?

ad_ip_instance util_cpack2 axi_ad9680_cpack { \


ad_ip_instance util_cpack2 axi_ad9680_cpack { \

our requirement is similar to ""Example 2: ADC with DDC Option (Two ADCs Plus Four DDCs)"" in AD9680 data sheet.

As i understand, we may have to reduce no of lanes to 2 from given default 4 lanes in example design to maintain minimum lane rate of >3.125Gbps.

Is there any guidelines to reduce the lane nos in HDL design? Do I need to just edit daq2_bd.tcl?

  • I made the following changes to dac2_bd.tcl

    Changed line to 


    Added new line

    adi_axi_jesd204_rx_create axi_ad9680_jesd $RX_NUM_OF_LANES
    ad_ip_parameter axi_ad9680_jesd/rx CONFIG.DATA_PATH_WIDTH 8

    I was able to build the project. But when I check axi_ad9680_jesd(Attached image) I observed Data path Width as 4. I was expecting that this will change to 8 No sure whether this is correct.

    Attaching 4478.daq2_bd.rar

    In Vivado log file I could see following details

    ### ad_ip_parameter axi_ad9680_jesd/rx CONFIG.DATA_PATH_WIDTH 8
    WARNING: [BD 41-721] Attempt to set value '8' on disabled parameter 'DATA_PATH_WIDTH' of cell '/axi_ad9680_jesd/rx' is ignored

  • I believe that hdl version (hdl_2019_r2) does not support changing following parameter

    ad_ip_parameter axi_ad9083_rx_jesd/rx CONFIG.TPL_DATA_PATH_WIDTH 8

    "hdl/library/jesd204/jesd204_rx/jesd204_rx.v" has only following paramters

    module jesd204_rx #(
    parameter NUM_LANES = 1,
    parameter NUM_LINKS = 1,
    parameter NUM_INPUT_PIPELINE = 1,
    parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
    /* Only 4 is supported at the moment for 8b/10b and 8 for 64b */
    parameter DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4,
    parameter ENABLE_FRAME_ALIGN_CHECK = 1,
    ) (

    I would request you to suggest the branch i need to checkout inorder for changes suggested to take effect.

    Is it possible for me to update jesd204_rx of (hdl_2019_r2) with verion from master branch?

  • Can Expect an update for this request?? I am still stuck at this point.

  • Hello,

    I created two branches on git where I've modified the daq2 hdl and linux project. The modification is not tested on hardware. The hdl part is available here:  and the linux part is available here: . 

    Best Regards,


  • Hello Dan,

    I tried building hdl using Vivado 2020.1

    I encounter the following error while building project.


    Building axi_clkgen library [/cygdrive/d/adi/Analog_Support/hdl/library/axi_clkgen/axi_clkgen_ip.log] ... OK
    Building axi_hdmi_tx library [/cygdrive/d/adi/Analog_Support/hdl/library/axi_hdmi_tx/axi_hdmi_tx_ip.log] ... OK
    Building axi_spdif_tx library [/cygdrive/d/adi/Analog_Support/hdl/library/axi_spdif_tx/axi_spdif_tx_ip.log] ... OK
    Building axi_adcfifo library [/cygdrive/d/adi/Analog_Support/hdl/library/xilinx/axi_adcfifo/axi_adcfifo_ip.log] ... OK
    Building daq2_zc706 project [/cygdrive/d/adi/Analog_Support/hdl/projects/daq2/zc706/daq2_zc706_vivado.log] ... FAILED
    For details see /cygdrive/d/adi/Analog_Support/hdl/projects/daq2/zc706/daq2_zc706_vivado.log

    make: *** [../../scripts/ daq2_zc706.sdk/system_top.hdf] Error 1


    Attaching log file

  • Hello,

    Can you please make a fresh clone of the hdl repository on my fork and switch to daq2_without_ad9144_proj branch and then build the daq2/zc706 project?

    Thank you.

    Best Regards,


  • Hi,

    As of now I do not have zc706 hardware with me. So i tried building for kc705 + fmcdaq2.
    I could build project and boot it on kc705.

    I could observe AD9680 on IIO scope but could not find any waveforms in capture

    In dts file I could not find include for XCVR_REFCLK_DIV1 so edit was follows
    axi_ad9680_adxcvr: axi-ad9680-adxcvr@44a50000 {
    compatible = "adi,axi-adxcvr-1.0";
    reg = <0x44a50000 0x10000>;

    clocks = <&clk0_ad9523 4>;
    clock-names = "conv";

    adi,sys-clk-select = <XCVR_CPLL>;

    adi,out-clk-select = <XCVR_REFCLK>;
    adi,vco-max-khz = <5000000>;

    I am also attaching boot-up print Linux print

    "jesd204: found 0 devices and 0 topologies" which I have not seen in working versions


    xdc file
    top file
    Linux boot-up print


  • I attached ILA to util_adcfifo adc_wr data and adc_wr in ILA I could not trigger for adc_wr or adc valid 

    when probed for clock freq I got 

    device_clock = 31.25MHz  i guess it should be 62.5MHz

    Link clock = 250MHz i guess it should be 125 MHz

    I guess In system_top.v

    IBUFDS_GTE2 i_ibufds_tx_ref_clk (
    .CEB (1'd0),
    .I (tx_ref_clk_p),
    .IB (tx_ref_clk_n),
    .O (),
    .ODIV2 (device_clk));

    Could be the issue

    in case of link clock I may have to edit dts for div2

  • I changed 

    device_clk generation in system_top.v to

    IBUFDS_GTE2 i_ibufds_tx_ref_clk (
    .CEB (1'd0),
    .I (tx_ref_clk_p),
    .IB (tx_ref_clk_n),
    .O (device_clk),
    .ODIV2 ());

    in dts


    adi,sys-clk-select = <XCVR_CPLL>;
    adi,out-clk-select = <XCVR_REFCLK_DIV2>;

    Once these changes made

    device_clk = 62.5MHz

    link_clk = 125MHz

    In ILA attached there is still  no data 

  • I guess when I read 

    0x570 register for AD9680 using IIO . it  has a value 0f 0x88 (default configuration)

    This shows 

    L= 4 expected 2

    M = 2 expected 8

    F = 1 expected 8

    So AD9680 may not be configured properly . How to do this??

    While building linux kernel I has used Vivado SDK 2019.1? Will that be the problem

    I also tried capturing data from util_xcvr_rxdata which showed a constant value