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Enable DDC in FMCDAQ2 + kc705


I am using KC705 & FMCDAQ2 combo. I would finally move to ZC706 + FMCDAQ2

I would like enable DDC in AD9680. My preferred configuration is given in ""Table 23. DDC Example Configurations"" Chip decimation ratio is 16 ie no of virtual converters 8.
I have referred to below link.

In case of HDL design, ""you could modify the design to M=8 ""

Does that mean I need to edit projects\daq2\common\daq2_bd.tcl? What are the other parameters to change?

ad_ip_instance util_cpack2 axi_ad9680_cpack { \


ad_ip_instance util_cpack2 axi_ad9680_cpack { \

our requirement is similar to ""Example 2: ADC with DDC Option (Two ADCs Plus Four DDCs)"" in AD9680 data sheet.

As i understand, we may have to reduce no of lanes to 2 from given default 4 lanes in example design to maintain minimum lane rate of >3.125Gbps.

Is there any guidelines to reduce the lane nos in HDL design? Do I need to just edit daq2_bd.tcl?

  • Hello,

    You just need to edit the daq2_bd.tcl file in the common directory. Since the architecture construction is parameterized you just need to modify the variables defined in the beginning of the file: set RX_NUM_OF_LANES 2 ; # L
                                                                                 set RX_NUM_OF_CONVERTERS 8 ; # M
                                                                                 set RX_SAMPLES_PER_FRAME 1 ; # S
                                                                                 set RX_SAMPLE_WIDTH 16 ; # N/NP

    Best Regards,

    Dan Hotoleanu

  • For hdl_2019_r2 with the above modification in daq2_bd.tcl synthesis failed with following error 

    ""ERROR: [Synth 8-2908] range width must be a positive integer [d:/adi/ddc_ver/projects/daq2/kc705/daq2_kc705.srcs/sources_1/bd/system/ipshared/6295/util_cpack2.v:280]
    ERROR: [Synth 8-6156] failed synthesizing module 'util_cpack2' [d:/adi/ddc_ver/projects/daq2/kc705/daq2_kc705.srcs/sources_1/bd/system/ipshared/6295/util_cpack2.v:38]
    ERROR: [Synth 8-6156] failed synthesizing module 'system_axi_ad9680_cpack_0' [d:/adi/ddc_ver/projects/daq2/kc705/daq2_kc705.srcs/sources_1/bd/system/ip/system_axi_ad9680_cpack_0/synth/system_axi_ad9680_cpack_0.v:57]
    ERROR: [Synth 8-6156] failed synthesizing module 'system' [D:/adi/ddc_ver/projects/daq2/kc705/daq2_kc705.srcs/sources_1/bd/system/synth/system.v:2942]
    ERROR: [Synth 8-6156] failed synthesizing module 'system_wrapper' [D:/adi/ddc_ver/projects/daq2/kc705/daq2_kc705.srcs/sources_1/imports/hdl/system_wrapper.v:12]
    ERROR: [Synth 8-6156] failed synthesizing module 'system_top' [d:/adi/ddc_ver/projects/daq2/kc705/system_top.v:38]


  • Hello, 

    after a review of the changes we found that in the above mentioned design the following line is incorrect:

    ad_ip_parameter axi_ad9680_jesd/rx CONFIG.DATA_PATH_WIDTH 8

    The correct value for DATA_PATH_WIDTH  must be 4.  This can be the cause of staying in CGS mode. 

    We are investigating the software too.  We will attempt to bring up the link with Linux. 

    Thank you,


  • Hello,

    I tried

    ad_ip_parameter axi_ad9680_jesd/rx CONFIG.DATA_PATH_WIDTH 4

    Now I could get some random data at the output of ADC

    I tried checker patterns as in ""JESD204B DATA LINK LAYER TEST PATTERNS""

    I used IIO scope for feeding patterns

    Even with checker output I could  get only random data at input of axi_ad9680_tpl

    link_clk , link_valid , link_data(127:0)

    Link_valid turns High but data remains random even for constant checker pattern..

    I guess device is out of CGS...

    I have tried experiment of kc705 I will try same on Zc706

    In case you have a working model please share....I wish to resolve this issue....

  • Hello, 

    we managed to do progress on our side with Linux,  

    The link is in DATA but on half of the channels seems that we receive only noize, other half are constant zero.

    We are investigating it.  We plan to enable the test patterns and check against that. 


  • Hello, 

    I managed to setup all the DDC channels and they seem to work now, you can follow the configuration I made here in the ad9680.c Linux driver ( Just for the test I configured all 4 DDC channels with a decimation factor of 16 and with a NCO frequency and NCO phase of 8.

    If you have any questions, let met know!

    Best regards,


  • I will try it at my end!! 

    I request you to update hdl version too so that in future we need to just check out from the git link....

    current link I refer for is 

  • Hi Filip,

    I am attempting to create uImage,BOOT.BIN for the project.

    Since I am using 2020.1 Vivado for building your Linux , I am not getting proper steps to boot using Vitis. Do you have any recommended step for this build BOOT.BIN.

    I am able to the build the project for hdl_revision_2019_2. But when it comes to building for Vitis I am unable to boot ZC706. I am not receiving any print on console.

    Please help me build this project.

  • I was referring to steps in ""Build the boot image""
    for building images for zc706 for hdl_2019_R2. I could successfully build and boot project.

    DDC project uses Vivado 2020.1 I guess I will have to used Vitis.

    Here I am not so sure about the steps. I tried to create BOOT.BIN which has
    1. system_top.bit
    2. zynq_fsbl.elf
    3. uBoot.elf

    i followed the steps given in for creating FSBL FSBL

    After porting BOOT.BIN to SD card. I could not find any prints on my console. I could see DONE LED going high. I guess there is some issue with the method used to create FSBL.

    What steps did you adopt??

  • Hello,

    If you want to build the BOOT.BIN you first have to build the project itself, for example hdl/projects/daq2/zc706, do a make there, and after the build is done, copy the uBoot.elf file in the project folder and then open the .xpr vivado project and then go in the tcl console and write those two commands: source ../../scripts/adi_make.tcl and then adi_make::boot_bin and after this you'll get a BOOT.BIN in the boot_bin folder. I did an update on git here ( and this will work with vivado version 2020.1, you just need to follow the steps I mentioned.

    Best regards,


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