Hi,
I am using KC705 & FMCDAQ2 combo. I would finally move to ZC706 + FMCDAQ2
I would like enable DDC in AD9680. My preferred configuration is given in ""Table 23. DDC Example Configurations"" Chip decimation ratio is 16 ie no of virtual converters 8.
I have referred to below link.
In case of HDL design, ""you could modify the design to M=8 ""
Does that mean I need to edit projects\daq2\common\daq2_bd.tcl? What are the other parameters to change?
""
ad_ip_instance util_cpack2 axi_ad9680_cpack { \
NUM_OF_CHANNELS 2 \
SAMPLES_PER_CHANNEL 4 \
SAMPLE_DATA_WIDTH 16 \
}
""
to
""
ad_ip_instance util_cpack2 axi_ad9680_cpack { \
NUM_OF_CHANNELS 8 \
SAMPLES_PER_CHANNEL 1 \
SAMPLE_DATA_WIDTH 16 \
}
""
our requirement is similar to ""Example 2: ADC with DDC Option (Two ADCs Plus Four DDCs)"" in AD9680 data sheet.
As i understand, we may have to reduce no of lanes to 2 from given default 4 lanes in example design to maintain minimum lane rate of >3.125Gbps.
Is there any guidelines to reduce the lane nos in HDL design? Do I need to just edit daq2_bd.tcl?
