Enable DDC in FMCDAQ2 + kc705

Hello,

You just need to edit the daq2_bd.tcl file in the common directory. Since the architecture construction is parameterized you just need to modify the variables defined in the beginning of the file: set RX_NUM_OF_LANES 2 ; # L
                                                                             set RX_NUM_OF_CONVERTERS 8 ; # M
                                                                             set RX_SAMPLES_PER_FRAME 1 ; # S
                                                                             set RX_SAMPLE_WIDTH 16 ; # N/NP

Best Regards,

Dan Hotoleanu

For hdl_2019_r2 with the above modification in daq2_bd.tcl synthesis failed with following error 

""ERROR: [Synth 8-2908] range width must be a positive integer [d:/adi/ddc_ver/projects/daq2/kc705/daq2_kc705.srcs/sources_1/bd/system/ipshared/6295/util_cpack2.v:280]
ERROR: [Synth 8-6156] failed synthesizing module 'util_cpack2' [d:/adi/ddc_ver/projects/daq2/kc705/daq2_kc705.srcs/sources_1/bd/system/ipshared/6295/util_cpack2.v:38]
ERROR: [Synth 8-6156] failed synthesizing module 'system_axi_ad9680_cpack_0' [d:/adi/ddc_ver/projects/daq2/kc705/daq2_kc705.srcs/sources_1/bd/system/ip/system_axi_ad9680_cpack_0/synth/system_axi_ad9680_cpack_0.v:57]
ERROR: [Synth 8-6156] failed synthesizing module 'system' [D:/adi/ddc_ver/projects/daq2/kc705/daq2_kc705.srcs/sources_1/bd/system/synth/system.v:2942]
ERROR: [Synth 8-6156] failed synthesizing module 'system_wrapper' [D:/adi/ddc_ver/projects/daq2/kc705/daq2_kc705.srcs/sources_1/imports/hdl/system_wrapper.v:12]
ERROR: [Synth 8-6156] failed synthesizing module 'system_top' [d:/adi/ddc_ver/projects/daq2/kc705/system_top.v:38]

""

For hdl_2019_r2 with the above modification in daq2_bd.tcl synthesis failed with following error 

""ERROR: [Synth 8-2908] range width must be a positive integer [d:/adi/ddc_ver/projects/daq2/kc705/daq2_kc705.srcs/sources_1/bd/system/ipshared/6295/util_cpack2.v:280]
ERROR: [Synth 8-6156] failed synthesizing module 'util_cpack2' [d:/adi/ddc_ver/projects/daq2/kc705/daq2_kc705.srcs/sources_1/bd/system/ipshared/6295/util_cpack2.v:38]
ERROR: [Synth 8-6156] failed synthesizing module 'system_axi_ad9680_cpack_0' [d:/adi/ddc_ver/projects/daq2/kc705/daq2_kc705.srcs/sources_1/bd/system/ip/system_axi_ad9680_cpack_0/synth/system_axi_ad9680_cpack_0.v:57]
ERROR: [Synth 8-6156] failed synthesizing module 'system' [D:/adi/ddc_ver/projects/daq2/kc705/daq2_kc705.srcs/sources_1/bd/system/synth/system.v:2942]
ERROR: [Synth 8-6156] failed synthesizing module 'system_wrapper' [D:/adi/ddc_ver/projects/daq2/kc705/daq2_kc705.srcs/sources_1/imports/hdl/system_wrapper.v:12]
ERROR: [Synth 8-6156] failed synthesizing module 'system_top' [d:/adi/ddc_ver/projects/daq2/kc705/system_top.v:38]

""

Hello Dan,

I changed daq2_bd.tcl with following line

set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 64 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH) 

from

set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32/ ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH) 

This allowed Vivado to generate bit file. Still I am not sure about the implication of such a change. Here is the image of system block

Hello,

For the required configuration, you'll have to set F=8 and datapath 8 bytes (https://github.com/analogdevicesinc/hdl/blob/master/projects/ad9083_evb/common/ad9083_evb_bd.tcl#L27)  and you'll be in a mode similar with the one described here:

https://wiki.analog.com/resources/eval/user-guides/ad9083/ad9083_evb_reference_hdl

You'll need a link clock (lane_rate/40) and a deviceclock (lane_rate/20). 

DAQ2 has a single clock available as GTREFCLK from which the device_clock is derived, so you'll need to use that for all three clocks. Most likely you need to change the reference clock to 250MHz and use it as link clock and then divide it by 2 to use it as device clock. We need to test this configuration on our side and may take a few days.

Regards,

Adrian

I made the following changes to dac2_bd.tcl

Changed line to 

set RX_SAMPLES_PER_CHANNEL 1;# [expr $RX_NUM_OF_LANES * 32 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)]

Added new line

adi_axi_jesd204_rx_create axi_ad9680_jesd $RX_NUM_OF_LANES
ad_ip_parameter axi_ad9680_jesd/rx CONFIG.DATA_PATH_WIDTH 8

I was able to build the project. But when I check axi_ad9680_jesd(Attached image) I observed Data path Width as 4. I was expecting that this will change to 8 No sure whether this is correct.

Attaching 4478.daq2_bd.rar

I made the following changes to dac2_bd.tcl

Changed line to 

set RX_SAMPLES_PER_CHANNEL 1;# [expr $RX_NUM_OF_LANES * 32 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)]

Added new line

adi_axi_jesd204_rx_create axi_ad9680_jesd $RX_NUM_OF_LANES
ad_ip_parameter axi_ad9680_jesd/rx CONFIG.DATA_PATH_WIDTH 8

I was able to build the project. But when I check axi_ad9680_jesd(Attached image) I observed Data path Width as 4. I was expecting that this will change to 8 No sure whether this is correct.

Attaching 4478.daq2_bd.rar

In Vivado log file I could see following details

### ad_ip_parameter axi_ad9680_jesd/rx CONFIG.DATA_PATH_WIDTH 8
WARNING: [BD 41-721] Attempt to set value '8' on disabled parameter 'DATA_PATH_WIDTH' of cell '/axi_ad9680_jesd/rx' is ignored

I believe that hdl version (hdl_2019_r2) does not support changing following parameter

ad_ip_parameter axi_ad9083_rx_jesd/rx CONFIG.TPL_DATA_PATH_WIDTH 8

"hdl/library/jesd204/jesd204_rx/jesd204_rx.v" has only following paramters

module jesd204_rx #(
parameter NUM_LANES = 1,
parameter NUM_LINKS = 1,
parameter NUM_INPUT_PIPELINE = 1,
parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
/* Only 4 is supported at the moment for 8b/10b and 8 for 64b */
parameter DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4,
parameter ENABLE_FRAME_ALIGN_CHECK = 1,
parameter ENABLE_FRAME_ALIGN_ERR_RESET = 0
) (

I would request you to suggest the branch i need to checkout inorder for changes suggested to take effect.

Is it possible for me to update jesd204_rx of (hdl_2019_r2) with verion from master branch?

Can Expect an update for this request?? I am still stuck at this point.

Hello,

I created two branches on git where I've modified the daq2 hdl and linux project. The modification is not tested on hardware. The hdl part is available here: https://github.com/hotoleanudan/hdl/commit/d4b259bc967696cd74d6774810d728b8f04b08bb  and the linux part is available here: https://github.com/analogdevicesinc/linux/commit/22306c385556075a215e21a5b0c40760cca79cd0 . 

Best Regards,

Dan 

Hello Dan,

I tried building hdl using Vivado 2020.1

I encounter the following error while building project.

""

Building axi_clkgen library [/cygdrive/d/adi/Analog_Support/hdl/library/axi_clkgen/axi_clkgen_ip.log] ... OK
Building axi_hdmi_tx library [/cygdrive/d/adi/Analog_Support/hdl/library/axi_hdmi_tx/axi_hdmi_tx_ip.log] ... OK
Building axi_spdif_tx library [/cygdrive/d/adi/Analog_Support/hdl/library/axi_spdif_tx/axi_spdif_tx_ip.log] ... OK
Building axi_adcfifo library [/cygdrive/d/adi/Analog_Support/hdl/library/xilinx/axi_adcfifo/axi_adcfifo_ip.log] ... OK
Building daq2_zc706 project [/cygdrive/d/adi/Analog_Support/hdl/projects/daq2/zc706/daq2_zc706_vivado.log] ... FAILED
For details see /cygdrive/d/adi/Analog_Support/hdl/projects/daq2/zc706/daq2_zc706_vivado.log

make: *** [../../scripts/project-xilinx.mk:61: daq2_zc706.sdk/system_top.hdf] Error 1

""0755.daq2_zc706_vivado.log

Attaching log file

Hello,

Can you please make a fresh clone of the hdl repository on my fork https://github.com/hotoleanudan/hdl and switch to daq2_without_ad9144_proj branch and then build the daq2/zc706 project?

Thank you.

Best Regards,

Dan

Hi,

As of now I do not have zc706 hardware with me. So i tried building for kc705 + fmcdaq2.
I could build project and boot it on kc705.

I could observe AD9680 on IIO scope but could not find any waveforms in capture

In dts file I could not find include for XCVR_REFCLK_DIV1 so edit was follows
""
axi_ad9680_adxcvr: axi-ad9680-adxcvr@44a50000 {
compatible = "adi,axi-adxcvr-1.0";
reg = <0x44a50000 0x10000>;

clocks = <&clk0_ad9523 4>;
clock-names = "conv";

adi,sys-clk-select = <XCVR_CPLL>;

adi,out-clk-select = <XCVR_REFCLK>;
adi,use-lpm-enable;
adi,vco-max-khz = <5000000>;
""

I am also attaching boot-up print Linux print

"jesd204: found 0 devices and 0 topologies" which I have not seen in working versions

Attachments

xdc file
top file
Linux boot-up print
dts

Attachment.rar