AD9695 FMC Card Reference Design

Hi, I opened an example project of the AD9695 according to the HDL guide and the project has no block diagram. 

What could be the problem?

 The link with the project: (https://github.com/sarpadi/hdl/tree/dev_ad9695/projects/ad9695_fmc/zcu102

Regards,

Elad

Parents
  • +1
    •  Analog Employees 
    on Jul 1, 2021 1:44 PM

    Hi Elad,

    Take a look at the ad9695_fmc_vivado.log file. If you can't figure it out, attache the log file here as txt.

    Andrei

  • ource ../../scripts/adi_make.tcl
    # namespace eval adi_make {
    # ##############################################################################
    # # to print debug step messages "set debug_msg=1" (set adi_make::debug_msg 1)
    # variable debug_msg 0
    # ##############################################################################
    #
    # variable library_dir
    # variable PWD [pwd]
    # variable root_hdl_folder
    # variable done_list ""
    # variable indent_level ""
    #
    # # get library absolute path
    # set root_hdl_folder ""
    # set glb_path $PWD
    # if { [regexp projects $glb_path] } {
    # regsub {/projects.*$} $glb_path "" root_hdl_folder
    # } else {
    # puts "ERROR: Not in hdl/* folder"
    # return
    # }
    #
    # set library_dir "$root_hdl_folder/library"
    #
    # #----------------------------------------------------------------------------
    # # have debug messages
    # proc puts_msg { message } {
    # variable debug_msg
    # variable indent_level
    # if { $debug_msg == 1 } {
    # puts $indent_level$message
    # }
    # }
    #
    # #----------------------------------------------------------------------------
    # # returns the projects required set of libraries
    # proc get_libraries {} {
    #
    # set build_list ""
    #
    # set search_pattern "LIB_DEPS.*="
    # set fp1 [open ./Makefile r]
    # set file_data [read $fp1]
    # close $fp1
    #
    # set lines [split $file_data \n]
    # foreach line $lines {
    # if { [regexp $search_pattern $line] } {
    # regsub -all $search_pattern $line "" library
    # set library [string trim $library]
    # puts_msg "\t- project dep: $library"
    # append build_list "$library "
    # }
    # }
    # return $build_list
    # }
    #
    # #----------------------------------------------------------------------------
    # proc lib { libraries } {
    #
    # variable library_dir
    # variable PWD
    # variable done_list
    #
    # set build_list $libraries
    # if { $libraries == "all" } {
    # set build_list "[get_libraries]"
    # }
    #
    # set libraries ""
    # puts "Building:"
    # foreach b_lib $build_list {
    # puts "- $b_lib"
    # append libraries "$library_dir/$b_lib "
    # }
    #
    # puts "Please wait, this might take a few minutes"
    #
    # # searching for subdir libraries in path of the given args
    # set first_lib [lindex $libraries 0]
    # if { $first_lib == "" } {
    # set first_lib "."
    # }
    # # getting all (libraries)
    # set index 0
    # set library_element(1) $first_lib
    # foreach argument $libraries {
    # incr index 1
    # set library_element($index) $argument
    # }
    #
    # # search for all possible IPs in the given argument paths
    # set makefiles ""
    # if { $index == 0 } {
    # set index 1
    # }
    # for {set y 1} {$y<=$index} {incr y} {
    # set dir "$library_element($y)/"
    # #search 4 level subdirectories for Makefiles
    # for {set x 1} {$x<=4} {incr x} {
    # catch { append makefiles " [glob "${dir}Makefile"]" } err
    # append dir "*/"
    # }
    # }
    #
    # if { $makefiles == "" } {
    # puts "ERROR: Wrong path to IP or the IP does not have a Makefile starting from \"$library_element(1)\""
    # }
    #
    # # filter out non buildable libs (non *_ip.tcl)
    # set buildable ""
    # foreach fs $makefiles {
    # set lib_dir [file dirname $fs]
    # set lib_name "[file tail $lib_dir]_ip.tcl"
    # if { [file exists $lib_dir/$lib_name] } {
    # append buildable "$fs "
    # }
    # }
    # set makefiles $buildable
    #
    # # build all detected IPs
    # foreach fs $makefiles {
    # regsub /Makefile $fs "" fs
    # if { $fs == "." } {
    # set fs [string trim [file tail [file normalize $fs]]]
    # }
    # regsub .*library/ $fs "" fs
    # build_lib $fs
    # }
    #
    # cd $PWD
    # set done_list ""
    # }
    #
    # #----------------------------------------------------------------------------
    # # IP build procedure
    # proc build_lib { library } {
    #
    # variable done_list
    # variable library_dir
    # variable indent_level
    #
    # append indent_level "\t" ;# debug messages
    #
    # puts_msg "DEBUG build_lib proc (recursive called)"
    #
    # # determine if the IP was previously built in the current adi_make_lib.tcl call
    # if { [regexp $library $done_list] } {
    # puts_msg "> Build previously done on $library"
    # regsub . $indent_level "" indent_level
    # return
    # } else {
    # puts_msg "- Start build of $library"
    # }
    # puts_msg "- Search dependencies for $library"
    #
    # # search for current IP dependencies
    #
    # # define library dependency search (Makefiles)
    # set serch_pattern "XILINX_.*_DEPS.*="
    # set dep_list ""
    #
    # set fp1 [open $library_dir/$library/Makefile r]
    # set file_data [read $fp1]
    # close $fp1
    #
    # set lines [split $file_data \n]
    # foreach line $lines {
    # if { [regexp $serch_pattern $line] } {
    # regsub -all $serch_pattern $line "" lib_dep
    # set lib_dep [string trim $lib_dep]
    # puts_msg "\t$library is dependent on $lib_dep"
    # append dep_list "$lib_dep "
    # }
    # }
    #
    # foreach lib $dep_list {
    # build_lib $lib
    # }
    #
    # puts_msg "- Continue build on $library"
    # set lib_name "[file tail $library]_ip"
    #
    # cd $library_dir/${library}
    # exec vivado -mode batch -source "$library_dir/${library}/${lib_name}.tcl"
    # file copy -force ./vivado.log ./${lib_name}.log
    # puts "- Done building $library"
    # append done_list $library
    # regsub . $indent_level "" indent_level
    # }
    #
    # #----------------------------------------------------------------------------
    # # boot_bin build procedure
    # proc boot_bin {} {
    #
    # variable root_hdl_folder
    #
    # set arm_tr_sw_elf "bl31.elf"
    # set boot_bin_folder "boot_bin"
    # if {[catch {set hdf_file "[glob "./*.sdk/system_top.hdf"]"} fid]} {
    # puts stderr "ERROR: $fid\n\rNOTE: you must have built hdl project\n\
    # \rSee: ">wiki.analog.com/.../build\n"
    # return
    # }
    # if {[catch {set uboot_elf "[glob "./u-boot*.elf"]" } fid]} {
    # puts stderr "ERROR: $fid\n\rNOTE: you must have a the u-boot.elf in [pwd]\n\
    # \rSee: ">wiki.analog.com/.../build\n"
    # return
    # }
    #
    # puts "root_hdl_folder $root_hdl_folder"
    # puts "uboot_elf $uboot_elf"
    # puts "hdf_file $hdf_file"
    #
    # # determine if Xilinx SDK tools are set in the enviroment
    # package require platform
    # set os_type [platform::generic]
    # if { [regexp ^win $os_type] } {
    # set w_cmd where
    # } elseif { [regexp ^linux $os_type] } {
    # set w_cmd which
    # } else {
    # puts "ERROR: Unknown OS: $os_type"
    # exit 1
    # }
    # set xsct_loc [exec $w_cmd xsct]
    #
    # # search for Xilinx Command Line Tool (SDK)
    # if { $xsct_loc == "" } {
    # puts $env(PATH)
    # puts "ERROR: SDK not installed or it is not defined in the enviroment path"
    # exit 1
    # }
    #
    # set xsct_script "exec xsct $root_hdl_folder/projects/scripts/adi_make_boot_bin.tcl"
    # set build_args "$hdf_file $uboot_elf $boot_bin_folder $arm_tr_sw_elf"
    # puts "Please wait, this may take a few minutes."
    # eval $xsct_script $build_args
    # }
    #
    # } ;
    adi_make::lib all
    Building:
    - util_adcfifo
    - axi_dmac
    - axi_sysid
    - jesd204/ad_ip_jesd204_tpl_adc
    - jesd204/axi_jesd204_rx
    - jesd204/jesd204_rx
    - sysid_rom
    - util_pack/util_cpack2
    - xilinx/axi_adxcvr
    - xilinx/util_adxcvr
    Please wait, this might take a few minutes
    - Done building util_cdc
    - Done building util_adcfifo
    - Done building util_axis_fifo
    - Done building axi_dmac
    - Done building axi_sysid
    - Done building jesd204/ad_ip_jesd204_tpl_adc
    - Done building jesd204/axi_jesd204_common
    - Done building jesd204/interfaces
    - Done building jesd204/axi_jesd204_rx
    - Done building jesd204/jesd204_common
    - Done building jesd204/jesd204_rx
    - Done building sysid_rom
    - Done building util_pack/util_cpack2
    - Done building xilinx/axi_adxcvr
    - Done building xilinx/util_adxcvr
    source ./system_project.tcl
    # source ../../scripts/adi_env.tcl
    ## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
    ## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
    ## if [info exists ::env(ADI_HDL_DIR)] {
    ## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
    ## }
    ## if [info exists ::env(ADI_GHDL_DIR)] {
    ## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
    ## }
    ## proc get_env_param {name default_value} {
    ## if [info exists ::env($name)] {
    ## puts "Getting from environment the parameter: $name=$::env($name) "
    ## return $::env($name)
    ## } else {
    ## return $default_value
    ## }
    ## }
    # source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
    ## if {![info exists REQUIRED_VIVADO_VERSION]} {
    ## set REQUIRED_VIVADO_VERSION "2020.1"
    ## }
    ## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
    ## set IGNORE_VERSION_CHECK 1
    ## } elseif {![info exists IGNORE_VERSION_CHECK]} {
    ## set IGNORE_VERSION_CHECK 0
    ## }
    ## if {[info exists ::env(ADI_USE_OOC_SYNTHESIS)]} {
    ## set ADI_USE_OOC_SYNTHESIS 1
    ## } elseif {![info exists ADI_USE_OOC_SYNTHESIS]} {
    ## set ADI_USE_OOC_SYNTHESIS 0
    ## }
    ## set ADI_USE_INCR_COMP 1
    ## set ADI_POWER_OPTIMIZATION 0
    ## set p_board "not-applicable"
    ## set p_device "none"
    ## set sys_zynq 1
    ## set p_prcfg_init ""
    ## set p_prcfg_list ""
    ## set p_prcfg_status ""
    ## proc adi_project {project_name {mode 0} {parameter_list {}} } {
    ##
    ## set device ""
    ## set board ""
    ##
    ## # Determine the device based on the board name
    ## if [regexp "_ac701$" $project_name] {
    ## set device "xc7a200tfbg676-2"
    ## set board [lindex [lsearch -all -inline [get_board_parts] *ac701*] end]
    ## }
    ## if [regexp "_kc705$" $project_name] {
    ## set device "xc7k325tffg900-2"
    ## set board [lindex [lsearch -all -inline [get_board_parts] *kc705*] end]
    ## }
    ## if [regexp "_vc707$" $project_name] {
    ## set device "xc7vx485tffg1761-2"
    ## set board [lindex [lsearch -all -inline [get_board_parts] *vc707*] end]
    ## }
    ## if [regexp "_vcu118$" $project_name] {
    ## set device "xcvu9p-flga2104-2L-e"
    ## set board [lindex [lsearch -all -inline [get_board_parts] *vcu118*] end]
    ## }
    ## if [regexp "_kcu105$" $project_name] {
    ## set device "xcku040-ffva1156-2-e"
    ## set board [lindex [lsearch -all -inline [get_board_parts] *kcu105*] end]
    ## }
    ## if [regexp "_zed$" $project_name] {
    ## set device "xc7z020clg484-1"
    ## set board [lindex [lsearch -all -inline [get_board_parts] *zed*] end]
    ## }
    ## if [regexp "_coraz7s$" $project_name] {
    ## set device "xc7z007sclg400-1"
    ## set board "not-applicable"
    ## }
    ## if [regexp "_microzed$" $project_name] {
    ## set device "xc7z010clg400-1"
    ## set board "not-applicable"
    ## }
    ## if [regexp "_zc702$" $project_name] {
    ## set device "xc7z020clg484-1"
    ## set board [lindex [lsearch -all -inline [get_board_parts] *zc702*] end]
    ## }
    ## if [regexp "_zc706$" $project_name] {
    ## set device "xc7z045ffg900-2"
    ## set board [lindex [lsearch -all -inline [get_board_parts] *zc706*] end]
    ## }
    ## if [regexp "_mitx045$" $project_name] {
    ## set device "xc7z045ffg900-2"
    ## set board "not-applicable"
    ## }
    ## if [regexp "_zcu102$" $project_name] {
    ## set device "xczu9eg-ffvb1156-2-e"
    ## set board [lindex [lsearch -all -inline [get_board_parts] *zcu102*] end]
    ## }
    ##
    ## adi_project_create $project_name $mode $parameter_list $device $board
    ## }
    ## proc adi_project_create {project_name mode parameter_list device {board "not-applicable"}} {
    ##
    ## global ad_hdl_dir
    ## global ad_ghdl_dir
    ## global p_board
    ## global p_device
    ## global sys_zynq
    ## global REQUIRED_VIVADO_VERSION
    ## global IGNORE_VERSION_CHECK
    ## global ADI_USE_OOC_SYNTHESIS
    ## global ADI_USE_INCR_COMP
    ##
    ## ## update the value of $p_device only if it was not already updated elsewhere
    ## if {$p_device eq "none"} {
    ## set p_device $device
    ## }
    ## set p_board $board
    ##
    ## if [regexp "^xc7z" $p_device] {
    ## set sys_zynq 1
    ## } elseif [regexp "^xczu" $p_device] {
    ## set sys_zynq 2
    ## } else {
    ## set sys_zynq 0
    ## }
    ##
    ## set VIVADO_VERSION [version -short]
    ## if {$IGNORE_VERSION_CHECK} {
    ## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
    ## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
    ## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
    ## puts -nonewline "got $VIVADO_VERSION.\n"
    ## }
    ## } else {
    ## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
    ## puts -nonewline "ERROR: vivado version mismatch; "
    ## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
    ## puts -nonewline "got $VIVADO_VERSION.\n"
    ## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
    ## exit 2
    ## }
    ## }
    ##
    ## if {$mode == 0} {
    ## set project_system_dir "./$project_name.srcs/sources_1/bd/system"
    ## create_project $project_name . -part $p_device -force
    ## } else {
    ## set project_system_dir ".srcs/sources_1/bd/system"
    ## create_project -in_memory -part $p_device
    ## }
    ##
    ## if {$mode == 1} {
    ## file mkdir $project_name.data
    ## }
    ##
    ## if {$p_board ne "not-applicable"} {
    ## set_property board_part $p_board [current_project]
    ## }
    ##
    ## set lib_dirs $ad_hdl_dir/library
    ## if {$ad_hdl_dir ne $ad_ghdl_dir} {
    ## lappend lib_dirs $ad_ghdl_dir/library
    ## }
    ##
    ## # Set a common IP cache for all projects
    ## if {$ADI_USE_OOC_SYNTHESIS == 1} {
    ## if {[file exists $ad_hdl_dir/ipcache] == 0} {
    ## file mkdir $ad_hdl_dir/ipcache
    ## }
    ## config_ip_cache -import_from_project -use_cache_location $ad_hdl_dir/ipcache
    ## }
    ##
    ## set_property ip_repo_paths $lib_dirs [current_fileset]
    ## update_ip_catalog
    ##
    ## ## Load custom message severity definitions
    ##
    ## if {![info exists ::env(ADI_DISABLE_MESSAGE_SUPPRESION)]} {
    ## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
    ## }
    ##
    ## ## In Vivado there is a limit for the number of warnings and errors which are
    ## ## displayed by the tool for a particular error or warning; the default value
    ## ## of this limit is 100.
    ## ## Overrides the default limit to 2000.
    ## set_param messaging.defaultLimit 2000
    ##
    ## # Set parameters of the top level file
    ## # Make the same parameters available to system_bd.tcl
    ## set proj_params [get_property generic [current_fileset]]
    ## foreach {param value} $parameter_list {
    ## lappend proj_params $param=$value
    ## set ad_project_params($param) $value
    ## }
    ## set_property generic $proj_params [current_fileset]
    ##
    ## create_bd_design "system"
    ## source system_bd.tcl
    ##
    ## save_bd_design
    ## validate_bd_design
    ##
    ## if {$ADI_USE_OOC_SYNTHESIS == 1} {
    ## set_property synth_checkpoint_mode Hierarchical [get_files $project_system_dir/system.bd]
    ## } else {
    ## set_property synth_checkpoint_mode None [get_files $project_system_dir/system.bd]
    ## }
    ## generate_target {synthesis implementation} [get_files $project_system_dir/system.bd]
    ## if {$ADI_USE_OOC_SYNTHESIS == 1} {
    ## export_ip_user_files -of_objects [get_files $project_system_dir/system.bd] -no_script -sync -force -quiet
    ## create_ip_run [get_files $project_system_dir/system.bd]
    ## }
    ## make_wrapper -files [get_files $project_system_dir/system.bd] -top
    ##
    ## if {$mode == 0} {
    ## import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v
    ## } else {
    ## write_hwdef -file "$project_name.data/$project_name.hwdef"
    ## }
    ##
    ## if {$ADI_USE_INCR_COMP == 1} {
    ## if {[file exists ./reference.dcp]} {
    ## set_property incremental_checkpoint ./reference.dcp [get_runs impl_1]
    ## }
    ## }
    ##
    ## }
    ## proc adi_project_files {project_name project_files} {
    ##
    ## foreach pfile $project_files {
    ## if {[string range $pfile [expr 1 + [string last . $pfile]] end] == "xdc"} {
    ## add_files -norecurse -fileset constrs_1 $pfile
    ## } else {
    ## add_files -norecurse -fileset sources_1 $pfile
    ## }
    ## }
    ##
    ## # NOTE: top file name is always system_top
    ## set_property top system_top [current_fileset]
    ## }
    ## proc adi_project_run {project_name} {
    ##
    ## global ADI_POWER_OPTIMIZATION
    ## global ADI_USE_OOC_SYNTHESIS
    ##
    ## if {$ADI_USE_OOC_SYNTHESIS == 1} {
    ## launch_runs -jobs 4 system_*_synth_1 synth_1
    ## } else {
    ## launch_runs synth_1
    ## }
    ## wait_on_run synth_1
    ## open_run synth_1
    ## report_timing_summary -file timing_synth.log
    ##
    ## if {![info exists ::env(ADI_NO_BITSTREAM_COMPRESSION)] && ![info exists ADI_NO_BITSTREAM_COMPRESSION]} {
    ## set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
    ## }
    ##
    ## if {$ADI_POWER_OPTIMIZATION == 1} {
    ## set_property STEPS.POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
    ## set_property STEPS.POST_PLACE_POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
    ## }
    ##
    ## launch_runs impl_1 -to_step write_bitstream
    ## wait_on_run impl_1
    ## open_run impl_1
    ## report_timing_summary -warn_on_violation -file timing_impl.log
    ##
    ## if {[info exists ::env(ADI_GENERATE_UTILIZATION)]} {
    ## set csv_file resource_utilization.csv
    ## if {[ catch {
    ## xilinx::designutils::report_failfast -csv -file $csv_file -transpose -no_header -ignore_pr -quiet
    ## set MMCM [llength [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ *MMCM* }]]
    ## set PLL [llength [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ *PLL* }]]
    ## set worst_slack_setup [get_property SLACK [get_timing_paths -setup]]
    ## set worst_slack_hold [get_property SLACK [get_timing_paths -hold]]
    ##
    ## set fileRead [open $csv_file r]
    ## set lines [split [read $fileRead] "\n"]
    ## set names_line [lindex $lines end-3]
    ## set values_line [lindex $lines end-2]
    ## close $fileRead
    ##
    ## set fileWrite [open $csv_file w]
    ## puts $fileWrite "$names_line,MMCM*,PLL*,Worst_Setup_Slack,Worst_Hold_Slack"
    ## puts $fileWrite "$values_line,$MMCM,$PLL,$worst_slack_setup,$worst_slack_hold"
    ## close $fileWrite
    ## } issue ] != 0 } {
    ## puts "GENERATE_REPORTS: tclapp::xilinx::designutils not installed"
    ## }
    ##
    ## # Define a list of IPs for which to generate report utilization
    ## set IP_list {
    ## ad_ip_jesd_204_tpl_adc
    ## ad_ip_jesd_204_tpl_dac
    ## axi_jesd204_rx
    ## axi_jesd204_tx
    ## jesd204_rx
    ## jesd204_tx
    ## axi_adxcvr
    ## util_adxcvr
    ## axi_dmac
    ## util_cpack2
    ## util_upack2
    ## }
    ##
    ## foreach IP_name $IP_list {
    ## set output_file ${IP_name}_resource_utilization.log
    ## file delete $output_file
    ## foreach IP_instance [ get_cells -quiet -hierarchical -filter " ORIG_REF_NAME =~ $IP_name || REF_NAME =~ $IP_name " ] {
    ## report_utilization -hierarchical -hierarchical_depth 1 -cells $IP_instance -file $output_file -append -quiet
    ## report_property $IP_instance -file $output_file -append -quiet
    ## set report_file [ open $output_file a ]
    ## puts $report_file "\n\n\n"
    ## close $report_file
    ## }
    ## }
    ## } else {
    ## puts "GENERATE_REPORTS: Resource utilization files won't be generated because ADI_GENERATE_UTILIZATION env var is not set"
    ## }
    ##
    ## if {[info exists ::env(ADI_GENERATE_XPA)]} {
    ## set csv_file power_analysis.csv
    ## set Layers "8to11"
    ## set CapLoad "20"
    ## set ToggleRate "15.00000"
    ## set StatProb "0.500000"
    ##
    ## set_load $CapLoad [all_outputs]
    ## set_operating_conditions -board_layers $Layers
    ## set_switching_activity -default_toggle_rate $ToggleRate
    ## set_switching_activity -default_static_probability $StatProb
    ## set_switching_activity -type lut -toggle_rate $ToggleRate -static_probability $StatProb -all
    ## set_switching_activity -type register -toggle_rate $ToggleRate -static_probability $StatProb -all
    ## set_switching_activity -type shift_register -toggle_rate $ToggleRate -static_probability $StatProb -all
    ## set_switching_activity -type lut_ram -toggle_rate $ToggleRate -static_probability $StatProb -all
    ## set_switching_activity -type bram -toggle_rate $ToggleRate -static_probability $StatProb -all
    ## set_switching_activity -type dsp -toggle_rate $ToggleRate -static_probability $StatProb -all
    ## set_switching_activity -type gt_rxdata -toggle_rate $ToggleRate -static_probability $StatProb -all
    ## set_switching_activity -type gt_txdata -toggle_rate $ToggleRate -static_probability $StatProb -all
    ## set_switching_activity -type io_output -toggle_rate $ToggleRate -static_probability $StatProb -all
    ## set_switching_activity -type bram_enable -toggle_rate $ToggleRate -static_probability $StatProb -all
    ## set_switching_activity -type bram_wr_enable -toggle_rate $ToggleRate -static_probability $StatProb -all
    ## set_switching_activity -type io_bidir_enable -toggle_rate $ToggleRate -static_probability $StatProb -all
    ## report_power -file $csv_file
    ##
    ## set fileRead [open $csv_file r]
    ## set filecontent [read $fileRead]
    ## set input_list [split $filecontent "\n"]
    ##
    ## set TextList [lsearch -all -inline $input_list "*Total On-Chip Power (W)*"]
    ## set on_chip_pwr "[lindex [lindex $TextList 0] 6] W"
    ## set TextList [lsearch -all -inline $input_list "*Junction Temperature (C)*"]
    ## set junction_temp "[lindex [lindex $TextList 0] 5] *C"
    ## close $fileRead
    ##
    ## set fileWrite [open $csv_file w]
    ## puts $fileWrite "On-chip_power,Junction_temp"
    ## puts $fileWrite "$on_chip_pwr,$junction_temp"
    ## close $fileWrite
    ## } else {
    ## puts "GENERATE_REPORTS: Power analysis files won't be generated because ADI_GENERATE_XPA env var is not set"
    ## }
    ##
    ## # Look for undefined clocks which do not show up in the timing summary
    ## set timing_check [check_timing -override_defaults no_clock -no_header -return_string]
    ## if {[regexp { (\d+) register} $timing_check -> num_regs]} {
    ##
    ## if {[info exist num_regs]} {
    ## if {$num_regs > 0} {
    ## puts "CRITICAL WARNING: There are $num_regs registers with no clocks !!! See no_clock.log for details."
    ## check_timing -override_defaults no_clock -verbose -file no_clock.log
    ## }
    ## }
    ##
    ## } else {
    ## puts "CRITICAL WARNING: The search for undefined clocks failed !!!"
    ## }
    ##
    ## file mkdir $project_name.sdk
    ##
    ## set timing_string $[report_timing_summary -return_string]
    ## if { [string match "*VIOLATED*" $timing_string] == 1 ||
    ## [string match "*Timing constraints are not met*" $timing_string] == 1} {
    ## write_hw_platform -fixed -force -include_bit -file $project_name.sdk/system_top_bad_timing.xsa
    ## return -code error [format "ERROR: Timing Constraints NOT met!"]
    ## } else {
    ## write_hw_platform -fixed -force -include_bit -file $project_name.sdk/system_top.xsa
    ## }
    ## }
    ## proc adi_project_synth {project_name prcfg_name hdl_files {xdc_files ""}} {
    ##
    ## global p_device
    ##
    ## set p_prefix "$project_name.data/$project_name"
    ##
    ## if {$prcfg_name eq ""} {
    ##
    ## read_verilog .srcs/sources_1/bd/system/hdl/system_wrapper.v
    ## read_verilog $hdl_files
    ## read_xdc $xdc_files
    ##
    ## synth_design -mode default -top system_top -part $p_device > $p_prefix.synth.rds
    ## write_checkpoint -force $p_prefix.synth.dcp
    ## close_project
    ##
    ## } else {
    ##
    ## create_project -in_memory -part $p_device
    ## read_verilog $hdl_files
    ## synth_design -mode out_of_context -top "prcfg" -part $p_device > $p_prefix.${prcfg_name}_synth.rds
    ## write_checkpoint -force $p_prefix.${prcfg_name}_synth.dcp
    ## close_project
    ## }
    ## }
    ## proc adi_project_impl {project_name prcfg_name {xdc_files ""}} {
    ##
    ## global p_device
    ## global p_prcfg_init
    ## global p_prcfg_list
    ## global p_prcfg_status
    ##
    ## set p_prefix "$project_name.data/$project_name"
    ##
    ## if {$prcfg_name eq "default"} {
    ## set p_prcfg_status 0
    ## set p_prcfg_list ""
    ## set p_prcfg_init "$p_prefix.${prcfg_name}_impl.dcp"
    ## file mkdir $project_name.sdk
    ## }
    ##
    ## if {$prcfg_name eq "default"} {
    ##
    ## open_checkpoint $p_prefix.synth.dcp -part $p_device
    ## read_xdc $xdc_files
    ## read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp
    ## set_property HD.RECONFIGURABLE 1 [get_cells i_prcfg]
    ## opt_design > $p_prefix.${prcfg_name}_opt.rds
    ## write_debug_probes -force $p_prefix.${prcfg_name}_debug_nets.ltx
    ## place_design > $p_prefix.${prcfg_name}_place.rds
    ## route_design > $p_prefix.${prcfg_name}_route.rds
    ##
    ## } else {
    ##
    ## open_checkpoint $p_prefix.default_impl_bb.dcp -part $p_device
    ## lock_design -level routing
    ## read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp
    ## read_xdc $xdc_files
    ## opt_design > $p_prefix.${prcfg_name}_opt.rds
    ## place_design > $p_prefix.${prcfg_name}_place.rds
    ## route_design > $p_prefix.${prcfg_name}_route.rds
    ## }
    ##
    ## write_checkpoint -force $p_prefix.${prcfg_name}_impl.dcp
    ## report_utilization -pblocks pb_prcfg -file $p_prefix.${prcfg_name}_utilization.rpt
    ## report_timing_summary -file $p_prefix.${prcfg_name}_timing_summary.rpt
    ##
    ## if [expr [get_property SLACK [get_timing_paths]] < 0] {
    ## set p_prcfg_status 1
    ## puts "CRITICAL WARNING: Timing Constraints NOT met ($prcfg_name)!"
    ## }
    ##
    ## write_checkpoint -force -cell i_prcfg $p_prefix.${prcfg_name}_prcfg_impl.dcp
    ## update_design -cell i_prcfg -black_box
    ## write_checkpoint -force $p_prefix.${prcfg_name}_impl_bb.dcp
    ## open_checkpoint $p_prefix.${prcfg_name}_impl.dcp -part $p_device
    ## write_bitstream -force -bin_file -file $p_prefix.${prcfg_name}.bit
    ## write_sysdef -hwdef $p_prefix.hwdef -bitfile $p_prefix.${prcfg_name}.bit -file $p_prefix.${prcfg_name}.hdf
    ## file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.${prcfg_name}.hdf
    ##
    ## if {$prcfg_name ne "default"} {
    ## lappend p_prcfg_list "$p_prefix.${prcfg_name}_impl.dcp"
    ## }
    ##
    ## if {$prcfg_name eq "default"} {
    ## file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.hdf
    ## }
    ## }
    ## proc adi_project_verify {project_name} {
    ##
    ## # checkpoint for the default design
    ## global p_prcfg_init
    ## # list of checkpoints with all the PRs integrated into the default design
    ## global p_prcfg_list
    ## global p_prcfg_status
    ##
    ## set p_prefix "$project_name.data/$project_name"
    ##
    ## pr_verify -full_check -initial $p_prcfg_init \
    ## -additional $p_prcfg_list \
    ## -file $p_prefix.prcfg_verify.log
    ##
    ## if {$p_prcfg_status == 1} {
    ## return -code error [format "ERROR: Timing Constraints NOT met!"]
    ## }
    ## }
    # source $ad_hdl_dir/projects/scripts/adi_board.tcl
    ## set sys_cpu_interconnect_index 0
    ## set sys_hp0_interconnect_index -1
    ## set sys_hp1_interconnect_index -1
    ## set sys_hp2_interconnect_index -1
    ## set sys_hp3_interconnect_index -1
    ## set sys_mem_interconnect_index -1
    ## set sys_mem_clk_index 0
    ## set xcvr_index -1
    ## set xcvr_tx_index 0
    ## set xcvr_rx_index 0
    ## set xcvr_instance NONE
    ## proc ad_ip_instance {i_ip i_name {i_params {}}} {
    ##
    ## set cell [create_bd_cell -type ip -vlnv [get_ipdefs -all -filter "VLNV =~ *:${i_ip}:* && \
    ## design_tool_contexts =~ *IPI* && UPGRADE_VERSIONS == \"\""] ${i_name}]
    ## if {$i_params != {}} {
    ## set config {}
    ## # Add CONFIG. prefix to all config options
    ## foreach {k v} $i_params {
    ## lappend config "CONFIG.$k" $v
    ## }
    ## set_property -dict $config $cell
    ## }
    ## }
    ## proc ad_ip_parameter {i_name i_param i_value} {
    ##
    ## set_property ${i_param} ${i_value} [get_bd_cells ${i_name}]
    ## }
    ## proc ad_connect_type {p_name} {
    ##
    ## set m_name ""
    ##
    ## if {$m_name eq ""} {set m_name [get_bd_intf_pins -quiet $p_name]}
    ## if {$m_name eq ""} {set m_name [get_bd_pins -quiet $p_name]}
    ## if {$m_name eq ""} {set m_name [get_bd_intf_ports -quiet $p_name]}
    ## if {$m_name eq ""} {set m_name [get_bd_ports -quiet $p_name]}
    ## if {$m_name eq ""} {set m_name [get_bd_intf_nets -quiet $p_name]}
    ## if {$m_name eq ""} {set m_name [get_bd_nets -quiet $p_name]}
    ##
    ## return $m_name
    ## }
    ## proc ad_connect {p_name_1 p_name_2} {
    ##
    ## ## connect an IPI object to GND or VCC
    ## ## instantiate xlconstant with the required width module if there isn't any
    ## ## already
    ## if {($p_name_2 eq "GND") || ($p_name_2 eq "VCC")} {
    ## set p_size 1
    ## set p_msb [get_property left [get_bd_pins $p_name_1]]
    ## set p_lsb [get_property right [get_bd_pins $p_name_1]]
    ## if {($p_msb ne "") && ($p_lsb ne "")} {
    ## set p_size [expr (($p_msb + 1) - $p_lsb)]
    ## }
    ## set p_cell_name "$p_name_2\_$p_size"
    ## if {[get_bd_cells -quiet $p_cell_name] eq ""} {
    ## if {$p_name_2 eq "VCC"} {
    ## set p_value [expr (1 << $p_size) - 1]
    ## } else {
    ## set p_value 0
    ## }
    ## ad_ip_instance xlconstant $p_cell_name
    ## set_property CONFIG.CONST_WIDTH $p_size [get_bd_cells $p_cell_name]
    ## set_property CONFIG.CONST_VAL $p_value [get_bd_cells $p_cell_name]
    ## }
    ## puts "connect_bd_net $p_cell_name/dout $p_name_1"
    ## connect_bd_net [get_bd_pins $p_name_1] [get_bd_pins $p_cell_name/dout]
    ## return
    ## }
    ##
    ## set m_name_1 [ad_connect_type $p_name_1]
    ## set m_name_2 [ad_connect_type $p_name_2]
    ##
    ## if {$m_name_1 eq ""} {
    ## if {[get_property CLASS $m_name_2] eq "bd_intf_pin"} {
    ## puts "create_bd_intf_net $p_name_1"
    ## create_bd_intf_net $p_name_1
    ## }
    ## if {[get_property CLASS $m_name_2] eq "bd_pin"} {
    ## puts "create_bd_net $p_name_1"
    ## create_bd_net $p_name_1
    ## }
    ## set m_name_1 [ad_connect_type $p_name_1]
    ## }
    ##
    ## if {[get_property CLASS $m_name_1] eq "bd_intf_pin"} {
    ## puts "connect_bd_intf_net $m_name_1 $m_name_2"
    ## connect_bd_intf_net $m_name_1 $m_name_2
    ## return
    ## }
    ##
    ## if {[get_property CLASS $m_name_1] eq "bd_pin"} {
    ## puts "connect_bd_net $m_name_1 $m_name_2"
    ## connect_bd_net $m_name_1 $m_name_2
    ## return
    ## }
    ##
    ## if {[get_property CLASS $m_name_1] eq "bd_net"} {
    ## puts "connect_bd_net -net $m_name_1 $m_name_2"
    ## connect_bd_net -net $m_name_1 $m_name_2
    ## return
    ## }
    ## }
    ## proc ad_disconnect {p_name_1 p_name_2} {
    ##
    ## set m_name_1 [ad_connect_type $p_name_1]
    ## set m_name_2 [ad_connect_type $p_name_2]
    ##
    ## if {[get_property CLASS $m_name_1] eq "bd_net"} {
    ## disconnect_bd_net $m_name_1 $m_name_2
    ## return
    ## }
    ##
    ## if {[get_property CLASS $m_name_1] eq "bd_port"} {
    ## delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
    ## [find_bd_objs -relation connected_to $m_name_1]]
    ## delete_bd_objs -quiet $m_name_1
    ## return
    ## }
    ##
    ## if {[get_property CLASS $m_name_1] eq "bd_pin"} {
    ## delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
    ## [find_bd_objs -relation connected_to $m_name_1]]
    ## delete_bd_objs -quiet $m_name_1
    ## return
    ## }
    ## }
    ## proc ad_xcvrcon {u_xcvr a_xcvr a_jesd {lane_map {}} {device_clk {}}} {
    ##
    ## global xcvr_index
    ## global xcvr_tx_index
    ## global xcvr_rx_index
    ## global xcvr_instance
    ##
    ## set no_of_lanes [get_property CONFIG.NUM_OF_LANES [get_bd_cells $a_xcvr]]
    ## set qpll_enable [get_property CONFIG.QPLL_ENABLE [get_bd_cells $a_xcvr]]
    ## set tx_or_rx_n [get_property CONFIG.TX_OR_RX_N [get_bd_cells $a_xcvr]]
    ##
    ## set jesd204_bd_type [get_property TYPE [get_bd_cells $a_jesd]]
    ##
    ## if {$jesd204_bd_type == "hier"} {
    ## set jesd204_type 0
    ## } else {
    ## set jesd204_type 1
    ## }
    ##
    ## if {$xcvr_instance ne $u_xcvr} {
    ## set xcvr_index [expr ($xcvr_index + 1)]
    ## set xcvr_tx_index 0
    ## set xcvr_rx_index 0
    ## set xcvr_instance $u_xcvr
    ## }
    ##
    ## set txrx "rx"
    ## set data_dir "I"
    ## set ctrl_dir "O"
    ## set index $xcvr_rx_index
    ##
    ## if {$tx_or_rx_n == 1} {
    ##
    ## set txrx "tx"
    ## set data_dir "O"
    ## set ctrl_dir "I"
    ## set index $xcvr_tx_index
    ## }
    ##
    ## set m_sysref ${txrx}_sysref_${index}
    ## set m_sync ${txrx}_sync_${index}
    ## set m_data ${txrx}_data
    ##
    ## if {$xcvr_index >= 1} {
    ##
    ## set m_sysref ${txrx}_sysref_${xcvr_index}_${index}
    ## set m_sync ${txrx}_sync_${xcvr_index}_${index}
    ## set m_data ${txrx}_data_${xcvr_index}
    ## }
    ##
    ## if {$jesd204_type == 0} {
    ## set num_of_links [get_property CONFIG.NUM_LINKS [get_bd_cells $a_jesd/$txrx]]
    ## } else {
    ## set num_of_links 1
    ## }
    ##
    ## create_bd_port -dir I $m_sysref
    ## create_bd_port -from [expr $num_of_links - 1] -to 0 -dir ${ctrl_dir} $m_sync
    ##
    ## if {$device_clk == {}} {
    ## set device_clk ${u_xcvr}/${txrx}_out_clk_${index}
    ## set rst_gen [regsub -all "/" ${a_jesd}_rstgen "_"]
    ## set create_rst_gen 1
    ## } else {
    ## set rst_gen ${device_clk}_rstgen
    ## # Only create one reset gen per clock
    ## set create_rst_gen [expr {[get_bd_cells -quiet ${rst_gen}] == {}}]
    ## }
    ##
    ## if {${create_rst_gen}} {
    ## ad_ip_instance proc_sys_reset ${rst_gen}
    ## ad_connect ${device_clk} ${rst_gen}/slowest_sync_clk
    ## ad_connect sys_cpu_resetn ${rst_gen}/ext_reset_in
    ## }
    ##
    ## for {set n 0} {$n < $no_of_lanes} {incr n} {
    ##
    ## set m [expr ($n + $index)]
    ##
    ##
    ## if {$lane_map != {}} {
    ## set phys_lane [lindex $lane_map $n]
    ## } else {
    ## set phys_lane $m
    ## }
    ##
    ## if {$tx_or_rx_n == 0} {
    ## ad_connect ${a_xcvr}/up_es_${n} ${u_xcvr}/up_es_${phys_lane}
    ## if {$jesd204_type == 0} {
    ## ad_connect ${a_jesd}/phy_en_char_align ${u_xcvr}/${txrx}_calign_${phys_lane}
    ## } else {
    ## ad_connect ${a_jesd}/rxencommaalign_out ${u_xcvr}/${txrx}_calign_${phys_lane}
    ## }
    ## }
    ##
    ## if {(($n%4) == 0) && ($qpll_enable == 1)} {
    ## ad_connect ${a_xcvr}/up_cm_${n} ${u_xcvr}/up_cm_${n}
    ## }
    ## ad_connect ${a_xcvr}/up_ch_${n} ${u_xcvr}/up_${txrx}_${phys_lane}
    ## ad_connect ${device_clk} ${u_xcvr}/${txrx}_clk_${phys_lane}
    ## if {$phys_lane != {}} {
    ## if {$jesd204_type == 0} {
    ## ad_connect ${u_xcvr}/${txrx}_${phys_lane} ${a_jesd}/${txrx}_phy${n}
    ## } else {
    ## ad_connect ${u_xcvr}/${txrx}_${phys_lane} ${a_jesd}/gt${n}_${txrx}
    ## }
    ## }
    ##
    ## create_bd_port -dir ${data_dir} ${m_data}_${m}_p
    ## create_bd_port -dir ${data_dir} ${m_data}_${m}_n
    ## ad_connect ${u_xcvr}/${txrx}_${m}_p ${m_data}_${m}_p
    ## ad_connect ${u_xcvr}/${txrx}_${m}_n ${m_data}_${m}_n
    ## }
    ##
    ## if {$jesd204_type == 0} {
    ## ad_connect ${a_jesd}/sysref $m_sysref
    ## ad_connect ${a_jesd}/sync $m_sync
    ## ad_connect ${device_clk} ${a_jesd}/device_clk
    ## } else {
    ## ad_connect ${a_jesd}/${txrx}_sysref $m_sysref
    ## ad_connect ${a_jesd}/${txrx}_sync $m_sync
    ## ad_connect ${device_clk} ${a_jesd}/${txrx}_core_clk
    ## ad_connect ${a_xcvr}/up_status ${a_jesd}/${txrx}_reset_done
    ## ad_connect ${rst_gen}/peripheral_reset ${a_jesd}/${txrx}_reset
    ## }
    ##
    ## if {$tx_or_rx_n == 0} {
    ## set xcvr_rx_index [expr ($xcvr_rx_index + $no_of_lanes)]
    ## }
    ##
    ## if {$tx_or_rx_n == 1} {
    ## set xcvr_tx_index [expr ($xcvr_tx_index + $no_of_lanes)]
    ## }
    ## }
    ## proc ad_xcvrpll {m_src m_dst} {
    ##
    ## foreach p_dst [get_bd_pins -quiet $m_dst] {
    ## connect_bd_net [ad_connect_type $m_src] $p_dst
    ## }
    ## }
    ## proc ad_mem_hp0_interconnect {p_clk p_name} {
    ##
    ## global sys_zynq
    ##
    ## if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP0")} {return}
    ## if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ## if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}
    ## }
    ## proc ad_mem_hp1_interconnect {p_clk p_name} {
    ##
    ## global sys_zynq
    ##
    ## if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP1")} {return}
    ## if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ## if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name}
    ## }
    ## proc ad_mem_hp2_interconnect {p_clk p_name} {
    ##
    ## global sys_zynq
    ##
    ## if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP2")} {return}
    ## if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ## if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name}
    ## }
    ## proc ad_mem_hp3_interconnect {p_clk p_name} {
    ##
    ## global sys_zynq
    ##
    ## if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP3")} {return}
    ## if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ## if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name}
    ## }
    ## proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
    ##
    ## global sys_zynq
    ## global sys_ddr_addr_seg
    ## global sys_hp0_interconnect_index
    ## global sys_hp1_interconnect_index
    ## global sys_hp2_interconnect_index
    ## global sys_hp3_interconnect_index
    ## global sys_mem_interconnect_index
    ## global sys_mem_clk_index
    ##
    ## set p_name_int $p_name
    ## set p_clk_source [get_bd_pins -filter {DIR == O} -of_objects [get_bd_nets $p_clk]]
    ##
    ## if {$p_sel eq "MEM"} {
    ## if {$sys_mem_interconnect_index < 0} {
    ## ad_ip_instance smartconnect axi_mem_interconnect
    ## }
    ## set m_interconnect_index $sys_mem_interconnect_index
    ## set m_interconnect_cell [get_bd_cells axi_mem_interconnect]
    ## set m_addr_seg [get_bd_addr_segs -of_objects [get_bd_cells axi_ddr_cntrl]]
    ## }
    ##
    ## if {($p_sel eq "HP0") && ($sys_zynq == 1)} {
    ## if {$sys_hp0_interconnect_index < 0} {
    ## set p_name_int sys_ps7/S_AXI_HP0
    ## set_property CONFIG.PCW_USE_S_AXI_HP0 {1} [get_bd_cells sys_ps7]
    ## ad_ip_instance smartconnect axi_hp0_interconnect
    ## }
    ## set m_interconnect_index $sys_hp0_interconnect_index
    ## set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
    ## set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM]
    ## }
    ##
    ## if {($p_sel eq "HP1") && ($sys_zynq == 1)} {
    ## if {$sys_hp1_interconnect_index < 0} {
    ## set p_name_int sys_ps7/S_AXI_HP1
    ## set_property CONFIG.PCW_USE_S_AXI_HP1 {1} [get_bd_cells sys_ps7]
    ## ad_ip_instance smartconnect axi_hp1_interconnect
    ## }
    ## set m_interconnect_index $sys_hp1_interconnect_index
    ## set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
    ## set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM]
    ## }
    ##
    ## if {($p_sel eq "HP2") && ($sys_zynq == 1)} {
    ## if {$sys_hp2_interconnect_index < 0} {
    ## set p_name_int sys_ps7/S_AXI_HP2
    ## set_property CONFIG.PCW_USE_S_AXI_HP2 {1} [get_bd_cells sys_ps7]
    ## ad_ip_instance smartconnect axi_hp2_interconnect
    ## }
    ## set m_interconnect_index $sys_hp2_interconnect_index
    ## set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
    ## set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM]
    ## }
    ##
    ## if {($p_sel eq "HP3") && ($sys_zynq == 1)} {
    ## if {$sys_hp3_interconnect_index < 0} {
    ## set p_name_int sys_ps7/S_AXI_HP3
    ## set_property CONFIG.PCW_USE_S_AXI_HP3 {1} [get_bd_cells sys_ps7]
    ## ad_ip_instance smartconnect axi_hp3_interconnect
    ## }
    ## set m_interconnect_index $sys_hp3_interconnect_index
    ## set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
    ## set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM]
    ## }
    ##
    ## if {($p_sel eq "HP0") && ($sys_zynq == 2)} {
    ## if {$sys_hp0_interconnect_index < 0} {
    ## set p_name_int sys_ps8/S_AXI_HP0_FPD
    ## set_property CONFIG.PSU__USE__S_AXI_GP2 {1} [get_bd_cells sys_ps8]
    ## ad_ip_instance smartconnect axi_hp0_interconnect
    ## }
    ## set m_interconnect_index $sys_hp0_interconnect_index
    ## set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
    ## set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_*]
    ## }
    ##
    ## if {($p_sel eq "HP1") && ($sys_zynq == 2)} {
    ## if {$sys_hp1_interconnect_index < 0} {
    ## set p_name_int sys_ps8/S_AXI_HP1_FPD
    ## set_property CONFIG.PSU__USE__S_AXI_GP3 {1} [get_bd_cells sys_ps8]
    ## ad_ip_instance smartconnect axi_hp1_interconnect
    ## }
    ## set m_interconnect_index $sys_hp1_interconnect_index
    ## set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
    ## set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_*]
    ## }
    ##
    ## if {($p_sel eq "HP2") && ($sys_zynq == 2)} {
    ## if {$sys_hp2_interconnect_index < 0} {
    ## set p_name_int sys_ps8/S_AXI_HP2_FPD
    ## set_property CONFIG.PSU__USE__S_AXI_GP4 {1} [get_bd_cells sys_ps8]
    ## ad_ip_instance smartconnect axi_hp2_interconnect
    ## }
    ## set m_interconnect_index $sys_hp2_interconnect_index
    ## set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
    ## set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_*]
    ## }
    ##
    ## if {($p_sel eq "HP3") && ($sys_zynq == 2)} {
    ## if {$sys_hp3_interconnect_index < 0} {
    ## set p_name_int sys_ps8/S_AXI_HP3_FPD
    ## set_property CONFIG.PSU__USE__S_AXI_GP5 {1} [get_bd_cells sys_ps8]
    ## ad_ip_instance smartconnect axi_hp3_interconnect
    ## }
    ## set m_interconnect_index $sys_hp3_interconnect_index
    ## set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
    ## set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP5/HP3_DDR_*]
    ## }
    ##
    ## set i_str "S$m_interconnect_index"
    ## if {$m_interconnect_index < 10} {
    ## set i_str "S0$m_interconnect_index"
    ## }
    ##
    ## set m_interconnect_index [expr $m_interconnect_index + 1]
    ##
    ## set p_intf_name [lrange [split $p_name_int "/"] end end]
    ## set p_cell_name [lrange [split $p_name_int "/"] 0 0]
    ## set p_intf_clock [get_bd_pins -filter "TYPE == clk && (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
    ## CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
    ## CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" -quiet -of_objects [get_bd_cells $p_cell_name]]
    ## if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne "" ||
    ## $p_intf_clock eq $p_clk_source} {
    ## set p_intf_clock ""
    ## }
    ##
    ## regsub clk $p_clk resetn p_rst
    ## if {[get_bd_nets -quiet $p_rst] eq ""} {
    ## set p_rst sys_cpu_resetn
    ## }
    ##
    ## if {$m_interconnect_index == 0} {
    ## set_property CONFIG.NUM_MI 1 $m_interconnect_cell
    ## set_property CONFIG.NUM_SI 1 $m_interconnect_cell
    ## ad_connect $p_rst $m_interconnect_cell/ARESETN
    ## ad_connect $p_clk $m_interconnect_cell/ACLK
    ## ad_connect $m_interconnect_cell/M00_AXI $p_name_int
    ## if {$p_intf_clock ne ""} {
    ## ad_connect $p_clk $p_intf_clock
    ## }
    ## } else {
    ##
    ## set_property CONFIG.NUM_SI $m_interconnect_index $m_interconnect_cell
    ## if {[lsearch [get_bd_nets -of_object [get_bd_pins $m_interconnect_cell/ACLK*]] [get_bd_nets $p_clk]] == -1 } {
    ## incr sys_mem_clk_index
    ## set_property CONFIG.NUM_CLKS [expr $sys_mem_clk_index +1] $m_interconnect_cell
    ## ad_connect $p_clk $m_interconnect_cell/ACLK$sys_mem_clk_index
    ## }
    ## ad_connect $m_interconnect_cell/${i_str}_AXI $p_name_int
    ## if {$p_intf_clock ne ""} {
    ## ad_connect $p_clk $p_intf_clock
    ## }
    ##
    ## set mem_mapped [get_bd_addr_segs -of [get_bd_addr_spaces -of [get_bd_intf_pins -filter {NAME=~ *DLMB*} -of [get_bd_cells /sys_mb]]] -filter {NAME=~ *DDR* || NAME=~ *ddr*}]
    ##
    ## if {$mem_mapped eq ""} {
    ## assign_bd_address $m_addr_seg
    ## } else {
    ## assign_bd_address -offset [get_property OFFSET $mem_mapped] \
    ## -range [get_property RANGE $mem_mapped] $m_addr_seg
    ## }
    ## }
    ##
    ## if {$p_sel eq "MEM"} {set sys_mem_interconnect_index $m_interconnect_index}
    ## if {$p_sel eq "HP0"} {set sys_hp0_interconnect_index $m_interconnect_index}
    ## if {$p_sel eq "HP1"} {set sys_hp1_interconnect_index $m_interconnect_index}
    ## if {$p_sel eq "HP2"} {set sys_hp2_interconnect_index $m_interconnect_index}
    ## if {$p_sel eq "HP3"} {set sys_hp3_interconnect_index $m_interconnect_index}
    ##
    ## }
    ## proc ad_cpu_interconnect {p_address p_name} {
    ##
    ## global sys_zynq
    ## global sys_cpu_interconnect_index
    ##
    ## set i_str "M$sys_cpu_interconnect_index"
    ## if {$sys_cpu_interconnect_index < 10} {
    ## set i_str "M0$sys_cpu_interconnect_index"
    ## }
    ##
    ## if {$sys_cpu_interconnect_index == 0} {
    ## ad_ip_instance axi_interconnect axi_cpu_interconnect
    ## if {$sys_zynq == 2} {
    ## ad_connect sys_cpu_clk sys_ps8/maxihpm0_lpd_aclk
    ## ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
    ## ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
    ## ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
    ## ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
    ## ad_connect axi_cpu_interconnect/S00_AXI sys_ps8/M_AXI_HPM0_LPD
    ## }
    ## if {$sys_zynq == 1} {
    ## ad_connect sys_cpu_clk sys_ps7/M_AXI_GP0_ACLK
    ## ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
    ## ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
    ## ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
    ## ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
    ## ad_connect axi_cpu_interconnect/S00_AXI sys_ps7/M_AXI_GP0
    ## }
    ## if {$sys_zynq == 0} {
    ## ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
    ## ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
    ## ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
    ## ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
    ## ad_connect axi_cpu_interconnect/S00_AXI sys_mb/M_AXI_DP
    ## }
    ## }
    ##
    ## if {$sys_zynq == 2} {
    ## set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps8/Data]
    ## }
    ## if {$sys_zynq == 1} {
    ## set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps7/Data]
    ## }
    ## if {$sys_zynq == 0} {
    ## set sys_addr_cntrl_space [get_bd_addr_spaces sys_mb/Data]
    ## }
    ##
    ## set sys_cpu_interconnect_index [expr $sys_cpu_interconnect_index + 1]
    ##
    ##
    ## set p_cell [get_bd_cells $p_name]
    ## set p_intf [get_bd_intf_pins -filter "MODE == Slave && VLNV == xilinx.com:interface:aximm_rtl:1.0"\
    ## -of_objects $p_cell]
    ##
    ## set p_hier_cell $p_cell
    ## set p_hier_intf $p_intf
    ##
    ## while {$p_hier_intf != "" && [get_property TYPE $p_hier_cell] == "hier"} {
    ## set p_hier_intf [find_bd_objs -boundary_type lower \
    ## -relation connected_to $p_hier_intf]
    ## if {$p_hier_intf != {}} {
    ## set p_hier_cell [get_bd_cells -of_objects $p_hier_intf]
    ## } else {
    ## set p_hier_cell {}
    ## }
    ## }
    ##
    ## set p_intf_clock ""
    ## set p_intf_reset ""
    ##
    ## if {$p_hier_cell != {}} {
    ## set p_intf_name [lrange [split $p_hier_intf "/"] end end]
    ##
    ## set p_intf_clock [get_bd_pins -filter "TYPE == clk && \
    ## (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
    ## CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || \
    ## CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
    ## CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" \
    ## -quiet -of_objects $p_hier_cell]
    ## set p_intf_reset [get_bd_pins -filter "TYPE == rst && \
    ## (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
    ## CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* ||
    ## CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
    ## CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" \
    ## -quiet -of_objects $p_hier_cell]
    ##
    ## if {($p_intf_clock ne "") && ($p_intf_reset eq "")} {
    ## set p_intf_reset [get_property CONFIG.ASSOCIATED_RESET [get_bd_pins ${p_intf_clock}]]
    ## if {$p_intf_reset ne ""} {
    ## set p_intf_reset [get_bd_pins -filter "NAME == $p_intf_reset" -of_objects $p_hier_cell]
    ## }
    ## }
    ##
    ## # Trace back up
    ## set p_hier_cell2 $p_hier_cell
    ##
    ## while {$p_intf_clock != {} && $p_hier_cell2 != $p_cell && $p_hier_cell2 != {}} {
    ## puts $p_intf_clock
    ## puts $p_hier_cell2
    ## set p_intf_clock [find_bd_objs -boundary_type upper \
    ## -relation connected_to $p_intf_clock]
    ## if {$p_intf_clock != {}} {
    ## set p_intf_clock [get_bd_pins [get_property PATH $p_intf_clock]]
    ## set p_hier_cell2 [get_bd_cells -of_objects $p_intf_clock]
    ## }
    ## }
    ##
    ## set p_hier_cell2 $p_hier_cell
    ##
    ## while {$p_intf_reset != {} && $p_hier_cell2 != $p_cell && $p_hier_cell2 != {}} {
    ## set p_intf_reset [find_bd_objs -boundary_type upper \
    ## -relation connected_to $p_intf_reset]
    ## if {$p_intf_reset != {}} {
    ## set p_intf_reset [get_bd_pins [get_property PATH $p_intf_reset]]
    ## set p_hier_cell2 [get_bd_cells -of_objects $p_intf_reset]
    ## }
    ## }
    ## }
    ##
    ##
    ## if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne ""} {
    ## set p_intf_clock ""
    ## }
    ## if {$p_intf_reset ne ""} {
    ## if {[find_bd_objs -quiet -relation connected_to $p_intf_reset] ne ""} {
    ## set p_intf_reset ""
    ## }
    ## }
    ##
    ## set_property CONFIG.NUM_MI $sys_cpu_interconnect_index [get_bd_cells axi_cpu_interconnect]
    ##
    ## ad_connect sys_cpu_clk axi_cpu_interconnect/${i_str}_ACLK
    ## if {$p_intf_clock ne ""} {
    ## ad_connect sys_cpu_clk ${p_intf_clock}
    ## }
    ## ad_connect sys_cpu_resetn axi_cpu_interconnect/${i_str}_ARESETN
    ## if {$p_intf_reset ne ""} {
    ## ad_connect sys_cpu_resetn ${p_intf_reset}
    ## }
    ## ad_connect axi_cpu_interconnect/${i_str}_AXI ${p_intf}
    ##
    ## set p_seg [get_bd_addr_segs -of_objects $p_hier_cell]
    ## set p_index 0
    ## foreach p_seg_name $p_seg {
    ## if {$p_index == 0} {
    ## set p_seg_range [get_property range $p_seg_name]
    ## if {$p_seg_range < 0x1000} {
    ## set p_seg_range 0x1000
    ## }
    ## if {$sys_zynq == 2} {
    ## if {($p_address >= 0x40000000) && ($p_address <= 0x4fffffff)} {
    ## set p_address [expr ($p_address + 0x40000000)]
    ## }
    ## if {($p_address >= 0x70000000) && ($p_address <= 0x7fffffff)} {
    ## set p_address [expr ($p_address + 0x20000000)]
    ## }
    ## }
    ## create_bd_addr_seg -range $p_seg_range \
    ## -offset $p_address $sys_addr_cntrl_space \
    ## $p_seg_name "SEG_data_${p_name}"
    ## } else {
    ## assign_bd_address $p_seg_name
    ## }
    ## incr p_index
    ## }
    ## }
    ## proc ad_cpu_interrupt {p_ps_index p_mb_index p_name} {
    ##
    ## global sys_zynq
    ##
    ## if {$sys_zynq == 0} {set p_index_int $p_mb_index}
    ## if {$sys_zynq >= 1} {set p_index_int $p_ps_index}
    ##
    ## set p_index [regsub -all {[^0-9]} $p_index_int ""]
    ## set m_index [expr ($p_index - 8)]
    ##
    ## if {($sys_zynq == 2) && ($p_index <= 7)} {
    ## set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_0/In$p_index]]
    ## set p_pin [get_bd_pins sys_concat_intc_0/In$p_index]
    ##
    ## puts "disconnect_bd_net $p_net $p_pin"
    ## disconnect_bd_net $p_net $p_pin
    ## ad_connect sys_concat_intc_0/In$p_index $p_name
    ## }
    ##
    ## if {($sys_zynq == 2) && ($p_index >= 8)} {
    ## set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_1/In$m_index]]
    ## set p_pin [get_bd_pins sys_concat_intc_1/In$m_index]
    ##
    ## puts "disconnect_bd_net $p_net $p_pin"
    ## disconnect_bd_net $p_net $p_pin
    ## ad_connect sys_concat_intc_1/In$m_index $p_name
    ## }
    ##
    ## if {$sys_zynq <= 1} {
    ##
    ## set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc/In$p_index]]
    ## set p_pin [get_bd_pins sys_concat_intc/In$p_index]
    ##
    ## puts "disconnect_bd_net $p_net $p_pin"
    ## disconnect_bd_net $p_net $p_pin
    ## ad_connect sys_concat_intc/In$p_index $p_name
    ## }
    ## }
    # adi_project ad9695_fmc_zcu102
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1704] No user IP repositories specified
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/xilinx/Vivado/2020_01/Vivado/2020.1/data/ip'.
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1700] Loaded user IP repository '/project/elisra/irus/work_dir/eladc/irus_work/a.0/fpga/synth/hdl-dev_ad9695/library'.
    WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/project/elisra/irus/work_dir/eladc/irus_work/a.0/fpga/synth/ghdl/library'; Can't find the specified path.
    If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
    ## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
    WARNING: [Common 17-1361] You have specified a new message control rule that is equivalent to an existing rule with attributes ' -id {Vivado 12-1790} -string {{Evaluation} {features} {should} {NOT} {be} {used} {in} {production} {systems.}} -new_severity {WARNING} '. The existing rule will be replaced.
    ## set_msg_config -id {BD 41-1343} -new_severity WARNING
    WARNING: [Common 17-1361] You have specified a new message control rule that is equivalent to an existing rule with attributes ' -id {BD 41-1343} -new_severity {WARNING} '. The existing rule will be replaced.
    ## set_msg_config -id {BD 41-1306} -new_severity WARNING
    WARNING: [Common 17-1361] You have specified a new message control rule that is equivalent to an existing rule with attributes ' -id {BD 41-1306} -new_severity {WARNING} '. The existing rule will be replaced.
    ## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
    ## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
    WARNING: [Common 17-1361] You have specified a new message control rule that is equivalent to an existing rule with attributes ' -id {IP_Flow 19-3656} -new_severity {INFO} '. The existing rule will be replaced.
    ## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
    WARNING: [Common 17-1361] You have specified a new message control rule that is equivalent to an existing rule with attributes ' -id {IP_Flow 19-4623} -new_severity {INFO} '. The existing rule will be replaced.
    ## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
    WARNING: [Common 17-1361] You have specified a new message control rule that is equivalent to an existing rule with attributes ' -id {IP_Flow 19-459} -new_severity {INFO} '. The existing rule will be replaced.
    ## set_msg_config -id {Synth 8-3331} -new_severity INFO
    WARNING: [Common 17-1361] You have specified a new message control rule that is equivalent to an existing rule with attributes ' -id {Synth 8-3331} -new_severity {INFO} '. The existing rule will be replaced.
    ## set_msg_config -id {Synth 8-2490} -new_severity WARNING
    WARNING: [Common 17-1361] You have specified a new message control rule that is equivalent to an existing rule with attributes ' -id {Synth 8-2490} -new_severity {WARNING} '. The existing rule will be replaced.
    ## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
    WARNING: [Common 17-1361] You have specified a new message control rule that is equivalent to an existing rule with attributes ' -id {Designutils 20-3303} -string {{HDPYFinalizeIO}} -new_severity {INFO} '. The existing rule will be replaced.
    ## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
    WARNING: [Common 17-1361] You have specified a new message control rule that is equivalent to an existing rule with attributes ' -id {Place 30-73} -string {{axi_spi}} -new_severity {WARNING} '. The existing rule will be replaced.
    ## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
    WARNING: [Common 17-1361] You have specified a new message control rule that is equivalent to an existing rule with attributes ' -string {{PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY}} -new_severity {WARNING} '. The existing rule will be replaced.
    Wrote : </project/elisra/irus/work_dir/eladc/irus_work/a.0/fpga/synth/hdl-dev_ad9695/projects/ad9695_fmc/zcu102/ad9695_fmc_zcu102.srcs/sources_1/bd/system/system.bd>
    ## set adc_fifo_address_width 14
    ## source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
    ### create_bd_port -dir O -from 2 -to 0 spi0_csn
    ### create_bd_port -dir O spi0_sclk
    ### create_bd_port -dir O spi0_mosi
    ### create_bd_port -dir I spi0_miso
    ### create_bd_port -dir O -from 2 -to 0 spi1_csn
    ### create_bd_port -dir O spi1_sclk
    ### create_bd_port -dir O spi1_mosi
    ### create_bd_port -dir I spi1_miso
    ### create_bd_port -dir I -from 94 -to 0 gpio_i
    ### create_bd_port -dir O -from 94 -to 0 gpio_o
    ### create_bd_port -dir O -from 94 -to 0 gpio_t
    ### ad_ip_instance zynq_ultra_ps_e sys_ps8
    ### apply_bd_automation -rule xilinx.com:bd_rule:zynq_ultra_ps_e \
    ### -config {apply_board_preset 1} [get_bd_cells sys_ps8]
    INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
    ### ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP0 0
    INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
    ### ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP1 0
    INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
    ### ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP2 1
    INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
    ### ad_ip_parameter sys_ps8 CONFIG.PSU__MAXIGP2__DATA_WIDTH 32
    ### ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL0_ENABLE 1
    ### ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL}
    ### ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ 100
    ### ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL1_ENABLE 1
    INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
    ### ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL2_ENABLE 1
    INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
    ### ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL}
    INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
    ### ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ 250
    INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
    ### ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL}
    INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
    ### ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ 500
    INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
    ### ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ0 1
    ### ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ1 1
    ### ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE 1
    INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
    ### set_property -dict [list \
    ### CONFIG.PSU__SPI0__PERIPHERAL__ENABLE 1 \
    ### CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO} \
    ### CONFIG.PSU__SPI0__GRP_SS1__ENABLE 1 \
    ### CONFIG.PSU__SPI0__GRP_SS2__ENABLE 1 \
    ### CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ 100 \
    ### CONFIG.PSU__SPI1__PERIPHERAL__ENABLE 1 \
    ### CONFIG.PSU__SPI1__PERIPHERAL__IO EMIO \
    ### CONFIG.PSU__SPI1__GRP_SS1__ENABLE 1 \
    ### CONFIG.PSU__SPI1__GRP_SS2__ENABLE 1 \
    ### CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ 100 \
    ### ] [get_bd_cells sys_ps8]
    INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
    ### ad_ip_instance proc_sys_reset sys_rstgen
    ### ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
    ### ad_ip_instance proc_sys_reset sys_250m_rstgen
    ### ad_ip_parameter sys_250m_rstgen CONFIG.C_EXT_RST_WIDTH 1
    ### ad_ip_instance proc_sys_reset sys_500m_rstgen
    ### ad_ip_parameter sys_500m_rstgen CONFIG.C_EXT_RST_WIDTH 1
    ### ad_connect sys_cpu_clk sys_ps8/pl_clk0
    create_bd_net sys_cpu_clk
    connect_bd_net -net /sys_cpu_clk /sys_ps8/pl_clk0
    ### ad_connect sys_250m_clk sys_ps8/pl_clk1
    create_bd_net sys_250m_clk
    connect_bd_net -net /sys_250m_clk /sys_ps8/pl_clk1
    ### ad_connect sys_500m_clk sys_ps8/pl_clk2
    create_bd_net sys_500m_clk
    connect_bd_net -net /sys_500m_clk /sys_ps8/pl_clk2
    ### ad_connect sys_ps8/pl_resetn0 sys_rstgen/ext_reset_in
    connect_bd_net /sys_ps8/pl_resetn0 /sys_rstgen/ext_reset_in
    ### ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
    connect_bd_net -net /sys_cpu_clk /sys_rstgen/slowest_sync_clk
    ### ad_connect sys_ps8/pl_resetn0 sys_250m_rstgen/ext_reset_in
    connect_bd_net /sys_ps8/pl_resetn0 /sys_250m_rstgen/ext_reset_in
    ### ad_connect sys_250m_clk sys_250m_rstgen/slowest_sync_clk
    connect_bd_net -net /sys_250m_clk /sys_250m_rstgen/slowest_sync_clk
    ### ad_connect sys_ps8/pl_resetn0 sys_500m_rstgen/ext_reset_in
    connect_bd_net /sys_ps8/pl_resetn0 /sys_500m_rstgen/ext_reset_in
    ### ad_connect sys_500m_clk sys_500m_rstgen/slowest_sync_clk
    connect_bd_net -net /sys_500m_clk /sys_500m_rstgen/slowest_sync_clk
    ### ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
    create_bd_net sys_cpu_reset
    connect_bd_net -net /sys_cpu_reset /sys_rstgen/peripheral_reset
    ### ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
    create_bd_net sys_cpu_resetn
    connect_bd_net -net /sys_cpu_resetn /sys_rstgen/peripheral_aresetn
    ### ad_connect sys_250m_reset sys_250m_rstgen/peripheral_reset
    create_bd_net sys_250m_reset
    connect_bd_net -net /sys_250m_reset /sys_250m_rstgen/peripheral_reset
    ### ad_connect sys_250m_resetn sys_250m_rstgen/peripheral_aresetn
    create_bd_net sys_250m_resetn
    connect_bd_net -net /sys_250m_resetn /sys_250m_rstgen/peripheral_aresetn
    ### ad_connect sys_500m_reset sys_500m_rstgen/peripheral_reset
    create_bd_net sys_500m_reset
    connect_bd_net -net /sys_500m_reset /sys_500m_rstgen/peripheral_reset
    ### ad_connect sys_500m_resetn sys_500m_rstgen/peripheral_aresetn
    create_bd_net sys_500m_resetn
    connect_bd_net -net /sys_500m_resetn /sys_500m_rstgen/peripheral_aresetn
    ### set sys_cpu_clk [get_bd_nets sys_cpu_clk]
    ### set sys_dma_clk [get_bd_nets sys_250m_clk]
    ### set sys_iodelay_clk [get_bd_nets sys_500m_clk]
    ### set sys_cpu_reset [get_bd_nets sys_cpu_reset]
    ### set sys_cpu_resetn [get_bd_nets sys_cpu_resetn]
    ### set sys_dma_reset [get_bd_nets sys_250m_reset]
    ### set sys_dma_resetn [get_bd_nets sys_250m_resetn]
    ### set sys_iodelay_reset [get_bd_nets sys_500m_reset]
    ### set sys_iodelay_resetn [get_bd_nets sys_500m_resetn]
    ### ad_connect gpio_i sys_ps8/emio_gpio_i
    connect_bd_net /gpio_i /sys_ps8/emio_gpio_i
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps8/emio_gpio_i is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0
    ### ad_connect gpio_o sys_ps8/emio_gpio_o
    connect_bd_net /gpio_o /sys_ps8/emio_gpio_o
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps8/emio_gpio_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0
    ### ad_connect gpio_t sys_ps8/emio_gpio_t
    connect_bd_net /gpio_t /sys_ps8/emio_gpio_t
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps8/emio_gpio_t is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0
    ### ad_ip_instance xlconcat spi0_csn_concat
    ### ad_ip_parameter spi0_csn_concat CONFIG.NUM_PORTS 3
    ### ad_connect sys_ps8/emio_spi0_ss_o_n spi0_csn_concat/In0
    connect_bd_net /sys_ps8/emio_spi0_ss_o_n /spi0_csn_concat/In0
    WARNING: [BD 41-1306] The connection to interface pin /sys_ps8/emio_spi0_ss_o_n is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    ### ad_connect sys_ps8/emio_spi0_ss1

  • 0
    •  Analog Employees 
    on Jul 21, 2021 11:42 AM in reply to Inomize

    Hi,

    The last message log you posted seems to be incomplete. Can you add it in a text file?
    I guess you are using a Windows Os, I think If you are building from GUI as the uncompleted log above it should work.
    The sys_is scripts are looking for a git branch, the problem might be:
    1. you don't have git in you environment (should not be a problem for the GUI build)
    2. you have git, but it can't determine a branch. Can you create/checkout a new branch in your local repo before starting a build (git checkout -b test_branch)

    Andrei

  • 0
    •  Analog Employees 
    on Jul 22, 2021 10:25 AM in reply to Inomize

    The log doesn't point to a problem...
    Can you start again with a clean repository?

    Andrei

  • 0
    •  Analog Employees 
    on Jul 22, 2021 10:35 AM in reply to andrei_g

    https://github.com/analogdevicesinc/hdl/commit/8335e1bd9a9884da57384e76c17a72ec30b7dfa3

    If you use the master branch or cherry pick the above commit the git error should be fixed.

    Andrei

  • Hi Andrei,

    It worked! Thank you very much!

    Elad

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