Xilinx Vivado 2020.2.2 with JESD204 library

Hi,

I'm trying to use the JESD204 library from your github (hdl/library/jesd204) in a Vivado 2020.2.2 project (the only version that supports my FPGA). Following the Building HDL Guide, I've got the most of JESD204 blocks and I've been able to include some blocks in the Block Design but, when I try to include the Transport Layer for ADC (ad_ip_jesd204_tpl_adc), Vivado closes itself.

Some scripts to building de blocks have lines with " if {![info exists REQUIRED_VIVADO_VERSION]} {set REQUIRED_VIVADO_VERSION "2020.1"} " and I change them by " if {![info exists REQUIRED_VIVADO_VERSION]} {set REQUIRED_VIVADO_VERSION "2020.2.2"} " because the first one returned an error.

Is this library able to use with Vivado 2020.2.2?

Thank you so much.
Ivan.
  • 0
    •  Analog Employees 
    on Jun 18, 2021 2:40 PM

    Hi Ivan, 

    we do not support yet 2020.2,   we did an initial testing and found issues around timing closure due different optimization levels in this version. Some clock nets are merged and certain timing constraints no longer apply. 

    So you may ran into those issues. 

    We are not aware of the " when I try to include the Transport Layer for ADC (ad_ip_jesd204_tpl_adc), Vivado closes itself" issue.

    Thanks for sharing.

    Laszlo