ADRV9009 DDS frequency setting issue

Hello buddies;

I am using  an adrv9009 evaluation board alongside a custom kintex k160 board, by modifying original reference design. Everything goes well and is working, however there are some issues:

1: 

when I want to set dds frequency using axi_dac_init function in microblaze (Originally it is used in ZYNQ devices as you know) whose default frequency is set to 3MHz, the real generated signal is 1.5MHz and when I set it to whatever like "f" the spectrum analyzer shows f/2. I expect to generate a single tone whose frequency is between - 491.52/2 to 491.52/2 MHz, right?

2:

I am going to inject my own digital signal into the tpl core, in order to this, I deleted dma path and first of all I tried to generated a 2-Lane DDS whose 127-bit data is in this order {I1,Q1,I2,Q2}. Is it correct? (I1 i.e signal_I Odd samples while I2 i.e signal_I Even samples, each in 491.52/2 MHz sampling Rate)

Thank you in advance

Parents
  • Hello, 

    1:  I would check first if the clocks of the link layer and TPL components are correct (lane rate / 40)

    2: The interface of the TPL towards the application layer is described here:

    https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_dac#application_layer_interface

    Laszlo

  • Hello and thank you for your reply.

    I was on the RX side during the time I did not respond you. Anyway, I used your answer for the first question. thank you again.

    For he second question, Unfortunately I still have trouble. I just want to know how is the correct order of the I0,I1,Q0,Q1 when I should concatenate them to inject it to the "JESD204 for DAC" through the path which is connected to the TX dma by default. I couldn't get correct result in spectrum yet

    I created a two-lane DDS in system generator. Surely it has been designed correctly : I checked the output directly in ILA by saving the ila data and checking it within Matlab.

    Then the concatenated data should be injected to the next stage.

    it is a simple example that appeared wrongly: Center frequency is 750MHz and DDS frequency set to 100MHz.

    but the second tone is unwanted and the sign that the order is incorrect. I change the order in all conditions but there was not a correct result at all. (there are 24 states)

  • Hello,

    sorry for this very late reply, we missed your question.

    You can see the mapping of the samples in the following wiki:

    https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_dac

    If all channels are always enabled, you can connect your logic directly to the dac tpl core directly  dac_data_0, dac_data_1 .. ports.   where dac_data_<n> is the nth channel having 32 bits each so 2 samples per beat.

    Thank you,

    Laszlo

  • Hello Inagy,

    This issue made us exhausted!

    Assume I0 means first series of I signal and I1 is the second one. and same for Q0 and Q1

    (if the final rate is 491.52MSPS, I0 and I1 are 245.76MSPS each. samples of I0 and I1 would be read every other .)

    So you mean like this: 

    dac_data_0 = concat(I0,I1) and dac_data_1=concat(Q0,Q1)

    right?

  • Strictly speaking from the DAC TPL point of view, in case of the ADRV9009 design, there are 4 channels/converters (M) on 4 lanes (L).

    Each channel has 32 bits, having 2 samples on each clock cycle since N = 16.

    So the mapping of samples is as follows:

    Clock cycle 0:

    Channel0 - dac_data_0 =  {converter0_sample1, converter0_sample0}

    Channel1 - dac_data_1 =  {converter1_sample1, converter1_sample0}

    Channel2 - dac_data_2 =  {converter2_sample1, converter2_sample0}

    Channel3 - dac_data_3 =  {converter3_sample1, converter3_sample0}

    Clock cycle 1:

    Channel0 - dac_data_0 =  {converter0_sample3, converter0_sample2}

    Channel1 - dac_data_1 =  {converter1_sample3, converter1_sample2}

    Channel2 - dac_data_2 =  {converter2_sample3, converter2_sample2}

    Channel3 - dac_data_3 =  {converter3_sample3, converter3_sample2}

    ...

    The clock (link_clk) at the TPL must mach lane rate / 40

    For start I would connect your logic to this interface, without the unpack core.

    Thank you,

    Laszlo

  • Finally solved by removing unpack core! I don't know what will be happened by this core!

    Thank you!

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