I have a customer trying to sync 4xAD9361 devices using a Zync Ultrascale. Please refer to page 88 of UG-570 for reference.
- Reference clock is 40MHz, provided by a Silicon Labs SI5395
- The traces to the SYNC_IN pins from the FPGA are matched very closely, within a few ns of each other.
- When we did this initially, the phase of the four DATA_CLK outputs is random, every time we restart and do MCS, we get offsets of 1/4,1/2,3/4 clock cycle between the different DATA_CLK out signals.
- Referring to fig 60 and 61 in UG570, we verified that we were meeting set up and hold times for the SYNC_IN signal with respect to the 40MHz clock to the AD9361.
- It's been my experience that sometimes, even the best of datasheets and user guides have errors. We considered that maybe TSC and THC in fig 60,61 should be with respect to the falling edge of REF_CLK, so gave that a try. Wonder of wonders, when we did that, all four DATACLK outputs now align.
- Within the AD9361 HDL code from ADI, there is a signal indicating data valid. This is an output from the first block that interfaces with the AD9361 data. I am having trouble with Xilinx license right now, otherwise would display graph of this block. The customer drives this signal to a GPIO pin to verify MCS. Right now we are seeing random phase shift of 1/4 clock cycle here.
- When customer looks at data from the four AD9361 devices, data is not sync'd, even through the DATA_CLK output pins look to be in sync, though the data valid signals are wandering.
Are there any other conditions or tests that we can run in order to achieve MCS? I need to verify that the customer is providing two sync pulses and clearing and enabling the MCS BBPLL and the MCS Digital CLK enable bits, as described in steps 5,6,7,8 in UG-570.