Looking for clarification about which FPGA families will support the JESD204B interface with an ADRV9008-1 receiver.
Obviously, the XCZU9EG-2FFVB1156 MPSoC works since it is with the ZCU102 board when paired with the ADRV9008 development board.
This document: https://www.analog.com/en/analog-dialogue/articles/quickly-implement-jesd204b.html implies that the preference is to use FPGAs that have GTH or GTX high speed serial transceiver built in.
Would it work with the GTP transceiver available on the Artix-7 series (assuming the desired ADC data throughput is less than the max supported by GTP)?
If so, is the penalty just bandwidth and performance (jitter)?