ADRV9008-1 supported by which families of Xilinx FPGA

Looking for clarification about which FPGA families will support the JESD204B interface with an ADRV9008-1 receiver.

Obviously, the  XCZU9EG-2FFVB1156 MPSoC works since it is with the ZCU102 board when paired with the ADRV9008 development board.

This document: https://www.analog.com/en/analog-dialogue/articles/quickly-implement-jesd204b.html  implies that the preference is to use FPGAs that have GTH or GTX high speed serial transceiver built in.

Would it work with the GTP transceiver available on the Artix-7 series (assuming the desired ADC data throughput is less than the max supported by GTP)? 

If so, is the penalty just bandwidth and performance (jitter)?

Thanks

  • +1
    •  Analog Employees 
    on May 17, 2021 12:07 PM

    Hello,

    At this point we haven't implemented support for GTP transceivers in the physical layer of the JESD204 Interface Framework, that's why we don't support Artix devices. We have a plan to implement support, but it's among a larger list and we don't know exactly when we'll have it available. To my knowledge the GTP transceiver need a slightly different system architecture than the GTX ones, but I suppose the only limitation would be related to maximum bandwidth available. Given that we haven't implemented support, this is more of a theoretical discussion. I think Xilinx may be able to give a more detailed response regarding transceiver limitations.

    Regards,

    Adrian

  • So the answer is that GTP could theoretically be supported, but there is not currently support for it right now.

    Is it a generally true statement for most (all?) high speed ADCs, DACs, and wideband transceivers requiring JESD204B that they require the higher speed GTX and faster serdes?

    Thanks for the clarification.

    -Ryan

  • 0
    •  Analog Employees 
    on May 18, 2021 9:44 AM in reply to boz336

    The GTP transceiver have a maximum rate up to 6.6Gsps and  Artix devices in general have a low number of transceiver banks/pins. Depending on the part, 6.6 GSPS and 2/4 lanes may not be enough to transfer data at the maximum bandwidth supported. If the datarate and available number of lanes are enough for a specific application, I don't see why it wouldn't work. 

    The AC701 development board has only two GTP transceivers populated in the FMC connector.

    Xilinx JESD204B IP supports Artix devices, it's just we don't have a reference design for it and it's not part of the ADI JESD204 Interface Framework (https://wiki.analog.com/resources/fpga/peripherals/jesd204)

    Regards,

    Adrian