I have custom hardware with three ADRV9009 devices connected to a Xilinx Zynq MPSOC ZU6 device. I am using the hdl_2018_R2 components in my block design to create the JESD204B interface to the ADRV9009.
I have initially copied over all the settings from a ZCU102 + ADRV9009 evaluation board reference design. This is working on my custom hardware at 245.76MSPS. For this configuration, I have both the RX and OBS RX transceivers using the CPLL and the TX using QPLL0.
I now want to move my custom hardware to a 208MSPS rate. This equates to a lane rate of 208M x 40 = 8.32Gbps.
According to the Xilinx datasheet, this falls outside the range of QPLL0 for the TX:
However, it does fall within the range of the CPLL and QPLL1. I have been in contact with the Linux embedded group here at EngineerZone and they believe that there is support for running the TX from CPLL/QPLL1 in the device driver.
I would like to find out what I must change in the HDL to run the TX from the CPLL.
Another complication is that the up_pll_rst output of the axi_adrv9009_tx_xcvr is currently connect to the up_qpll_rst_0 and that the axi_adrv9009_rx_xcvr and axi_adrv9009_obs_rx_xcvr connect to up_cpll_rst_0/1/2/3.
Please provide details of what I must change in the HDL block design to run the TX, RX and OBS RX all from the CPLL.
If this is not possible then please provide details of what I must change in the HDL block design to run the TX from QPLL1 instead of QPLL0.