Problem with FMCOMMS2 KC705 build

I was using the KC705 FMCOMMS2 project with Vivado and I have a question.

I had it all built as directed in the instructions and all the repos were built up.  It failed timing, but that is fine for now.

My issue is that I did a write_bd_tcl to file.  I then changed the design name from

# CHANGE DESIGN NAME HERE
variable design_name
set design_name system

to

# CHANGE DESIGN NAME HERE
variable design_name
set design_name BLAHBLAHBLAH

Next, I open up a new project and source the tcl file that was created.  It complains about some of the IP missing and I slowly copy over the ADI IP needed into my project.  Finally it is happy with the repo and throws a final error I can't get past.

can't read "auto_set_param_list": no such variable
ERROR: [BD 41-1273] Error running init TCL procedure: can't read "auto_set_param_list": no such variable
    adi_auto_assign_device_spec Line 18
can't read "auto_set_param_list": no such variable
    while executing
"foreach i $auto_set_param_list {
    if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
      set val [adi_device_spec $cellpath $i]
      set_property..."
    (procedure "adi_auto_assign_device_spec" line 18)
    invoked from within
"adi_auto_assign_device_spec $cellpath"
    (procedure "::analog.com_user_axi_ad9361_1.0::init" line 6)
    invoked from within
"::analog.com_user_axi_ad9361_1.0::init /axi_ad9361 {}"
    invoked from within
"create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361 "
    (procedure "create_root_design" line 94)
    invoked from within
"create_root_design """
    (file "AD9361_export_bd.tcl" line 1202)

Any idea where it is going sideways?  I assume that it has something to do with IP locations not being updated in the script or something.

Parents
  • +1
    •  Analog Employees 
    on Apr 30, 2021 9:12 AM

    Hello, 

    I tried to reproduce what you are seeing with the master branch: 

    1. built the project with make to build all the dependencies in the library

    2. opened the project and exported the block design with the write_bd_tcl

    3. created a new project for the kcu705 carrier

    4. sourced the modified tcl file 

    5. observed the errors about the missing IP files 

    6.  set the repo with the following or from GUI:

    set_property ip_repo_paths /export/data/workspace/ws5/hdl/library [current_project]
    
    update_ip_catalog

    7. source again the tcl file

    8. no errors observed, See log for reference.

    Thanks, 

    Laszlo

    source /media/data/workspace/ws5/hdl/projects/fmcomms2/kc705/myDesign.tcl
    # namespace eval _tcl {
    # proc get_script_folder {} {
    #    set script_path [file normalize [info script]]
    #    set script_folder [file dirname $script_path]
    #    return $script_folder
    # }
    # }
    # variable script_folder
    # set script_folder [_tcl::get_script_folder]
    # set scripts_vivado_version 2020.1
    # set current_vivado_version [version -short]
    # if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
    #    puts ""
    #    catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
    # 
    #    return 1
    # }
    # set list_projs [get_projects -quiet]
    # if { $list_projs eq "" } {
    #    create_project project_1 myproj -part xc7k325tffg900-2
    #    set_property BOARD_PART xilinx.com:kc705:part0:1.6 [current_project]
    # }
    # variable design_name
    # set design_name BLABLA 
    # set errMsg ""
    # set nRet 0
    # set cur_design [current_bd_design -quiet]
    # set list_cells [get_bd_cells -quiet]
    # if { ${design_name} eq "" } {
    #    # USE CASES:
    #    #    1) Design_name not set
    # 
    #    set errMsg "Please set the variable <design_name> to a non-empty value."
    #    set nRet 1
    # 
    # } elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
    #    # USE CASES:
    #    #    2): Current design opened AND is empty AND names same.
    #    #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
    #    #    4): Current design opened AND is empty AND names diff; design_name exists in project.
    # 
    #    if { $cur_design ne $design_name } {
    #       common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
    #       set design_name [get_property NAME $cur_design]
    #    }
    #    common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
    # 
    # } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
    #    # USE CASES:
    #    #    5) Current design opened AND has components AND same names.
    # 
    #    set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
    #    set nRet 1
    # } elseif { [get_files -quiet ${design_name}.bd] ne "" } {
    #    # USE CASES: 
    #    #    6) Current opened design, has components, but diff names, design_name exists in project.
    #    #    7) No opened design, design_name exists in project.
    # 
    #    set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
    #    set nRet 2
    # 
    # } else {
    #    # USE CASES:
    #    #    8) No opened design, design_name not in project.
    #    #    9) Current opened design, has components, but diff names, design_name not in project.
    # 
    #    common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
    # 
    #    create_bd_design $design_name
    # 
    #    common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
    #    current_bd_design $design_name
    # 
    # }
    INFO: [BD::TCL 103-2002] Constructing design in IPI design <BLABLA>...
    # common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
    INFO: [BD::TCL 103-2005] Currently the variable <design_name> is equal to "BLABLA".
    # if { $nRet != 0 } {
    #    catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
    #    return $nRet
    # }
    # set bCheckIPsPassed 1
    # set bCheckIPs 1
    # if { $bCheckIPs == 1 } {
    #    set list_check_ips "\ 
    # xilinx.com:ip:xlconstant:1.1\
    # analog.com:user:axi_ad9361:1.0\
    # analog.com:user:axi_dmac:1.0\
    # analog.com:user:util_rfifo:1.0\
    # xilinx.com:ip:mig_7series:4.2\
    # xilinx.com:ip:axi_ethernetlite:3.0\
    # xilinx.com:ip:axi_gpio:2.0\
    # xilinx.com:ip:axi_iic:2.0\
    # xilinx.com:ip:axi_intc:4.1\
    # xilinx.com:ip:axi_emc:3.0\
    # xilinx.com:ip:smartconnect:1.0\
    # xilinx.com:ip:axi_quad_spi:3.2\
    # analog.com:user:axi_sysid:1.0\
    # xilinx.com:ip:axi_timer:2.0\
    # xilinx.com:ip:axi_uartlite:2.0\
    # analog.com:user:sysid_rom:1.0\
    # xilinx.com:ip:proc_sys_reset:5.0\
    # xilinx.com:ip:xlconcat:2.1\
    # xilinx.com:ip:lmb_v10:3.0\
    # xilinx.com:ip:lmb_bram_if_cntlr:4.0\
    # xilinx.com:ip:blk_mem_gen:8.4\
    # xilinx.com:ip:microblaze:11.0\
    # xilinx.com:ip:mdm:3.2\
    # analog.com:user:util_wfifo:1.0\
    # analog.com:user:util_cpack2:1.0\
    # analog.com:user:util_upack2:1.0\
    # analog.com:user:util_clkdiv:1.0\
    # xilinx.com:ip:util_reduced_logic:2.0\
    # analog.com:user:util_tdd_sync:1.0\
    # "
    # 
    #    set list_ips_missing ""
    #    common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
    # 
    #    foreach ip_vlnv $list_check_ips {
    #       set ip_obj [get_ipdefs -all $ip_vlnv]
    #       if { $ip_obj eq "" } {
    #          lappend list_ips_missing $ip_vlnv
    #       }
    #    }
    # 
    #    if { $list_ips_missing ne "" } {
    #       catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
    #       set bCheckIPsPassed 0
    #    }
    # 
    # }
    INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog:  
    xilinx.com:ip:xlconstant:1.1 analog.com:user:axi_ad9361:1.0 analog.com:user:axi_dmac:1.0 analog.com:user:util_rfifo:1.0 xilinx.com:ip:mig_7series:4.2 xilinx.com:ip:axi_ethernetlite:3.0 xilinx.com:ip:axi_gpio:2.0 xilinx.com:ip:axi_iic:2.0 xilinx.com:ip:axi_intc:4.1 xilinx.com:ip:axi_emc:3.0 xilinx.com:ip:smartconnect:1.0 xilinx.com:ip:axi_quad_spi:3.2 analog.com:user:axi_sysid:1.0 xilinx.com:ip:axi_timer:2.0 xilinx.com:ip:axi_uartlite:2.0 analog.com:user:sysid_rom:1.0 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:xlconcat:2.1 xilinx.com:ip:lmb_v10:3.0 xilinx.com:ip:lmb_bram_if_cntlr:4.0 xilinx.com:ip:blk_mem_gen:8.4 xilinx.com:ip:microblaze:11.0 xilinx.com:ip:mdm:3.2 analog.com:user:util_wfifo:1.0 analog.com:user:util_cpack2:1.0 analog.com:user:util_upack2:1.0 analog.com:user:util_clkdiv:1.0 xilinx.com:ip:util_reduced_logic:2.0 analog.com:user:util_tdd_sync:1.0  .
    # if { $bCheckIPsPassed != 1 } {
    #   common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
    #   return 3
    # }
    # proc write_mig_file_system_axi_ddr_cntrl_0 { str_mig_prj_filepath } {
    # 
    #    file mkdir [ file dirname "$str_mig_prj_filepath" ]
    #    set mig_prj_file [open $str_mig_prj_filepath  w+]
    # 
    #    puts $mig_prj_file {<?xml version='1.0' encoding='UTF-8'?>}
    #    puts $mig_prj_file {<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->}
    #    puts $mig_prj_file {<Project NoOfControllers="1" >}
    #    puts $mig_prj_file {    <ModuleName>system_axi_ddr_cntrl_0</ModuleName>}
    #    puts $mig_prj_file {    <dci_inouts_inputs>1</dci_inouts_inputs>}
    #    puts $mig_prj_file {    <dci_inputs>1</dci_inputs>}
    #    puts $mig_prj_file {    <Debug_En>OFF</Debug_En>}
    #    puts $mig_prj_file {    <DataDepth_En>1024</DataDepth_En>}
    #    puts $mig_prj_file {    <LowPower_En>ON</LowPower_En>}
    #    puts $mig_prj_file {    <XADC_En>Disabled</XADC_En>}
    #    puts $mig_prj_file {    <TargetFPGA>xc7k325t-ffg900/-2</TargetFPGA>}
    #    puts $mig_prj_file {    <Version>2.3</Version>}
    #    puts $mig_prj_file {    <SystemClock>Differential</SystemClock>}
    #    puts $mig_prj_file {    <ReferenceClock>Use System Clock</ReferenceClock>}
    #    puts $mig_prj_file {    <SysResetPolarity>ACTIVE HIGH</SysResetPolarity>}
    #    puts $mig_prj_file {    <BankSelectionFlag>FALSE</BankSelectionFlag>}
    #    puts $mig_prj_file {    <InternalVref>0</InternalVref>}
    #    puts $mig_prj_file {    <dci_hr_inouts_inputs>40 Ohms</dci_hr_inouts_inputs>}
    #    puts $mig_prj_file {    <dci_cascade>1</dci_cascade>}
    #    puts $mig_prj_file {    <Controller number="0" >}
    #    puts $mig_prj_file {        <MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>}
    #    puts $mig_prj_file {        <TimePeriod>1250</TimePeriod>}
    #    puts $mig_prj_file {        <VccAuxIO>2.0V</VccAuxIO>}
    #    puts $mig_prj_file {        <PHYRatio>4:1</PHYRatio>}
    #    puts $mig_prj_file {        <InputClkFreq>200</InputClkFreq>}
    #    puts $mig_prj_file {        <UIExtraClocks>1</UIExtraClocks>}
    #    puts $mig_prj_file {        <MMCM_VCO>800</MMCM_VCO>}
    #    puts $mig_prj_file {        <MMCMClkOut0> 8.000</MMCMClkOut0>}
    #    puts $mig_prj_file {        <MMCMClkOut1>1</MMCMClkOut1>}
    #    puts $mig_prj_file {        <MMCMClkOut2>1</MMCMClkOut2>}
    #    puts $mig_prj_file {        <MMCMClkOut3>1</MMCMClkOut3>}
    #    puts $mig_prj_file {        <MMCMClkOut4>1</MMCMClkOut4>}
    #    puts $mig_prj_file {        <DataWidth>64</DataWidth>}
    #    puts $mig_prj_file {        <DeepMemory>1</DeepMemory>}
    #    puts $mig_prj_file {        <DataMask>1</DataMask>}
    #    puts $mig_prj_file {        <ECC>Disabled</ECC>}
    #    puts $mig_prj_file {        <Ordering>Normal</Ordering>}
    #    puts $mig_prj_file {        <CustomPart>FALSE</CustomPart>}
    #    puts $mig_prj_file {        <NewPartName></NewPartName>}
    #    puts $mig_prj_file {        <RowAddress>14</RowAddress>}
    #    puts $mig_prj_file {        <ColAddress>10</ColAddress>}
    #    puts $mig_prj_file {        <BankAddress>3</BankAddress>}
    #    puts $mig_prj_file {        <MemoryVoltage>1.5V</MemoryVoltage>}
    #    puts $mig_prj_file {        <C0_MEM_SIZE>1073741824</C0_MEM_SIZE>}
    #    puts $mig_prj_file {        <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>}
    #    puts $mig_prj_file {        <PinSelection>}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH12" SLEW="" name="ddr3_addr[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF13" SLEW="" name="ddr3_addr[10]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE13" SLEW="" name="ddr3_addr[11]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ11" SLEW="" name="ddr3_addr[12]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH11" SLEW="" name="ddr3_addr[13]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG13" SLEW="" name="ddr3_addr[1]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG12" SLEW="" name="ddr3_addr[2]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF12" SLEW="" name="ddr3_addr[3]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ12" SLEW="" name="ddr3_addr[4]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ13" SLEW="" name="ddr3_addr[5]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ14" SLEW="" name="ddr3_addr[6]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH14" SLEW="" name="ddr3_addr[7]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK13" SLEW="" name="ddr3_addr[8]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK14" SLEW="" name="ddr3_addr[9]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH9" SLEW="" name="ddr3_ba[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG9" SLEW="" name="ddr3_ba[1]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK9" SLEW="" name="ddr3_ba[2]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC11" SLEW="" name="ddr3_cas_n" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AH10" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AG10" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF10" SLEW="" name="ddr3_cke[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC12" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="Y16" SLEW="" name="ddr3_dm[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB17" SLEW="" name="ddr3_dm[1]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF17" SLEW="" name="ddr3_dm[2]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE16" SLEW="" name="ddr3_dm[3]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK5" SLEW="" name="ddr3_dm[4]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ3" SLEW="" name="ddr3_dm[5]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF6" SLEW="" name="ddr3_dm[6]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC7" SLEW="" name="ddr3_dm[7]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA15" SLEW="" name="ddr3_dq[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC19" SLEW="" name="ddr3_dq[10]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD17" SLEW="" name="ddr3_dq[11]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA18" SLEW="" name="ddr3_dq[12]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AB18" SLEW="" name="ddr3_dq[13]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE18" SLEW="" name="ddr3_dq[14]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD18" SLEW="" name="ddr3_dq[15]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG19" SLEW="" name="ddr3_dq[16]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK19" SLEW="" name="ddr3_dq[17]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG18" SLEW="" name="ddr3_dq[18]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF18" SLEW="" name="ddr3_dq[19]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA16" SLEW="" name="ddr3_dq[1]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH19" SLEW="" name="ddr3_dq[20]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ19" SLEW="" name="ddr3_dq[21]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE19" SLEW="" name="ddr3_dq[22]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD19" SLEW="" name="ddr3_dq[23]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK16" SLEW="" name="ddr3_dq[24]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ17" SLEW="" name="ddr3_dq[25]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG15" SLEW="" name="ddr3_dq[26]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF15" SLEW="" name="ddr3_dq[27]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH17" SLEW="" name="ddr3_dq[28]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG14" SLEW="" name="ddr3_dq[29]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC14" SLEW="" name="ddr3_dq[2]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH15" SLEW="" name="ddr3_dq[30]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK15" SLEW="" name="ddr3_dq[31]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK8" SLEW="" name="ddr3_dq[32]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK6" SLEW="" name="ddr3_dq[33]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG7" SLEW="" name="ddr3_dq[34]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF7" SLEW="" name="ddr3_dq[35]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF8" SLEW="" name="ddr3_dq[36]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK4" SLEW="" name="ddr3_dq[37]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ8" SLEW="" name="ddr3_dq[38]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ6" SLEW="" name="ddr3_dq[39]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD14" SLEW="" name="ddr3_dq[3]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH5" SLEW="" name="ddr3_dq[40]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH6" SLEW="" name="ddr3_dq[41]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ2" SLEW="" name="ddr3_dq[42]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH2" SLEW="" name="ddr3_dq[43]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH4" SLEW="" name="ddr3_dq[44]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ4" SLEW="" name="ddr3_dq[45]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK1" SLEW="" name="ddr3_dq[46]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ1" SLEW="" name="ddr3_dq[47]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF1" SLEW="" name="ddr3_dq[48]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF2" SLEW="" name="ddr3_dq[49]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA17" SLEW="" name="ddr3_dq[4]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE4" SLEW="" name="ddr3_dq[50]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE3" SLEW="" name="ddr3_dq[51]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF3" SLEW="" name="ddr3_dq[52]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF5" SLEW="" name="ddr3_dq[53]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE1" SLEW="" name="ddr3_dq[54]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE5" SLEW="" name="ddr3_dq[55]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC1" SLEW="" name="ddr3_dq[56]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD3" SLEW="" name="ddr3_dq[57]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC4" SLEW="" name="ddr3_dq[58]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC5" SLEW="" name="ddr3_dq[59]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AB15" SLEW="" name="ddr3_dq[5]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE6" SLEW="" name="ddr3_dq[60]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD6" SLEW="" name="ddr3_dq[61]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC2" SLEW="" name="ddr3_dq[62]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD4" SLEW="" name="ddr3_dq[63]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE15" SLEW="" name="ddr3_dq[6]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="Y15" SLEW="" name="ddr3_dq[7]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AB19" SLEW="" name="ddr3_dq[8]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD16" SLEW="" name="ddr3_dq[9]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AC15" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="Y18" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AK18" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ16" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ7" SLEW="" name="ddr3_dqs_n[4]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH1" SLEW="" name="ddr3_dqs_n[5]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG3" SLEW="" name="ddr3_dqs_n[6]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD1" SLEW="" name="ddr3_dqs_n[7]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AC16" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="Y19" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ18" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH16" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH7" SLEW="" name="ddr3_dqs_p[4]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG2" SLEW="" name="ddr3_dqs_p[5]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG4" SLEW="" name="ddr3_dqs_p[6]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD2" SLEW="" name="ddr3_dqs_p[7]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD8" SLEW="" name="ddr3_odt[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD9" SLEW="" name="ddr3_ras_n" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="LVCMOS15" PADName="AK3" SLEW="" name="ddr3_reset_n" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE9" SLEW="" name="ddr3_we_n" IN_TERM="" />}
    #    puts $mig_prj_file {        </PinSelection>}
    #    puts $mig_prj_file {        <System_Clock>}
    #    puts $mig_prj_file {            <Pin PADName="AD12/AD11(CC_P/N)" Bank="33" name="sys_clk_p/n" />}
    #    puts $mig_prj_file {        </System_Clock>}
    #    puts $mig_prj_file {        <System_Control>}
    #    puts $mig_prj_file {            <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />}
    #    puts $mig_prj_file {            <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />}
    #    puts $mig_prj_file {            <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />}
    #    puts $mig_prj_file {        </System_Control>}
    #    puts $mig_prj_file {        <TimingParameters>}
    #    puts $mig_prj_file {            <Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.75" tras="35" trcd="13.75" />}
    #    puts $mig_prj_file {        </TimingParameters>}
    #    puts $mig_prj_file {        <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>}
    #    puts $mig_prj_file {        <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>}
    #    puts $mig_prj_file {        <mrCasLatency name="CAS Latency" >11</mrCasLatency>}
    #    puts $mig_prj_file {        <mrMode name="Mode" >Normal</mrMode>}
    #    puts $mig_prj_file {        <mrDllReset name="DLL Reset" >No</mrDllReset>}
    #    puts $mig_prj_file {        <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>}
    #    puts $mig_prj_file {        <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>}
    #    puts $mig_prj_file {        <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>}
    #    puts $mig_prj_file {        <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>}
    #    puts $mig_prj_file {        <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>}
    #    puts $mig_prj_file {        <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>}
    #    puts $mig_prj_file {        <emrPosted name="Additive Latency (AL)" >0</emrPosted>}
    #    puts $mig_prj_file {        <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>}
    #    puts $mig_prj_file {        <emrDQS name="TDQS enable" >Enabled</emrDQS>}
    #    puts $mig_prj_file {        <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>}
    #    puts $mig_prj_file {        <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>}
    #    puts $mig_prj_file {        <mr2CasWriteLatency name="CAS write latency" >8</mr2CasWriteLatency>}
    #    puts $mig_prj_file {        <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>}
    #    puts $mig_prj_file {        <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>}
    #    puts $mig_prj_file {        <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>}
    #    puts $mig_prj_file {        <PortInterface>AXI</PortInterface>}
    #    puts $mig_prj_file {        <AXIParameters>}
    #    puts $mig_prj_file {            <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>}
    #    puts $mig_prj_file {            <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>}
    #    puts $mig_prj_file {            <C0_S_AXI_DATA_WIDTH>512</C0_S_AXI_DATA_WIDTH>}
    #    puts $mig_prj_file {            <C0_S_AXI_ID_WIDTH>3</C0_S_AXI_ID_WIDTH>}
    #    puts $mig_prj_file {            <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>}
    #    puts $mig_prj_file {        </AXIParameters>}
    #    puts $mig_prj_file {    </Controller>}
    #    puts $mig_prj_file {</Project>}
    # 
    #    close $mig_prj_file
    # }
    # proc create_root_design { parentCell } {
    # 
    #   variable script_folder
    #   variable design_name
    # 
    #   if { $parentCell eq "" } {
    #      set parentCell [get_bd_cells /]
    #   }
    # 
    #   # Get object for parentCell
    #   set parentObj [get_bd_cells $parentCell]
    #   if { $parentObj == "" } {
    #      catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
    #      return
    #   }
    # 
    #   # Make sure parentObj is hier blk
    #   set parentType [get_property TYPE $parentObj]
    #   if { $parentType ne "hier" } {
    #      catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
    #      return
    #   }
    # 
    #   # Save current instance; Restore later
    #   set oldCurInst [current_bd_instance .]
    # 
    #   # Set parent object as current
    #   current_bd_instance $parentObj
    # 
    # 
    #   # Create interface ports
    #   set ddr3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 ]
    # 
    #   set gpio_lcd [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_lcd ]
    # 
    #   set iic_main [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main ]
    # 
    #   set linear_flash [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:emc_rtl:1.0 linear_flash ]
    # 
    #   set mdio [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio ]
    # 
    #   set mii [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mii_rtl:1.0 mii ]
    # 
    # 
    #   # Create ports
    #   set enable [ create_bd_port -dir O enable ]
    #   set gpio0_i [ create_bd_port -dir I -from 31 -to 0 gpio0_i ]
    #   set gpio0_o [ create_bd_port -dir O -from 31 -to 0 gpio0_o ]
    #   set gpio0_t [ create_bd_port -dir O -from 31 -to 0 gpio0_t ]
    #   set gpio1_i [ create_bd_port -dir I -from 31 -to 0 gpio1_i ]
    #   set gpio1_o [ create_bd_port -dir O -from 31 -to 0 gpio1_o ]
    #   set gpio1_t [ create_bd_port -dir O -from 31 -to 0 gpio1_t ]
    #   set rx_clk_in_n [ create_bd_port -dir I rx_clk_in_n ]
    #   set rx_clk_in_p [ create_bd_port -dir I rx_clk_in_p ]
    #   set rx_data_in_n [ create_bd_port -dir I -from 5 -to 0 rx_data_in_n ]
    #   set rx_data_in_p [ create_bd_port -dir I -from 5 -to 0 rx_data_in_p ]
    #   set rx_frame_in_n [ create_bd_port -dir I rx_frame_in_n ]
    #   set rx_frame_in_p [ create_bd_port -dir I rx_frame_in_p ]
    #   set spi_clk_i [ create_bd_port -dir I spi_clk_i ]
    #   set spi_clk_o [ create_bd_port -dir O spi_clk_o ]
    #   set spi_csn_i [ create_bd_port -dir I -from 7 -to 0 spi_csn_i ]
    #   set spi_csn_o [ create_bd_port -dir O -from 7 -to 0 spi_csn_o ]
    #   set spi_sdi_i [ create_bd_port -dir I spi_sdi_i ]
    #   set spi_sdo_i [ create_bd_port -dir I spi_sdo_i ]
    #   set spi_sdo_o [ create_bd_port -dir O spi_sdo_o ]
    #   set sys_clk_n [ create_bd_port -dir I sys_clk_n ]
    #   set sys_clk_p [ create_bd_port -dir I sys_clk_p ]
    #   set sys_rst [ create_bd_port -dir I -type rst sys_rst ]
    #   set_property -dict [ list \
    #    CONFIG.POLARITY {ACTIVE_HIGH} \
    #  ] $sys_rst
    #   set tdd_sync_i [ create_bd_port -dir I tdd_sync_i ]
    #   set tdd_sync_o [ create_bd_port -dir O tdd_sync_o ]
    #   set tdd_sync_t [ create_bd_port -dir O tdd_sync_t ]
    #   set tx_clk_out_n [ create_bd_port -dir O tx_clk_out_n ]
    #   set tx_clk_out_p [ create_bd_port -dir O tx_clk_out_p ]
    #   set tx_data_out_n [ create_bd_port -dir O -from 5 -to 0 tx_data_out_n ]
    #   set tx_data_out_p [ create_bd_port -dir O -from 5 -to 0 tx_data_out_p ]
    #   set tx_frame_out_n [ create_bd_port -dir O tx_frame_out_n ]
    #   set tx_frame_out_p [ create_bd_port -dir O tx_frame_out_p ]
    #   set txnrx [ create_bd_port -dir O txnrx ]
    #   set uart_sin [ create_bd_port -dir I uart_sin ]
    #   set uart_sout [ create_bd_port -dir O uart_sout ]
    #   set up_enable [ create_bd_port -dir I up_enable ]
    #   set up_txnrx [ create_bd_port -dir I up_txnrx ]
    # 
    #   # Create instance: GND_1, and set properties
    #   set GND_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 GND_1 ]
    #   set_property -dict [ list \
    #    CONFIG.CONST_VAL {0} \
    #    CONFIG.CONST_WIDTH {1} \
    #  ] $GND_1
    # 
    #   # Create instance: GND_12, and set properties
    #   set GND_12 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 GND_12 ]
    #   set_property -dict [ list \
    #    CONFIG.CONST_VAL {0} \
    #    CONFIG.CONST_WIDTH {12} \
    #  ] $GND_12
    # 
    #   # Create instance: axi_ad9361, and set properties
    #   set axi_ad9361 [ create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361 ]
    #   set_property -dict [ list \
    #    CONFIG.ADC_INIT_DELAY {31} \
    #    CONFIG.DAC_DDS_CORDIC_DW {14} \
    #    CONFIG.DAC_DDS_TYPE {1} \
    #    CONFIG.ID {0} \
    #  ] $axi_ad9361
    # 
    #   # Create instance: axi_ad9361_adc_dma, and set properties
    #   set axi_ad9361_adc_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma ]
    #   set_property -dict [ list \
    #    CONFIG.AXI_SLICE_DEST {false} \
    #    CONFIG.AXI_SLICE_SRC {false} \
    #    CONFIG.CYCLIC {false} \
    #    CONFIG.DMA_2D_TRANSFER {false} \
    #    CONFIG.DMA_DATA_WIDTH_SRC {64} \
    #    CONFIG.DMA_TYPE_DEST {0} \
    #    CONFIG.DMA_TYPE_SRC {2} \
    #    CONFIG.SYNC_TRANSFER_START {true} \
    #  ] $axi_ad9361_adc_dma
    # 
    #   # Create instance: axi_ad9361_dac_dma, and set properties
    #   set axi_ad9361_dac_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma ]
    #   set_property -dict [ list \
    #    CONFIG.AXI_SLICE_DEST {false} \
    #    CONFIG.AXI_SLICE_SRC {false} \
    #    CONFIG.CYCLIC {true} \
    #    CONFIG.DMA_2D_TRANSFER {false} \
    #    CONFIG.DMA_DATA_WIDTH_DEST {64} \
    #    CONFIG.DMA_TYPE_DEST {1} \
    #    CONFIG.DMA_TYPE_SRC {0} \
    #  ] $axi_ad9361_dac_dma
    # 
    #   # Create instance: axi_ad9361_dac_fifo, and set properties
    #   set axi_ad9361_dac_fifo [ create_bd_cell -type ip -vlnv analog.com:user:util_rfifo:1.0 axi_ad9361_dac_fifo ]
    #   set_property -dict [ list \
    #    CONFIG.DIN_ADDRESS_WIDTH {4} \
    #    CONFIG.DIN_DATA_WIDTH {16} \
    #    CONFIG.DOUT_DATA_WIDTH {16} \
    #  ] $axi_ad9361_dac_fifo
    # 
    #   # Create instance: axi_cpu_interconnect, and set properties
    #   set axi_cpu_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect ]
    #   set_property -dict [ list \
    #    CONFIG.NUM_MI {14} \
    #  ] $axi_cpu_interconnect
    # 
    #   # Create instance: axi_ddr_cntrl, and set properties
    #   set axi_ddr_cntrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.2 axi_ddr_cntrl ]
    # 
    #   # Generate the PRJ File for MIG
    #   set str_mig_folder [get_property IP_DIR [ get_ips [ get_property CONFIG.Component_Name $axi_ddr_cntrl ] ] ]
    #   set str_mig_file_name kc705_system_mig.prj
    #   set str_mig_file_path ${str_mig_folder}/${str_mig_file_name}
    # 
    #   write_mig_file_system_axi_ddr_cntrl_0 $str_mig_file_path
    # 
    #   set_property -dict [ list \
    #    CONFIG.XML_INPUT_FILE {kc705_system_mig.prj} \
    #  ] $axi_ddr_cntrl
    # 
    #   # Create instance: axi_ethernet, and set properties
    #   set axi_ethernet [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernetlite:3.0 axi_ethernet ]
    #   set_property -dict [ list \
    #    CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc} \
    #    CONFIG.MII_BOARD_INTERFACE {mii} \
    #    CONFIG.USE_BOARD_FLOW {true} \
    #  ] $axi_ethernet
    # 
    #   # Create instance: axi_gpio, and set properties
    #   set axi_gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio ]
    #   set_property -dict [ list \
    #    CONFIG.C_GPIO2_WIDTH {32} \
    #    CONFIG.C_GPIO_WIDTH {32} \
    #    CONFIG.C_INTERRUPT_PRESENT {1} \
    #    CONFIG.C_IS_DUAL {1} \
    #  ] $axi_gpio
    # 
    #   # Create instance: axi_gpio_lcd, and set properties
    #   set axi_gpio_lcd [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_lcd ]
    #   set_property -dict [ list \
    #    CONFIG.C_GPIO_WIDTH {7} \
    #    CONFIG.C_INTERRUPT_PRESENT {1} \
    #  ] $axi_gpio_lcd
    # 
    #   # Create instance: axi_iic_main, and set properties
    #   set axi_iic_main [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main ]
    # 
    #   # Create instance: axi_intc, and set properties
    #   set axi_intc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc ]
    #   set_property -dict [ list \
    #    CONFIG.C_HAS_FAST {0} \
    #  ] $axi_intc
    # 
    #   # Create instance: axi_linear_flash, and set properties
    #   set axi_linear_flash [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_emc:3.0 axi_linear_flash ]
    #   set_property -dict [ list \
    #    CONFIG.C_MEM0_TYPE {2} \
    #    CONFIG.C_S_AXI_MEM_ID_WIDTH {0} \
    #    CONFIG.C_TAVDV_PS_MEM_0 {100000} \
    #    CONFIG.C_TCEDV_PS_MEM_0 {100000} \
    #    CONFIG.C_THZCE_PS_MEM_0 {20000} \
    #    CONFIG.C_THZOE_PS_MEM_0 {15000} \
    #    CONFIG.C_TLZWE_PS_MEM_0 {0} \
    #    CONFIG.C_TPACC_PS_FLASH_0 {25000} \
    #    CONFIG.C_TWC_PS_MEM_0 {19000} \
    #    CONFIG.C_TWPH_PS_MEM_0 {20000} \
    #    CONFIG.C_TWP_PS_MEM_0 {50000} \
    #    CONFIG.C_WR_REC_TIME_MEM_0 {0} \
    #    CONFIG.EMC_BOARD_INTERFACE {linear_flash} \
    #    CONFIG.USE_BOARD_FLOW {true} \
    #  ] $axi_linear_flash
    # 
    #   # Create instance: axi_mem_interconnect, and set properties
    #   set axi_mem_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_mem_interconnect ]
    #   set_property -dict [ list \
    #    CONFIG.NUM_CLKS {2} \
    #    CONFIG.NUM_MI {1} \
    #    CONFIG.NUM_SI {4} \
    #  ] $axi_mem_interconnect
    # 
    #   # Create instance: axi_spi, and set properties
    #   set axi_spi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_spi ]
    #   set_property -dict [ list \
    #    CONFIG.C_NUM_SS_BITS {8} \
    #    CONFIG.C_SCK_RATIO {8} \
    #    CONFIG.C_USE_STARTUP {0} \
    #  ] $axi_spi
    # 
    #   # Create instance: axi_sysid_0, and set properties
    #   set axi_sysid_0 [ create_bd_cell -type ip -vlnv analog.com:user:axi_sysid:1.0 axi_sysid_0 ]
    #   set_property -dict [ list \
    #    CONFIG.ROM_ADDR_BITS {9} \
    #  ] $axi_sysid_0
    # 
    #   # Create instance: axi_timer, and set properties
    #   set axi_timer [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer ]
    # 
    #   # Create instance: axi_uart, and set properties
    #   set axi_uart [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart ]
    #   set_property -dict [ list \
    #    CONFIG.C_BAUDRATE {115200} \
    #  ] $axi_uart
    # 
    #   # Create instance: rom_sys_0, and set properties
    #   set rom_sys_0 [ create_bd_cell -type ip -vlnv analog.com:user:sysid_rom:1.0 rom_sys_0 ]
    #   set_property -dict [ list \
    #    CONFIG.PATH_TO_FILE {/export/data/workspace/ws5/hdl/projects/fmcomms2/kc705/mem_init_sys.txt} \
    #    CONFIG.ROM_ADDR_BITS {9} \
    #  ] $rom_sys_0
    # 
    #   # Create instance: sys_200m_rstgen, and set properties
    #   set sys_200m_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_200m_rstgen ]
    #   set_property -dict [ list \
    #    CONFIG.C_EXT_RST_WIDTH {1} \
    #  ] $sys_200m_rstgen
    # 
    #   # Create instance: sys_concat_intc, and set properties
    #   set sys_concat_intc [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc ]
    #   set_property -dict [ list \
    #    CONFIG.NUM_PORTS {16} \
    #  ] $sys_concat_intc
    # 
    #   # Create instance: sys_dlmb, and set properties
    #   set sys_dlmb [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_dlmb ]
    # 
    #   # Create instance: sys_dlmb_cntlr, and set properties
    #   set sys_dlmb_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_dlmb_cntlr ]
    #   set_property -dict [ list \
    #    CONFIG.C_ECC {0} \
    #  ] $sys_dlmb_cntlr
    # 
    #   # Create instance: sys_ilmb, and set properties
    #   set sys_ilmb [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_ilmb ]
    # 
    #   # Create instance: sys_ilmb_cntlr, and set properties
    #   set sys_ilmb_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr ]
    #   set_property -dict [ list \
    #    CONFIG.C_ECC {0} \
    #  ] $sys_ilmb_cntlr
    # 
    #   # Create instance: sys_lmb_bram, and set properties
    #   set sys_lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 sys_lmb_bram ]
    #   set_property -dict [ list \
    #    CONFIG.Memory_Type {True_Dual_Port_RAM} \
    #    CONFIG.use_bram_block {BRAM_Controller} \
    #  ] $sys_lmb_bram
    # 
    #   # Create instance: sys_mb, and set properties
    #   set sys_mb [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:11.0 sys_mb ]
    #   set_property -dict [ list \
    #    CONFIG.G_TEMPLATE_LIST {4} \
    #  ] $sys_mb
    # 
    #   # Create instance: sys_mb_debug, and set properties
    #   set sys_mb_debug [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 sys_mb_debug ]
    #   set_property -dict [ list \
    #    CONFIG.C_USE_UART {1} \
    #  ] $sys_mb_debug
    # 
    #   # Create instance: sys_rstgen, and set properties
    #   set sys_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen ]
    #   set_property -dict [ list \
    #    CONFIG.C_EXT_RST_WIDTH {1} \
    #  ] $sys_rstgen
    # 
    #   # Create instance: util_ad9361_adc_fifo, and set properties
    #   set util_ad9361_adc_fifo [ create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 util_ad9361_adc_fifo ]
    #   set_property -dict [ list \
    #    CONFIG.DIN_ADDRESS_WIDTH {4} \
    #    CONFIG.DIN_DATA_WIDTH {16} \
    #    CONFIG.DOUT_DATA_WIDTH {16} \
    #    CONFIG.NUM_OF_CHANNELS {4} \
    #  ] $util_ad9361_adc_fifo
    # 
    #   # Create instance: util_ad9361_adc_pack, and set properties
    #   set util_ad9361_adc_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack2:1.0 util_ad9361_adc_pack ]
    #   set_property -dict [ list \
    #    CONFIG.NUM_OF_CHANNELS {4} \
    #    CONFIG.SAMPLE_DATA_WIDTH {16} \
    #  ] $util_ad9361_adc_pack
    # 
    #   # Create instance: util_ad9361_dac_upack, and set properties
    #   set util_ad9361_dac_upack [ create_bd_cell -type ip -vlnv analog.com:user:util_upack2:1.0 util_ad9361_dac_upack ]
    #   set_property -dict [ list \
    #    CONFIG.NUM_OF_CHANNELS {4} \
    #    CONFIG.SAMPLE_DATA_WIDTH {16} \
    #  ] $util_ad9361_dac_upack
    # 
    #   # Create instance: util_ad9361_divclk, and set properties
    #   set util_ad9361_divclk [ create_bd_cell -type ip -vlnv analog.com:user:util_clkdiv:1.0 util_ad9361_divclk ]
    # 
    #   # Create instance: util_ad9361_divclk_reset, and set properties
    #   set util_ad9361_divclk_reset [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 util_ad9361_divclk_reset ]
    # 
    #   # Create instance: util_ad9361_divclk_sel, and set properties
    #   set util_ad9361_divclk_sel [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 util_ad9361_divclk_sel ]
    #   set_property -dict [ list \
    #    CONFIG.C_SIZE {2} \
    #  ] $util_ad9361_divclk_sel
    # 
    #   # Create instance: util_ad9361_divclk_sel_concat, and set properties
    #   set util_ad9361_divclk_sel_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 util_ad9361_divclk_sel_concat ]
    #   set_property -dict [ list \
    #    CONFIG.NUM_PORTS {2} \
    #  ] $util_ad9361_divclk_sel_concat
    # 
    #   # Create instance: util_ad9361_tdd_sync, and set properties
    #   set util_ad9361_tdd_sync [ create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync ]
    #   set_property -dict [ list \
    #    CONFIG.TDD_SYNC_PERIOD {10000000} \
    #  ] $util_ad9361_tdd_sync
    # 
    #   # Create interface connections
    #   connect_bd_intf_net -intf_net Conn [get_bd_intf_pins sys_dlmb/LMB_Sl_0] [get_bd_intf_pins sys_dlmb_cntlr/SLMB]
    #   connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins sys_ilmb/LMB_Sl_0] [get_bd_intf_pins sys_ilmb_cntlr/SLMB]
    #   connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DP]
    #   connect_bd_intf_net -intf_net axi_ad9361_adc_dma_m_dest_axi [get_bd_intf_pins axi_ad9361_adc_dma/m_dest_axi] [get_bd_intf_pins axi_mem_interconnect/S02_AXI]
    #   connect_bd_intf_net -intf_net axi_ad9361_dac_dma_m_axis [get_bd_intf_pins axi_ad9361_dac_dma/m_axis] [get_bd_intf_pins util_ad9361_dac_upack/s_axis]
    #   connect_bd_intf_net -intf_net axi_ad9361_dac_dma_m_src_axi [get_bd_intf_pins axi_ad9361_dac_dma/m_src_axi] [get_bd_intf_pins axi_mem_interconnect/S03_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M00_AXI [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins sys_mb_debug/S_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M01_AXI [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_ethernet/S_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M02_AXI [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins axi_gpio_lcd/S_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M03_AXI [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_intc/s_axi]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M04_AXI [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_timer/S_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M05_AXI [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins axi_uart/S_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M06_AXI [get_bd_intf_pins axi_cpu_interconnect/M06_AXI] [get_bd_intf_pins axi_iic_main/S_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M07_AXI [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_sysid_0/s_axi]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M08_AXI [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_gpio/S_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M09_AXI [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_spi/AXI_LITE]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M10_AXI [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_linear_flash/S_AXI_MEM]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M11_AXI [get_bd_intf_pins axi_ad9361/s_axi] [get_bd_intf_pins axi_cpu_interconnect/M11_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M12_AXI [get_bd_intf_pins axi_ad9361_adc_dma/s_axi] [get_bd_intf_pins axi_cpu_interconnect/M12_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M13_AXI [get_bd_intf_pins axi_ad9361_dac_dma/s_axi] [get_bd_intf_pins axi_cpu_interconnect/M13_AXI]
    #   connect_bd_intf_net -intf_net axi_ddr_cntrl_DDR3 [get_bd_intf_ports ddr3] [get_bd_intf_pins axi_ddr_cntrl/DDR3]
    #   connect_bd_intf_net -intf_net axi_ethernet_MDIO [get_bd_intf_ports mdio] [get_bd_intf_pins axi_ethernet/MDIO]
    #   connect_bd_intf_net -intf_net axi_ethernet_MII [get_bd_intf_ports mii] [get_bd_intf_pins axi_ethernet/MII]
    #   connect_bd_intf_net -intf_net axi_gpio_lcd_GPIO [get_bd_intf_ports gpio_lcd] [get_bd_intf_pins axi_gpio_lcd/GPIO]
    #   connect_bd_intf_net -intf_net axi_iic_main_IIC [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_main/IIC]
    #   connect_bd_intf_net -intf_net axi_intc_interrupt [get_bd_intf_pins axi_intc/interrupt] [get_bd_intf_pins sys_mb/INTERRUPT]
    #   connect_bd_intf_net -intf_net axi_linear_flash_EMC_INTF [get_bd_intf_ports linear_flash] [get_bd_intf_pins axi_linear_flash/EMC_INTF]
    #   connect_bd_intf_net -intf_net axi_mem_interconnect_M00_AXI [get_bd_intf_pins axi_ddr_cntrl/S_AXI] [get_bd_intf_pins axi_mem_interconnect/M00_AXI]
    #   connect_bd_intf_net -intf_net sys_dlmb_cntlr_BRAM_PORT [get_bd_intf_pins sys_dlmb_cntlr/BRAM_PORT] [get_bd_intf_pins sys_lmb_bram/BRAM_PORTA]
    #   connect_bd_intf_net -intf_net sys_ilmb_cntlr_BRAM_PORT [get_bd_intf_pins sys_ilmb_cntlr/BRAM_PORT] [get_bd_intf_pins sys_lmb_bram/BRAM_PORTB]
    #   connect_bd_intf_net -intf_net sys_mb_DLMB [get_bd_intf_pins sys_dlmb/LMB_M] [get_bd_intf_pins sys_mb/DLMB]
    #   connect_bd_intf_net -intf_net sys_mb_ILMB [get_bd_intf_pins sys_ilmb/LMB_M] [get_bd_intf_pins sys_mb/ILMB]
    #   connect_bd_intf_net -intf_net sys_mb_M_AXI_DC [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DC]
    #   connect_bd_intf_net -intf_net sys_mb_M_AXI_IC [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins sys_mb/M_AXI_IC]
    #   connect_bd_intf_net -intf_net sys_mb_debug_MBDEBUG_0 [get_bd_intf_pins sys_mb/DEBUG] [get_bd_intf_pins sys_mb_debug/MBDEBUG_0]
    #   connect_bd_intf_net -intf_net util_ad9361_adc_pack_packed_fifo_wr [get_bd_intf_pins axi_ad9361_adc_dma/fifo_wr] [get_bd_intf_pins util_ad9361_adc_pack/packed_fifo_wr]
    # 
    #   # Create port connections
    #   connect_bd_net -net GND_12_dout [get_bd_pins GND_12/dout] [get_bd_pins axi_ddr_cntrl/device_temp_i]
    #   connect_bd_net -net GND_1_dout [get_bd_pins GND_1/dout] [get_bd_pins sys_concat_intc/In2] [get_bd_pins sys_concat_intc/In3] [get_bd_pins sys_concat_intc/In6] [get_bd_pins sys_concat_intc/In7] [get_bd_pins sys_concat_intc/In8] [get_bd_pins sys_concat_intc/In14] [get_bd_pins sys_concat_intc/In15]
    #   connect_bd_net -net axi_ad9361_adc_data_i0 [get_bd_pins axi_ad9361/adc_data_i0] [get_bd_pins util_ad9361_adc_fifo/din_data_0]
    #   connect_bd_net -net axi_ad9361_adc_data_i1 [get_bd_pins axi_ad9361/adc_data_i1] [get_bd_pins util_ad9361_adc_fifo/din_data_2]
    #   connect_bd_net -net axi_ad9361_adc_data_q0 [get_bd_pins axi_ad9361/adc_data_q0] [get_bd_pins util_ad9361_adc_fifo/din_data_1]
    #   connect_bd_net -net axi_ad9361_adc_data_q1 [get_bd_pins axi_ad9361/adc_data_q1] [get_bd_pins util_ad9361_adc_fifo/din_data_3]
    #   connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In12]
    #   connect_bd_net -net axi_ad9361_adc_enable_i0 [get_bd_pins axi_ad9361/adc_enable_i0] [get_bd_pins util_ad9361_adc_fifo/din_enable_0]
    #   connect_bd_net -net axi_ad9361_adc_enable_i1 [get_bd_pins axi_ad9361/adc_enable_i1] [get_bd_pins util_ad9361_adc_fifo/din_enable_2]
    #   connect_bd_net -net axi_ad9361_adc_enable_q0 [get_bd_pins axi_ad9361/adc_enable_q0] [get_bd_pins util_ad9361_adc_fifo/din_enable_1]
    #   connect_bd_net -net axi_ad9361_adc_enable_q1 [get_bd_pins axi_ad9361/adc_enable_q1] [get_bd_pins util_ad9361_adc_fifo/din_enable_3]
    #   connect_bd_net -net axi_ad9361_adc_r1_mode [get_bd_pins axi_ad9361/adc_r1_mode] [get_bd_pins util_ad9361_divclk_sel_concat/In0]
    #   connect_bd_net -net axi_ad9361_adc_valid_i0 [get_bd_pins axi_ad9361/adc_valid_i0] [get_bd_pins util_ad9361_adc_fifo/din_valid_0]
    #   connect_bd_net -net axi_ad9361_adc_valid_i1 [get_bd_pins axi_ad9361/adc_valid_i1] [get_bd_pins util_ad9361_adc_fifo/din_valid_2]
    #   connect_bd_net -net axi_ad9361_adc_valid_q0 [get_bd_pins axi_ad9361/adc_valid_q0] [get_bd_pins util_ad9361_adc_fifo/din_valid_1]
    #   connect_bd_net -net axi_ad9361_adc_valid_q1 [get_bd_pins axi_ad9361/adc_valid_q1] [get_bd_pins util_ad9361_adc_fifo/din_valid_3]
    #   connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In13]
    #   connect_bd_net -net axi_ad9361_dac_enable_i0 [get_bd_pins axi_ad9361/dac_enable_i0] [get_bd_pins axi_ad9361_dac_fifo/dout_enable_0]
    #   connect_bd_net -net axi_ad9361_dac_enable_i1 [get_bd_pins axi_ad9361/dac_enable_i1] [get_bd_pins axi_ad9361_dac_fifo/dout_enable_2]
    #   connect_bd_net -net axi_ad9361_dac_enable_q0 [get_bd_pins axi_ad9361/dac_enable_q0] [get_bd_pins axi_ad9361_dac_fifo/dout_enable_1]
    #   connect_bd_net -net axi_ad9361_dac_enable_q1 [get_bd_pins axi_ad9361/dac_enable_q1] [get_bd_pins axi_ad9361_dac_fifo/dout_enable_3]
    #   connect_bd_net -net axi_ad9361_dac_fifo_din_enable_0 [get_bd_pins axi_ad9361_dac_fifo/din_enable_0] [get_bd_pins util_ad9361_dac_upack/enable_0]
    #   connect_bd_net -net axi_ad9361_dac_fifo_din_enable_1 [get_bd_pins axi_ad9361_dac_fifo/din_enable_1] [get_bd_pins util_ad9361_dac_upack/enable_1]
    #   connect_bd_net -net axi_ad9361_dac_fifo_din_enable_2 [get_bd_pins axi_ad9361_dac_fifo/din_enable_2] [get_bd_pins util_ad9361_dac_upack/enable_2]
    #   connect_bd_net -net axi_ad9361_dac_fifo_din_enable_3 [get_bd_pins axi_ad9361_dac_fifo/din_enable_3] [get_bd_pins util_ad9361_dac_upack/enable_3]
    #   connect_bd_net -net axi_ad9361_dac_fifo_din_valid_0 [get_bd_pins axi_ad9361_dac_fifo/din_valid_0] [get_bd_pins util_ad9361_dac_upack/fifo_rd_en]
    #   connect_bd_net -net axi_ad9361_dac_fifo_dout_data_0 [get_bd_pins axi_ad9361/dac_data_i0] [get_bd_pins axi_ad9361_dac_fifo/dout_data_0]
    #   connect_bd_net -net axi_ad9361_dac_fifo_dout_data_1 [get_bd_pins axi_ad9361/dac_data_q0] [get_bd_pins axi_ad9361_dac_fifo/dout_data_1]
    #   connect_bd_net -net axi_ad9361_dac_fifo_dout_data_2 [get_bd_pins axi_ad9361/dac_data_i1] [get_bd_pins axi_ad9361_dac_fifo/dout_data_2]
    #   connect_bd_net -net axi_ad9361_dac_fifo_dout_data_3 [get_bd_pins axi_ad9361/dac_data_q1] [get_bd_pins axi_ad9361_dac_fifo/dout_data_3]
    #   connect_bd_net -net axi_ad9361_dac_fifo_dout_unf [get_bd_pins axi_ad9361/dac_dunf] [get_bd_pins axi_ad9361_dac_fifo/dout_unf]
    #   connect_bd_net -net axi_ad9361_dac_r1_mode [get_bd_pins axi_ad9361/dac_r1_mode] [get_bd_pins util_ad9361_divclk_sel_concat/In1]
    #   connect_bd_net -net axi_ad9361_dac_valid_i0 [get_bd_pins axi_ad9361/dac_valid_i0] [get_bd_pins axi_ad9361_dac_fifo/dout_valid_0]
    #   connect_bd_net -net axi_ad9361_dac_valid_i1 [get_bd_pins axi_ad9361/dac_valid_i1] [get_bd_pins axi_ad9361_dac_fifo/dout_valid_2]
    #   connect_bd_net -net axi_ad9361_dac_valid_q0 [get_bd_pins axi_ad9361/dac_valid_q0] [get_bd_pins axi_ad9361_dac_fifo/dout_valid_1]
    #   connect_bd_net -net axi_ad9361_dac_valid_q1 [get_bd_pins axi_ad9361/dac_valid_q1] [get_bd_pins axi_ad9361_dac_fifo/dout_valid_3]
    #   connect_bd_net -net axi_ad9361_enable [get_bd_ports enable] [get_bd_pins axi_ad9361/enable]
    #   connect_bd_net -net axi_ad9361_l_clk [get_bd_pins axi_ad9361/clk] [get_bd_pins axi_ad9361/l_clk] [get_bd_pins axi_ad9361_dac_fifo/dout_clk] [get_bd_pins util_ad9361_adc_fifo/din_clk] [get_bd_pins util_ad9361_divclk/clk]
    #   connect_bd_net -net axi_ad9361_rst [get_bd_pins axi_ad9361/rst] [get_bd_pins axi_ad9361_dac_fifo/dout_rst] [get_bd_pins util_ad9361_adc_fifo/din_rst]
    #   connect_bd_net -net axi_ad9361_tdd_sync_cntr [get_bd_ports tdd_sync_t] [get_bd_pins axi_ad9361/tdd_sync_cntr] [get_bd_pins util_ad9361_tdd_sync/sync_mode]
    #   connect_bd_net -net axi_ad9361_tx_clk_out_n [get_bd_ports tx_clk_out_n] [get_bd_pins axi_ad9361/tx_clk_out_n]
    #   connect_bd_net -net axi_ad9361_tx_clk_out_p [get_bd_ports tx_clk_out_p] [get_bd_pins axi_ad9361/tx_clk_out_p]
    #   connect_bd_net -net axi_ad9361_tx_data_out_n [get_bd_ports tx_data_out_n] [get_bd_pins axi_ad9361/tx_data_out_n]
    #   connect_bd_net -net axi_ad9361_tx_data_out_p [get_bd_ports tx_data_out_p] [get_bd_pins axi_ad9361/tx_data_out_p]
    #   connect_bd_net -net axi_ad9361_tx_frame_out_n [get_bd_ports tx_frame_out_n] [get_bd_pins axi_ad9361/tx_frame_out_n]
    #   connect_bd_net -net axi_ad9361_tx_frame_out_p [get_bd_ports tx_frame_out_p] [get_bd_pins axi_ad9361/tx_frame_out_p]
    #   connect_bd_net -net axi_ad9361_txnrx [get_bd_ports txnrx] [get_bd_pins axi_ad9361/txnrx]
    #   connect_bd_net -net axi_ddr_cntrl_mmcm_locked [get_bd_pins axi_ddr_cntrl/mmcm_locked] [get_bd_pins sys_200m_rstgen/dcm_locked] [get_bd_pins sys_rstgen/dcm_locked]
    #   connect_bd_net -net axi_ethernet_ip2intc_irpt [get_bd_pins axi_ethernet/ip2intc_irpt] [get_bd_pins sys_concat_intc/In1]
    #   connect_bd_net -net axi_gpio_gpio2_io_o [get_bd_ports gpio1_o] [get_bd_pins axi_gpio/gpio2_io_o]
    #   connect_bd_net -net axi_gpio_gpio2_io_t [get_bd_ports gpio1_t] [get_bd_pins axi_gpio/gpio2_io_t]
    #   connect_bd_net -net axi_gpio_gpio_io_o [get_bd_ports gpio0_o] [get_bd_pins axi_gpio/gpio_io_o]
    #   connect_bd_net -net axi_gpio_gpio_io_t [get_bd_ports gpio0_t] [get_bd_pins axi_gpio/gpio_io_t]
    #   connect_bd_net -net axi_gpio_ip2intc_irpt [get_bd_pins axi_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In11]
    #   connect_bd_net -net axi_gpio_lcd_ip2intc_irpt [get_bd_pins axi_gpio_lcd/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5]
    #   connect_bd_net -net axi_iic_main_iic2intc_irpt [get_bd_pins axi_iic_main/iic2intc_irpt] [get_bd_pins sys_concat_intc/In9]
    #   connect_bd_net -net axi_spi_io0_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_spi/io0_o]
    #   connect_bd_net -net axi_spi_ip2intc_irpt [get_bd_pins axi_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In10]
    #   connect_bd_net -net axi_spi_sck_o [get_bd_ports spi_clk_o] [get_bd_pins axi_spi/sck_o]
    #   connect_bd_net -net axi_spi_ss_o [get_bd_ports spi_csn_o] [get_bd_pins axi_spi/ss_o]
    #   connect_bd_net -net axi_sysid_0_rom_addr [get_bd_pins axi_sysid_0/rom_addr] [get_bd_pins rom_sys_0/rom_addr]
    #   connect_bd_net -net axi_timer_interrupt [get_bd_pins axi_timer/interrupt] [get_bd_pins sys_concat_intc/In0]
    #   connect_bd_net -net axi_uart_interrupt [get_bd_pins axi_uart/interrupt] [get_bd_pins sys_concat_intc/In4]
    #   connect_bd_net -net axi_uart_tx [get_bd_ports uart_sout] [get_bd_pins axi_uart/tx]
    #   connect_bd_net -net gpio0_i_1 [get_bd_ports gpio0_i] [get_bd_pins axi_gpio/gpio_io_i]
    #   connect_bd_net -net gpio1_i_1 [get_bd_ports gpio1_i] [get_bd_pins axi_gpio/gpio2_io_i]
    #   connect_bd_net -net rom_sys_0_rom_data [get_bd_pins axi_sysid_0/sys_rom_data] [get_bd_pins rom_sys_0/rom_data]
    #   connect_bd_net -net rx_clk_in_n_1 [get_bd_ports rx_clk_in_n] [get_bd_pins axi_ad9361/rx_clk_in_n]
    #   connect_bd_net -net rx_clk_in_p_1 [get_bd_ports rx_clk_in_p] [get_bd_pins axi_ad9361/rx_clk_in_p]
    #   connect_bd_net -net rx_data_in_n_1 [get_bd_ports rx_data_in_n] [get_bd_pins axi_ad9361/rx_data_in_n]
    #   connect_bd_net -net rx_data_in_p_1 [get_bd_ports rx_data_in_p] [get_bd_pins axi_ad9361/rx_data_in_p]
    #   connect_bd_net -net rx_frame_in_n_1 [get_bd_ports rx_frame_in_n] [get_bd_pins axi_ad9361/rx_frame_in_n]
    #   connect_bd_net -net rx_frame_in_p_1 [get_bd_ports rx_frame_in_p] [get_bd_pins axi_ad9361/rx_frame_in_p]
    #   connect_bd_net -net spi_clk_i_1 [get_bd_ports spi_clk_i] [get_bd_pins axi_spi/sck_i]
    #   connect_bd_net -net spi_csn_i_1 [get_bd_ports spi_csn_i] [get_bd_pins axi_spi/ss_i]
    #   connect_bd_net -net spi_sdi_i_1 [get_bd_ports spi_sdi_i] [get_bd_pins axi_spi/io1_i]
    #   connect_bd_net -net spi_sdo_i_1 [get_bd_ports spi_sdo_i] [get_bd_pins axi_spi/io0_i]
    #   connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9361/delay_clk] [get_bd_pins axi_ddr_cntrl/ui_clk] [get_bd_pins axi_mem_interconnect/aclk] [get_bd_pins sys_200m_rstgen/slowest_sync_clk]
    #   connect_bd_net -net sys_200m_reset [get_bd_pins sys_200m_rstgen/peripheral_reset]
    #   connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/aresetn] [get_bd_pins sys_200m_rstgen/peripheral_aresetn]
    #   connect_bd_net -net sys_200m_rst [get_bd_pins axi_ddr_cntrl/ui_clk_sync_rst] [get_bd_pins sys_200m_rstgen/ext_reset_in]
    #   connect_bd_net -net sys_clk_n_1 [get_bd_ports sys_clk_n] [get_bd_pins axi_ddr_cntrl/sys_clk_n]
    #   connect_bd_net -net sys_clk_p_1 [get_bd_ports sys_clk_p] [get_bd_pins axi_ddr_cntrl/sys_clk_p]
    #   connect_bd_net -net sys_concat_intc_dout [get_bd_pins axi_intc/intr] [get_bd_pins sys_concat_intc/dout]
    #   connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ad9361/s_axi_aclk] [get_bd_pins axi_ad9361_adc_dma/m_dest_axi_aclk] [get_bd_pins axi_ad9361_adc_dma/s_axi_aclk] [get_bd_pins axi_ad9361_dac_dma/m_src_axi_aclk] [get_bd_pins axi_ad9361_dac_dma/s_axi_aclk] [get_bd_pins axi_cpu_interconnect/ACLK] [get_bd_pins axi_cpu_interconnect/M00_ACLK] [get_bd_pins axi_cpu_interconnect/M01_ACLK] [get_bd_pins axi_cpu_interconnect/M02_ACLK] [get_bd_pins axi_cpu_interconnect/M03_ACLK] [get_bd_pins axi_cpu_interconnect/M04_ACLK] [get_bd_pins axi_cpu_interconnect/M05_ACLK] [get_bd_pins axi_cpu_interconnect/M06_ACLK] [get_bd_pins axi_cpu_interconnect/M07_ACLK] [get_bd_pins axi_cpu_interconnect/M08_ACLK] [get_bd_pins axi_cpu_interconnect/M09_ACLK] [get_bd_pins axi_cpu_interconnect/M10_ACLK] [get_bd_pins axi_cpu_interconnect/M11_ACLK] [get_bd_pins axi_cpu_interconnect/M12_ACLK] [get_bd_pins axi_cpu_interconnect/M13_ACLK] [get_bd_pins axi_cpu_interconnect/S00_ACLK] [get_bd_pins axi_ddr_cntrl/ui_addn_clk_0] [get_bd_pins axi_ethernet/s_axi_aclk] [get_bd_pins axi_gpio/s_axi_aclk] [get_bd_pins axi_gpio_lcd/s_axi_aclk] [get_bd_pins axi_iic_main/s_axi_aclk] [get_bd_pins axi_intc/s_axi_aclk] [get_bd_pins axi_linear_flash/rdclk] [get_bd_pins axi_linear_flash/s_axi_aclk] [get_bd_pins axi_mem_interconnect/aclk1] [get_bd_pins axi_spi/ext_spi_clk] [get_bd_pins axi_spi/s_axi_aclk] [get_bd_pins axi_sysid_0/s_axi_aclk] [get_bd_pins axi_timer/s_axi_aclk] [get_bd_pins axi_uart/s_axi_aclk] [get_bd_pins rom_sys_0/clk] [get_bd_pins sys_dlmb/LMB_Clk] [get_bd_pins sys_dlmb_cntlr/LMB_Clk] [get_bd_pins sys_ilmb/LMB_Clk] [get_bd_pins sys_ilmb_cntlr/LMB_Clk] [get_bd_pins sys_mb/Clk] [get_bd_pins sys_mb_debug/S_AXI_ACLK] [get_bd_pins sys_rstgen/slowest_sync_clk] [get_bd_pins util_ad9361_tdd_sync/clk]
    #   connect_bd_net -net sys_cpu_reset [get_bd_pins sys_rstgen/peripheral_reset]
    #   connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_ad9361/s_axi_aresetn] [get_bd_pins axi_ad9361_adc_dma/m_dest_axi_aresetn] [get_bd_pins axi_ad9361_adc_dma/s_axi_aresetn] [get_bd_pins axi_ad9361_dac_dma/m_src_axi_aresetn] [get_bd_pins axi_ad9361_dac_dma/s_axi_aresetn] [get_bd_pins axi_cpu_interconnect/ARESETN] [get_bd_pins axi_cpu_interconnect/M00_ARESETN] [get_bd_pins axi_cpu_interconnect/M01_ARESETN] [get_bd_pins axi_cpu_interconnect/M02_ARESETN] [get_bd_pins axi_cpu_interconnect/M03_ARESETN] [get_bd_pins axi_cpu_interconnect/M04_ARESETN] [get_bd_pins axi_cpu_interconnect/M05_ARESETN] [get_bd_pins axi_cpu_interconnect/M06_ARESETN] [get_bd_pins axi_cpu_interconnect/M07_ARESETN] [get_bd_pins axi_cpu_interconnect/M08_ARESETN] [get_bd_pins axi_cpu_interconnect/M09_ARESETN] [get_bd_pins axi_cpu_interconnect/M10_ARESETN] [get_bd_pins axi_cpu_interconnect/M11_ARESETN] [get_bd_pins axi_cpu_interconnect/M12_ARESETN] [get_bd_pins axi_cpu_interconnect/M13_ARESETN] [get_bd_pins axi_cpu_interconnect/S00_ARESETN] [get_bd_pins axi_ddr_cntrl/aresetn] [get_bd_pins axi_ethernet/s_axi_aresetn] [get_bd_pins axi_gpio/s_axi_aresetn] [get_bd_pins axi_gpio_lcd/s_axi_aresetn] [get_bd_pins axi_iic_main/s_axi_aresetn] [get_bd_pins axi_intc/s_axi_aresetn] [get_bd_pins axi_linear_flash/s_axi_aresetn] [get_bd_pins axi_spi/s_axi_aresetn] [get_bd_pins axi_sysid_0/s_axi_aresetn] [get_bd_pins axi_timer/s_axi_aresetn] [get_bd_pins axi_uart/s_axi_aresetn] [get_bd_pins sys_mb_debug/S_AXI_ARESETN] [get_bd_pins sys_rstgen/peripheral_aresetn] [get_bd_pins util_ad9361_divclk_reset/ext_reset_in] [get_bd_pins util_ad9361_tdd_sync/rstn]
    #   connect_bd_net -net sys_mb_debug_Debug_SYS_Rst [get_bd_pins sys_mb_debug/Debug_SYS_Rst] [get_bd_pins sys_rstgen/mb_debug_sys_rst]
    #   connect_bd_net -net sys_rst_1 [get_bd_ports sys_rst] [get_bd_pins axi_ddr_cntrl/sys_rst] [get_bd_pins sys_rstgen/ext_reset_in]
    #   connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_dlmb/SYS_Rst] [get_bd_pins sys_dlmb_cntlr/LMB_Rst] [get_bd_pins sys_ilmb/SYS_Rst] [get_bd_pins sys_ilmb_cntlr/LMB_Rst] [get_bd_pins sys_rstgen/bus_struct_reset]
    #   connect_bd_net -net sys_rstgen_mb_reset [get_bd_pins sys_mb/Reset] [get_bd_pins sys_rstgen/mb_reset]
    #   connect_bd_net -net tdd_sync_i_1 [get_bd_ports tdd_sync_i] [get_bd_pins util_ad9361_tdd_sync/sync_in]
    #   connect_bd_net -net uart_sin_1 [get_bd_ports uart_sin] [get_bd_pins axi_uart/rx]
    #   connect_bd_net -net up_enable_1 [get_bd_ports up_enable] [get_bd_pins axi_ad9361/up_enable]
    #   connect_bd_net -net up_txnrx_1 [get_bd_ports up_txnrx] [get_bd_pins axi_ad9361/up_txnrx]
    #   connect_bd_net -net util_ad9361_adc_fifo_din_ovf [get_bd_pins axi_ad9361/adc_dovf] [get_bd_pins util_ad9361_adc_fifo/din_ovf]
    #   connect_bd_net -net util_ad9361_adc_fifo_dout_data_0 [get_bd_pins util_ad9361_adc_fifo/dout_data_0] [get_bd_pins util_ad9361_adc_pack/fifo_wr_data_0]
    #   connect_bd_net -net util_ad9361_adc_fifo_dout_data_1 [get_bd_pins util_ad9361_adc_fifo/dout_data_1] [get_bd_pins util_ad9361_adc_pack/fifo_wr_data_1]
    #   connect_bd_net -net util_ad9361_adc_fifo_dout_data_2 [get_bd_pins util_ad9361_adc_fifo/dout_data_2] [get_bd_pins util_ad9361_adc_pack/fifo_wr_data_2]
    #   connect_bd_net -net util_ad9361_adc_fifo_dout_data_3 [get_bd_pins util_ad9361_adc_fifo/dout_data_3] [get_bd_pins util_ad9361_adc_pack/fifo_wr_data_3]
    #   connect_bd_net -net util_ad9361_adc_fifo_dout_enable_0 [get_bd_pins util_ad9361_adc_fifo/dout_enable_0] [get_bd_pins util_ad9361_adc_pack/enable_0]
    #   connect_bd_net -net util_ad9361_adc_fifo_dout_enable_1 [get_bd_pins util_ad9361_adc_fifo/dout_enable_1] [get_bd_pins util_ad9361_adc_pack/enable_1]
    #   connect_bd_net -net util_ad9361_adc_fifo_dout_enable_2 [get_bd_pins util_ad9361_adc_fifo/dout_enable_2] [get_bd_pins util_ad9361_adc_pack/enable_2]
    #   connect_bd_net -net util_ad9361_adc_fifo_dout_enable_3 [get_bd_pins util_ad9361_adc_fifo/dout_enable_3] [get_bd_pins util_ad9361_adc_pack/enable_3]
    #   connect_bd_net -net util_ad9361_adc_fifo_dout_valid_0 [get_bd_pins util_ad9361_adc_fifo/dout_valid_0] [get_bd_pins util_ad9361_adc_pack/fifo_wr_en]
    #   connect_bd_net -net util_ad9361_adc_pack_fifo_wr_overflow [get_bd_pins util_ad9361_adc_fifo/dout_ovf] [get_bd_pins util_ad9361_adc_pack/fifo_wr_overflow]
    #   connect_bd_net -net util_ad9361_dac_upack_fifo_rd_data_0 [get_bd_pins axi_ad9361_dac_fifo/din_data_0] [get_bd_pins util_ad9361_dac_upack/fifo_rd_data_0]
    #   connect_bd_net -net util_ad9361_dac_upack_fifo_rd_data_1 [get_bd_pins axi_ad9361_dac_fifo/din_data_1] [get_bd_pins util_ad9361_dac_upack/fifo_rd_data_1]
    #   connect_bd_net -net util_ad9361_dac_upack_fifo_rd_data_2 [get_bd_pins axi_ad9361_dac_fifo/din_data_2] [get_bd_pins util_ad9361_dac_upack/fifo_rd_data_2]
    #   connect_bd_net -net util_ad9361_dac_upack_fifo_rd_data_3 [get_bd_pins axi_ad9361_dac_fifo/din_data_3] [get_bd_pins util_ad9361_dac_upack/fifo_rd_data_3]
    #   connect_bd_net -net util_ad9361_dac_upack_fifo_rd_underflow [get_bd_pins axi_ad9361_dac_fifo/din_unf] [get_bd_pins util_ad9361_dac_upack/fifo_rd_underflow]
    #   connect_bd_net -net util_ad9361_dac_upack_fifo_rd_valid [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_0] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_1] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_2] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_3] [get_bd_pins util_ad9361_dac_upack/fifo_rd_valid]
    #   connect_bd_net -net util_ad9361_divclk_clk_out [get_bd_pins axi_ad9361_adc_dma/fifo_wr_clk] [get_bd_pins axi_ad9361_dac_dma/m_axis_aclk] [get_bd_pins axi_ad9361_dac_fifo/din_clk] [get_bd_pins util_ad9361_adc_fifo/dout_clk] [get_bd_pins util_ad9361_adc_pack/clk] [get_bd_pins util_ad9361_dac_upack/clk] [get_bd_pins util_ad9361_divclk/clk_out] [get_bd_pins util_ad9361_divclk_reset/slowest_sync_clk]
    #   connect_bd_net -net util_ad9361_divclk_reset_peripheral_aresetn [get_bd_pins axi_ad9361_dac_fifo/din_rstn] [get_bd_pins util_ad9361_adc_fifo/dout_rstn] [get_bd_pins util_ad9361_divclk_reset/peripheral_aresetn]
    #   connect_bd_net -net util_ad9361_divclk_reset_peripheral_reset [get_bd_pins util_ad9361_adc_pack/reset] [get_bd_pins util_ad9361_dac_upack/reset] [get_bd_pins util_ad9361_divclk_reset/peripheral_reset]
    #   connect_bd_net -net util_ad9361_divclk_sel_Res [get_bd_pins util_ad9361_divclk/clk_sel] [get_bd_pins util_ad9361_divclk_sel/Res]
    #   connect_bd_net -net util_ad9361_divclk_sel_concat_dout [get_bd_pins util_ad9361_divclk_sel/Op1] [get_bd_pins util_ad9361_divclk_sel_concat/dout]
    #   connect_bd_net -net util_ad9361_tdd_sync_sync_out [get_bd_ports tdd_sync_o] [get_bd_pins axi_ad9361/tdd_sync] [get_bd_pins util_ad9361_tdd_sync/sync_out]
    # 
    #   # Create address segments
    #   assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces axi_ad9361_adc_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] -force
    #   assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces axi_ad9361_dac_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] -force
    #   assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] -force
    #   assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] -force
    #   assign_bd_address -offset 0x79020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ad9361/s_axi/axi_lite] -force
    #   assign_bd_address -offset 0x7C400000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ad9361_adc_dma/s_axi/axi_lite] -force
    #   assign_bd_address -offset 0x7C420000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ad9361_dac_dma/s_axi/axi_lite] -force
    #   assign_bd_address -offset 0x40E00000 -range 0x00002000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ethernet/S_AXI/Reg] -force
    #   assign_bd_address -offset 0x40000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_gpio/S_AXI/Reg] -force
    #   assign_bd_address -offset 0x40010000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_gpio_lcd/S_AXI/Reg] -force
    #   assign_bd_address -offset 0x41600000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_iic_main/S_AXI/Reg] -force
    #   assign_bd_address -offset 0x41200000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_intc/S_AXI/Reg] -force
    #   assign_bd_address -offset 0x60000000 -range 0x02000000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_linear_flash/S_AXI_MEM/Mem0] -force
    #   assign_bd_address -offset 0x44A70000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_spi/AXI_LITE/Reg] -force
    #   assign_bd_address -offset 0x45000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_sysid_0/s_axi/axi_lite] -force
    #   assign_bd_address -offset 0x41C00000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_timer/S_AXI/Reg] -force
    #   assign_bd_address -offset 0x40600000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_uart/S_AXI/Reg] -force
    #   assign_bd_address -offset 0x41400000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs sys_mb_debug/S_AXI/Reg] -force
    #   assign_bd_address -offset 0x00000000 -range 0x00020000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] -force
    #   assign_bd_address -offset 0x00000000 -range 0x00020000 -target_address_space [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] -force
    # 
    # 
    #   # Restore current instance
    #   current_bd_instance $oldCurInst
    # 
    #   validate_bd_design
    #   save_bd_design
    # }
    # create_root_design ""
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [BD 41-1753] The name 'util_ad9361_divclk_sel_concat' you have specified is long. The Windows OS has path length limitations. It is recommended you use shorter names(less than 25 characters) to reduce the likelihood of issues when/if running on windows OS.
    WARNING: [BD 41-1306] The connection to interface pin /axi_gpio/gpio2_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO2
    WARNING: [BD 41-1306] The connection to interface pin /axi_gpio/gpio2_io_t is being overridden by the user. This pin will not be connected as a part of interface connection GPIO2
    WARNING: [BD 41-1306] The connection to interface pin /axi_gpio/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
    WARNING: [BD 41-1306] The connection to interface pin /axi_gpio/gpio_io_t is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
    WARNING: [BD 41-1306] The connection to interface pin /axi_spi/io0_o is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    WARNING: [BD 41-1306] The connection to interface pin /axi_spi/sck_o is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    WARNING: [BD 41-1306] The connection to interface pin /axi_spi/ss_o is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    WARNING: [BD 41-1306] The connection to interface pin /axi_uart/tx is being overridden by the user. This pin will not be connected as a part of interface connection UART
    WARNING: [BD 41-1306] The connection to interface pin /axi_gpio/gpio_io_i is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
    WARNING: [BD 41-1306] The connection to interface pin /axi_gpio/gpio2_io_i is being overridden by the user. This pin will not be connected as a part of interface connection GPIO2
    WARNING: [BD 41-1306] The connection to interface pin /axi_spi/sck_i is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    WARNING: [BD 41-1306] The connection to interface pin /axi_spi/ss_i is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    WARNING: [BD 41-1306] The connection to interface pin /axi_spi/io1_i is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    WARNING: [BD 41-1306] The connection to interface pin /axi_spi/io0_i is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    WARNING: [BD 41-1306] The connection to interface pin /axi_ddr_cntrl/sys_clk_n is being overridden by the user. This pin will not be connected as a part of interface connection SYS_CLK
    WARNING: [BD 41-1306] The connection to interface pin /axi_ddr_cntrl/sys_clk_p is being overridden by the user. This pin will not be connected as a part of interface connection SYS_CLK
    WARNING: [BD 41-1306] The connection to interface pin /axi_uart/rx is being overridden by the user. This pin will not be connected as a part of interface connection UART
    Slave segment '/axi_ddr_cntrl/memmap/memaddr' is being assigned into address space '/axi_ad9361_adc_dma/m_dest_axi' at <0x8000_0000 [ 1G ]>.
    Slave segment '/axi_ddr_cntrl/memmap/memaddr' is being assigned into address space '/axi_ad9361_dac_dma/m_src_axi' at <0x8000_0000 [ 1G ]>.
    Slave segment '/axi_ddr_cntrl/memmap/memaddr' is being assigned into address space '/sys_mb/Data' at <0x8000_0000 [ 1G ]>.
    Slave segment '/axi_ddr_cntrl/memmap/memaddr' is being assigned into address space '/sys_mb/Instruction' at <0x8000_0000 [ 1G ]>.
    Slave segment '/axi_ad9361/s_axi/axi_lite' is being assigned into address space '/sys_mb/Data' at <0x7902_0000 [ 64K ]>.
    Slave segment '/axi_ad9361_adc_dma/s_axi/axi_lite' is being assigned into address space '/sys_mb/Data' at <0x7C40_0000 [ 4K ]>.
    Slave segment '/axi_ad9361_dac_dma/s_axi/axi_lite' is being assigned into address space '/sys_mb/Data' at <0x7C42_0000 [ 4K ]>.
    Slave segment '/axi_ethernet/S_AXI/Reg' is being assigned into address space '/sys_mb/Data' at <0x40E0_0000 [ 8K ]>.
    Slave segment '/axi_gpio/S_AXI/Reg' is being assigned into address space '/sys_mb/Data' at <0x4000_0000 [ 4K ]>.
    Slave segment '/axi_gpio_lcd/S_AXI/Reg' is being assigned into address space '/sys_mb/Data' at <0x4001_0000 [ 4K ]>.
    Slave segment '/axi_iic_main/S_AXI/Reg' is being assigned into address space '/sys_mb/Data' at <0x4160_0000 [ 4K ]>.
    Slave segment '/axi_intc/S_AXI/Reg' is being assigned into address space '/sys_mb/Data' at <0x4120_0000 [ 4K ]>.
    Slave segment '/axi_linear_flash/S_AXI_MEM/Mem0' is being assigned into address space '/sys_mb/Data' at <0x6000_0000 [ 32M ]>.
    Slave segment '/axi_spi/AXI_LITE/Reg' is being assigned into address space '/sys_mb/Data' at <0x44A7_0000 [ 4K ]>.
    Slave segment '/axi_sysid_0/s_axi/axi_lite' is being assigned into address space '/sys_mb/Data' at <0x4500_0000 [ 64K ]>.
    Slave segment '/axi_timer/S_AXI/Reg' is being assigned into address space '/sys_mb/Data' at <0x41C0_0000 [ 4K ]>.
    Slave segment '/axi_uart/S_AXI/Reg' is being assigned into address space '/sys_mb/Data' at <0x4060_0000 [ 4K ]>.
    Slave segment '/sys_mb_debug/S_AXI/Reg' is being assigned into address space '/sys_mb/Data' at <0x4140_0000 [ 4K ]>.
    Slave segment '/sys_dlmb_cntlr/SLMB/Mem' is being assigned into address space '/sys_mb/Data' at <0x0000_0000 [ 128K ]>.
    Slave segment '/sys_ilmb_cntlr/SLMB/Mem' is being assigned into address space '/sys_mb/Instruction' at <0x0000_0000 [ 128K ]>.
    INFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /axi_spi 
                       #######################################################################################
                       INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are synchronous to each other.
                       ########################################################################################
    INFO: [xilinx.com:ip:microblaze:11.0-16] /sys_mb: Setting D-cache cacheable area base address C_DCACHE_BASEADDR to 0x80000000 and high address C_DCACHE_HIGHADDR to 0xBFFFFFFF.
    INFO: [xilinx.com:ip:microblaze:11.0-16] /sys_mb: Setting I-cache cacheable area base address C_ICACHE_BASEADDR to 0x80000000 and high address C_ICACHE_HIGHADDR to 0xBFFFFFFF.
    WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_intc: Property SENSITIVITY = "NULL" for interrupt input 15 not recognized - using default interrupt type Rising Edge. Please change this manually if necessary.
    WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_intc: Property SENSITIVITY = "NULL" for interrupt input 14 not recognized - using default interrupt type Rising Edge. Please change this manually if necessary.
    WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_intc: Property SENSITIVITY = "NULL" for interrupt input 8 not recognized - using default interrupt type Rising Edge. Please change this manually if necessary.
    WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_intc: Property SENSITIVITY = "NULL" for interrupt input 7 not recognized - using default interrupt type Rising Edge. Please change this manually if necessary.
    WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_intc: Property SENSITIVITY = "NULL" for interrupt input 6 not recognized - using default interrupt type Rising Edge. Please change this manually if necessary.
    WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_intc: Property SENSITIVITY = "NULL" for interrupt input 3 not recognized - using default interrupt type Rising Edge. Please change this manually if necessary.
    WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_intc: Property SENSITIVITY = "NULL" for interrupt input 2 not recognized - using default interrupt type Rising Edge. Please change this manually if necessary.
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/delay_clk have been updated from connected ip, but BD cell '/axi_ad9361' does not accept parameter changes, so they may not be synchronized with cell properties:
    	PHASE = 0 
    Please resolve any mismatches by directly setting properties on BD cell </axi_ad9361> to completely resolve these warnings.
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/s_axi_aclk have been updated from connected ip, but BD cell '/axi_ad9361' does not accept parameter changes, so they may not be synchronized with cell properties:
    	PHASE = 0 
    Please resolve any mismatches by directly setting properties on BD cell </axi_ad9361> to completely resolve these warnings.
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_rst have been updated from connected ip, but BD cell '/axi_ad9361_dac_fifo' does not accept parameter changes, so they may not be synchronized with cell properties:
    	POLARITY = ACTIVE_HIGH 
    Please resolve any mismatches by directly setting properties on BD cell </axi_ad9361_dac_fifo> to completely resolve these warnings.
    WARNING: [BD 41-927] Following properties on pin /axi_sysid_0/s_axi_aclk have been updated from connected ip, but BD cell '/axi_sysid_0' does not accept parameter changes, so they may not be synchronized with cell properties:
    	PHASE = 0 
    Please resolve any mismatches by directly setting properties on BD cell </axi_sysid_0> to completely resolve these warnings.
    WARNING: [BD 41-927] Following properties on pin /rom_sys_0/clk have been updated from connected ip, but BD cell '/rom_sys_0' does not accept parameter changes, so they may not be synchronized with cell properties:
    	PHASE = 0 
    Please resolve any mismatches by directly setting properties on BD cell </rom_sys_0> to completely resolve these warnings.
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_rst have been updated from connected ip, but BD cell '/util_ad9361_adc_fifo' does not accept parameter changes, so they may not be synchronized with cell properties:
    	POLARITY = ACTIVE_HIGH 
    Please resolve any mismatches by directly setting properties on BD cell </util_ad9361_adc_fifo> to completely resolve these warnings.
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_tdd_sync/clk have been updated from connected ip, but BD cell '/util_ad9361_tdd_sync' does not accept parameter changes, so they may not be synchronized with cell properties:
    	PHASE = 0 
    Please resolve any mismatches by directly setting properties on BD cell </util_ad9361_tdd_sync> to completely resolve these warnings.
    WARNING: [BD 41-1771] Block interface /axi_ethernet/MDIO has associated board param 'MDIO_BOARD_INTERFACE', which is set to board part interface 'mdio_mdc'. This interface is connected to an external interface /mdio, whose name 'mdio' does not match with the board interface name 'mdio_mdc'.
    This is a visual-only issue - this interface /axi_ethernet/MDIO will be connected to board interface 'mdio_mdc'. If desired, please change the name of this port /mdio manually.
    validate_bd_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 9050.668 ; gain = 0.000 ; free physical = 3071 ; free virtual = 60119
    Wrote  : </export/data/test/write_bd_Tcl_test/project_1/project_1.srcs/sources_1/bd/BLABLA/BLABLA.bd> 
    Wrote  : </export/data/test/write_bd_Tcl_test/project_1/project_1.srcs/sources_1/bd/BLABLA/ui/bd_b3bac500.ui> 
    

Reply
  • +1
    •  Analog Employees 
    on Apr 30, 2021 9:12 AM

    Hello, 

    I tried to reproduce what you are seeing with the master branch: 

    1. built the project with make to build all the dependencies in the library

    2. opened the project and exported the block design with the write_bd_tcl

    3. created a new project for the kcu705 carrier

    4. sourced the modified tcl file 

    5. observed the errors about the missing IP files 

    6.  set the repo with the following or from GUI:

    set_property ip_repo_paths /export/data/workspace/ws5/hdl/library [current_project]
    
    update_ip_catalog

    7. source again the tcl file

    8. no errors observed, See log for reference.

    Thanks, 

    Laszlo

    source /media/data/workspace/ws5/hdl/projects/fmcomms2/kc705/myDesign.tcl
    # namespace eval _tcl {
    # proc get_script_folder {} {
    #    set script_path [file normalize [info script]]
    #    set script_folder [file dirname $script_path]
    #    return $script_folder
    # }
    # }
    # variable script_folder
    # set script_folder [_tcl::get_script_folder]
    # set scripts_vivado_version 2020.1
    # set current_vivado_version [version -short]
    # if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
    #    puts ""
    #    catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
    # 
    #    return 1
    # }
    # set list_projs [get_projects -quiet]
    # if { $list_projs eq "" } {
    #    create_project project_1 myproj -part xc7k325tffg900-2
    #    set_property BOARD_PART xilinx.com:kc705:part0:1.6 [current_project]
    # }
    # variable design_name
    # set design_name BLABLA 
    # set errMsg ""
    # set nRet 0
    # set cur_design [current_bd_design -quiet]
    # set list_cells [get_bd_cells -quiet]
    # if { ${design_name} eq "" } {
    #    # USE CASES:
    #    #    1) Design_name not set
    # 
    #    set errMsg "Please set the variable <design_name> to a non-empty value."
    #    set nRet 1
    # 
    # } elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
    #    # USE CASES:
    #    #    2): Current design opened AND is empty AND names same.
    #    #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
    #    #    4): Current design opened AND is empty AND names diff; design_name exists in project.
    # 
    #    if { $cur_design ne $design_name } {
    #       common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
    #       set design_name [get_property NAME $cur_design]
    #    }
    #    common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
    # 
    # } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
    #    # USE CASES:
    #    #    5) Current design opened AND has components AND same names.
    # 
    #    set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
    #    set nRet 1
    # } elseif { [get_files -quiet ${design_name}.bd] ne "" } {
    #    # USE CASES: 
    #    #    6) Current opened design, has components, but diff names, design_name exists in project.
    #    #    7) No opened design, design_name exists in project.
    # 
    #    set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
    #    set nRet 2
    # 
    # } else {
    #    # USE CASES:
    #    #    8) No opened design, design_name not in project.
    #    #    9) Current opened design, has components, but diff names, design_name not in project.
    # 
    #    common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
    # 
    #    create_bd_design $design_name
    # 
    #    common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
    #    current_bd_design $design_name
    # 
    # }
    INFO: [BD::TCL 103-2002] Constructing design in IPI design <BLABLA>...
    # common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
    INFO: [BD::TCL 103-2005] Currently the variable <design_name> is equal to "BLABLA".
    # if { $nRet != 0 } {
    #    catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
    #    return $nRet
    # }
    # set bCheckIPsPassed 1
    # set bCheckIPs 1
    # if { $bCheckIPs == 1 } {
    #    set list_check_ips "\ 
    # xilinx.com:ip:xlconstant:1.1\
    # analog.com:user:axi_ad9361:1.0\
    # analog.com:user:axi_dmac:1.0\
    # analog.com:user:util_rfifo:1.0\
    # xilinx.com:ip:mig_7series:4.2\
    # xilinx.com:ip:axi_ethernetlite:3.0\
    # xilinx.com:ip:axi_gpio:2.0\
    # xilinx.com:ip:axi_iic:2.0\
    # xilinx.com:ip:axi_intc:4.1\
    # xilinx.com:ip:axi_emc:3.0\
    # xilinx.com:ip:smartconnect:1.0\
    # xilinx.com:ip:axi_quad_spi:3.2\
    # analog.com:user:axi_sysid:1.0\
    # xilinx.com:ip:axi_timer:2.0\
    # xilinx.com:ip:axi_uartlite:2.0\
    # analog.com:user:sysid_rom:1.0\
    # xilinx.com:ip:proc_sys_reset:5.0\
    # xilinx.com:ip:xlconcat:2.1\
    # xilinx.com:ip:lmb_v10:3.0\
    # xilinx.com:ip:lmb_bram_if_cntlr:4.0\
    # xilinx.com:ip:blk_mem_gen:8.4\
    # xilinx.com:ip:microblaze:11.0\
    # xilinx.com:ip:mdm:3.2\
    # analog.com:user:util_wfifo:1.0\
    # analog.com:user:util_cpack2:1.0\
    # analog.com:user:util_upack2:1.0\
    # analog.com:user:util_clkdiv:1.0\
    # xilinx.com:ip:util_reduced_logic:2.0\
    # analog.com:user:util_tdd_sync:1.0\
    # "
    # 
    #    set list_ips_missing ""
    #    common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
    # 
    #    foreach ip_vlnv $list_check_ips {
    #       set ip_obj [get_ipdefs -all $ip_vlnv]
    #       if { $ip_obj eq "" } {
    #          lappend list_ips_missing $ip_vlnv
    #       }
    #    }
    # 
    #    if { $list_ips_missing ne "" } {
    #       catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
    #       set bCheckIPsPassed 0
    #    }
    # 
    # }
    INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog:  
    xilinx.com:ip:xlconstant:1.1 analog.com:user:axi_ad9361:1.0 analog.com:user:axi_dmac:1.0 analog.com:user:util_rfifo:1.0 xilinx.com:ip:mig_7series:4.2 xilinx.com:ip:axi_ethernetlite:3.0 xilinx.com:ip:axi_gpio:2.0 xilinx.com:ip:axi_iic:2.0 xilinx.com:ip:axi_intc:4.1 xilinx.com:ip:axi_emc:3.0 xilinx.com:ip:smartconnect:1.0 xilinx.com:ip:axi_quad_spi:3.2 analog.com:user:axi_sysid:1.0 xilinx.com:ip:axi_timer:2.0 xilinx.com:ip:axi_uartlite:2.0 analog.com:user:sysid_rom:1.0 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:xlconcat:2.1 xilinx.com:ip:lmb_v10:3.0 xilinx.com:ip:lmb_bram_if_cntlr:4.0 xilinx.com:ip:blk_mem_gen:8.4 xilinx.com:ip:microblaze:11.0 xilinx.com:ip:mdm:3.2 analog.com:user:util_wfifo:1.0 analog.com:user:util_cpack2:1.0 analog.com:user:util_upack2:1.0 analog.com:user:util_clkdiv:1.0 xilinx.com:ip:util_reduced_logic:2.0 analog.com:user:util_tdd_sync:1.0  .
    # if { $bCheckIPsPassed != 1 } {
    #   common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
    #   return 3
    # }
    # proc write_mig_file_system_axi_ddr_cntrl_0 { str_mig_prj_filepath } {
    # 
    #    file mkdir [ file dirname "$str_mig_prj_filepath" ]
    #    set mig_prj_file [open $str_mig_prj_filepath  w+]
    # 
    #    puts $mig_prj_file {<?xml version='1.0' encoding='UTF-8'?>}
    #    puts $mig_prj_file {<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->}
    #    puts $mig_prj_file {<Project NoOfControllers="1" >}
    #    puts $mig_prj_file {    <ModuleName>system_axi_ddr_cntrl_0</ModuleName>}
    #    puts $mig_prj_file {    <dci_inouts_inputs>1</dci_inouts_inputs>}
    #    puts $mig_prj_file {    <dci_inputs>1</dci_inputs>}
    #    puts $mig_prj_file {    <Debug_En>OFF</Debug_En>}
    #    puts $mig_prj_file {    <DataDepth_En>1024</DataDepth_En>}
    #    puts $mig_prj_file {    <LowPower_En>ON</LowPower_En>}
    #    puts $mig_prj_file {    <XADC_En>Disabled</XADC_En>}
    #    puts $mig_prj_file {    <TargetFPGA>xc7k325t-ffg900/-2</TargetFPGA>}
    #    puts $mig_prj_file {    <Version>2.3</Version>}
    #    puts $mig_prj_file {    <SystemClock>Differential</SystemClock>}
    #    puts $mig_prj_file {    <ReferenceClock>Use System Clock</ReferenceClock>}
    #    puts $mig_prj_file {    <SysResetPolarity>ACTIVE HIGH</SysResetPolarity>}
    #    puts $mig_prj_file {    <BankSelectionFlag>FALSE</BankSelectionFlag>}
    #    puts $mig_prj_file {    <InternalVref>0</InternalVref>}
    #    puts $mig_prj_file {    <dci_hr_inouts_inputs>40 Ohms</dci_hr_inouts_inputs>}
    #    puts $mig_prj_file {    <dci_cascade>1</dci_cascade>}
    #    puts $mig_prj_file {    <Controller number="0" >}
    #    puts $mig_prj_file {        <MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>}
    #    puts $mig_prj_file {        <TimePeriod>1250</TimePeriod>}
    #    puts $mig_prj_file {        <VccAuxIO>2.0V</VccAuxIO>}
    #    puts $mig_prj_file {        <PHYRatio>4:1</PHYRatio>}
    #    puts $mig_prj_file {        <InputClkFreq>200</InputClkFreq>}
    #    puts $mig_prj_file {        <UIExtraClocks>1</UIExtraClocks>}
    #    puts $mig_prj_file {        <MMCM_VCO>800</MMCM_VCO>}
    #    puts $mig_prj_file {        <MMCMClkOut0> 8.000</MMCMClkOut0>}
    #    puts $mig_prj_file {        <MMCMClkOut1>1</MMCMClkOut1>}
    #    puts $mig_prj_file {        <MMCMClkOut2>1</MMCMClkOut2>}
    #    puts $mig_prj_file {        <MMCMClkOut3>1</MMCMClkOut3>}
    #    puts $mig_prj_file {        <MMCMClkOut4>1</MMCMClkOut4>}
    #    puts $mig_prj_file {        <DataWidth>64</DataWidth>}
    #    puts $mig_prj_file {        <DeepMemory>1</DeepMemory>}
    #    puts $mig_prj_file {        <DataMask>1</DataMask>}
    #    puts $mig_prj_file {        <ECC>Disabled</ECC>}
    #    puts $mig_prj_file {        <Ordering>Normal</Ordering>}
    #    puts $mig_prj_file {        <CustomPart>FALSE</CustomPart>}
    #    puts $mig_prj_file {        <NewPartName></NewPartName>}
    #    puts $mig_prj_file {        <RowAddress>14</RowAddress>}
    #    puts $mig_prj_file {        <ColAddress>10</ColAddress>}
    #    puts $mig_prj_file {        <BankAddress>3</BankAddress>}
    #    puts $mig_prj_file {        <MemoryVoltage>1.5V</MemoryVoltage>}
    #    puts $mig_prj_file {        <C0_MEM_SIZE>1073741824</C0_MEM_SIZE>}
    #    puts $mig_prj_file {        <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>}
    #    puts $mig_prj_file {        <PinSelection>}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH12" SLEW="" name="ddr3_addr[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF13" SLEW="" name="ddr3_addr[10]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE13" SLEW="" name="ddr3_addr[11]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ11" SLEW="" name="ddr3_addr[12]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH11" SLEW="" name="ddr3_addr[13]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG13" SLEW="" name="ddr3_addr[1]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG12" SLEW="" name="ddr3_addr[2]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF12" SLEW="" name="ddr3_addr[3]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ12" SLEW="" name="ddr3_addr[4]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ13" SLEW="" name="ddr3_addr[5]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ14" SLEW="" name="ddr3_addr[6]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH14" SLEW="" name="ddr3_addr[7]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK13" SLEW="" name="ddr3_addr[8]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK14" SLEW="" name="ddr3_addr[9]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH9" SLEW="" name="ddr3_ba[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG9" SLEW="" name="ddr3_ba[1]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK9" SLEW="" name="ddr3_ba[2]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC11" SLEW="" name="ddr3_cas_n" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AH10" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AG10" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF10" SLEW="" name="ddr3_cke[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC12" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="Y16" SLEW="" name="ddr3_dm[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB17" SLEW="" name="ddr3_dm[1]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF17" SLEW="" name="ddr3_dm[2]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE16" SLEW="" name="ddr3_dm[3]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK5" SLEW="" name="ddr3_dm[4]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ3" SLEW="" name="ddr3_dm[5]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF6" SLEW="" name="ddr3_dm[6]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC7" SLEW="" name="ddr3_dm[7]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA15" SLEW="" name="ddr3_dq[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC19" SLEW="" name="ddr3_dq[10]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD17" SLEW="" name="ddr3_dq[11]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA18" SLEW="" name="ddr3_dq[12]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AB18" SLEW="" name="ddr3_dq[13]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE18" SLEW="" name="ddr3_dq[14]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD18" SLEW="" name="ddr3_dq[15]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG19" SLEW="" name="ddr3_dq[16]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK19" SLEW="" name="ddr3_dq[17]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG18" SLEW="" name="ddr3_dq[18]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF18" SLEW="" name="ddr3_dq[19]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA16" SLEW="" name="ddr3_dq[1]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH19" SLEW="" name="ddr3_dq[20]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ19" SLEW="" name="ddr3_dq[21]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE19" SLEW="" name="ddr3_dq[22]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD19" SLEW="" name="ddr3_dq[23]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK16" SLEW="" name="ddr3_dq[24]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ17" SLEW="" name="ddr3_dq[25]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG15" SLEW="" name="ddr3_dq[26]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF15" SLEW="" name="ddr3_dq[27]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH17" SLEW="" name="ddr3_dq[28]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG14" SLEW="" name="ddr3_dq[29]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC14" SLEW="" name="ddr3_dq[2]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH15" SLEW="" name="ddr3_dq[30]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK15" SLEW="" name="ddr3_dq[31]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK8" SLEW="" name="ddr3_dq[32]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK6" SLEW="" name="ddr3_dq[33]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG7" SLEW="" name="ddr3_dq[34]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF7" SLEW="" name="ddr3_dq[35]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF8" SLEW="" name="ddr3_dq[36]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK4" SLEW="" name="ddr3_dq[37]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ8" SLEW="" name="ddr3_dq[38]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ6" SLEW="" name="ddr3_dq[39]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD14" SLEW="" name="ddr3_dq[3]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH5" SLEW="" name="ddr3_dq[40]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH6" SLEW="" name="ddr3_dq[41]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ2" SLEW="" name="ddr3_dq[42]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH2" SLEW="" name="ddr3_dq[43]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH4" SLEW="" name="ddr3_dq[44]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ4" SLEW="" name="ddr3_dq[45]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK1" SLEW="" name="ddr3_dq[46]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ1" SLEW="" name="ddr3_dq[47]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF1" SLEW="" name="ddr3_dq[48]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF2" SLEW="" name="ddr3_dq[49]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA17" SLEW="" name="ddr3_dq[4]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE4" SLEW="" name="ddr3_dq[50]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE3" SLEW="" name="ddr3_dq[51]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF3" SLEW="" name="ddr3_dq[52]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF5" SLEW="" name="ddr3_dq[53]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE1" SLEW="" name="ddr3_dq[54]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE5" SLEW="" name="ddr3_dq[55]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC1" SLEW="" name="ddr3_dq[56]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD3" SLEW="" name="ddr3_dq[57]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC4" SLEW="" name="ddr3_dq[58]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC5" SLEW="" name="ddr3_dq[59]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AB15" SLEW="" name="ddr3_dq[5]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE6" SLEW="" name="ddr3_dq[60]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD6" SLEW="" name="ddr3_dq[61]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC2" SLEW="" name="ddr3_dq[62]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD4" SLEW="" name="ddr3_dq[63]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE15" SLEW="" name="ddr3_dq[6]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="Y15" SLEW="" name="ddr3_dq[7]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AB19" SLEW="" name="ddr3_dq[8]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD16" SLEW="" name="ddr3_dq[9]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AC15" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="Y18" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AK18" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ16" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ7" SLEW="" name="ddr3_dqs_n[4]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH1" SLEW="" name="ddr3_dqs_n[5]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG3" SLEW="" name="ddr3_dqs_n[6]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD1" SLEW="" name="ddr3_dqs_n[7]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AC16" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="Y19" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ18" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH16" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH7" SLEW="" name="ddr3_dqs_p[4]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG2" SLEW="" name="ddr3_dqs_p[5]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG4" SLEW="" name="ddr3_dqs_p[6]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD2" SLEW="" name="ddr3_dqs_p[7]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD8" SLEW="" name="ddr3_odt[0]" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD9" SLEW="" name="ddr3_ras_n" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="LVCMOS15" PADName="AK3" SLEW="" name="ddr3_reset_n" IN_TERM="" />}
    #    puts $mig_prj_file {            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE9" SLEW="" name="ddr3_we_n" IN_TERM="" />}
    #    puts $mig_prj_file {        </PinSelection>}
    #    puts $mig_prj_file {        <System_Clock>}
    #    puts $mig_prj_file {            <Pin PADName="AD12/AD11(CC_P/N)" Bank="33" name="sys_clk_p/n" />}
    #    puts $mig_prj_file {        </System_Clock>}
    #    puts $mig_prj_file {        <System_Control>}
    #    puts $mig_prj_file {            <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />}
    #    puts $mig_prj_file {            <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />}
    #    puts $mig_prj_file {            <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />}
    #    puts $mig_prj_file {        </System_Control>}
    #    puts $mig_prj_file {        <TimingParameters>}
    #    puts $mig_prj_file {            <Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.75" tras="35" trcd="13.75" />}
    #    puts $mig_prj_file {        </TimingParameters>}
    #    puts $mig_prj_file {        <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>}
    #    puts $mig_prj_file {        <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>}
    #    puts $mig_prj_file {        <mrCasLatency name="CAS Latency" >11</mrCasLatency>}
    #    puts $mig_prj_file {        <mrMode name="Mode" >Normal</mrMode>}
    #    puts $mig_prj_file {        <mrDllReset name="DLL Reset" >No</mrDllReset>}
    #    puts $mig_prj_file {        <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>}
    #    puts $mig_prj_file {        <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>}
    #    puts $mig_prj_file {        <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>}
    #    puts $mig_prj_file {        <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>}
    #    puts $mig_prj_file {        <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>}
    #    puts $mig_prj_file {        <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>}
    #    puts $mig_prj_file {        <emrPosted name="Additive Latency (AL)" >0</emrPosted>}
    #    puts $mig_prj_file {        <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>}
    #    puts $mig_prj_file {        <emrDQS name="TDQS enable" >Enabled</emrDQS>}
    #    puts $mig_prj_file {        <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>}
    #    puts $mig_prj_file {        <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>}
    #    puts $mig_prj_file {        <mr2CasWriteLatency name="CAS write latency" >8</mr2CasWriteLatency>}
    #    puts $mig_prj_file {        <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>}
    #    puts $mig_prj_file {        <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>}
    #    puts $mig_prj_file {        <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>}
    #    puts $mig_prj_file {        <PortInterface>AXI</PortInterface>}
    #    puts $mig_prj_file {        <AXIParameters>}
    #    puts $mig_prj_file {            <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>}
    #    puts $mig_prj_file {            <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>}
    #    puts $mig_prj_file {            <C0_S_AXI_DATA_WIDTH>512</C0_S_AXI_DATA_WIDTH>}
    #    puts $mig_prj_file {            <C0_S_AXI_ID_WIDTH>3</C0_S_AXI_ID_WIDTH>}
    #    puts $mig_prj_file {            <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>}
    #    puts $mig_prj_file {        </AXIParameters>}
    #    puts $mig_prj_file {    </Controller>}
    #    puts $mig_prj_file {</Project>}
    # 
    #    close $mig_prj_file
    # }
    # proc create_root_design { parentCell } {
    # 
    #   variable script_folder
    #   variable design_name
    # 
    #   if { $parentCell eq "" } {
    #      set parentCell [get_bd_cells /]
    #   }
    # 
    #   # Get object for parentCell
    #   set parentObj [get_bd_cells $parentCell]
    #   if { $parentObj == "" } {
    #      catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
    #      return
    #   }
    # 
    #   # Make sure parentObj is hier blk
    #   set parentType [get_property TYPE $parentObj]
    #   if { $parentType ne "hier" } {
    #      catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
    #      return
    #   }
    # 
    #   # Save current instance; Restore later
    #   set oldCurInst [current_bd_instance .]
    # 
    #   # Set parent object as current
    #   current_bd_instance $parentObj
    # 
    # 
    #   # Create interface ports
    #   set ddr3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 ]
    # 
    #   set gpio_lcd [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_lcd ]
    # 
    #   set iic_main [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main ]
    # 
    #   set linear_flash [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:emc_rtl:1.0 linear_flash ]
    # 
    #   set mdio [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio ]
    # 
    #   set mii [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mii_rtl:1.0 mii ]
    # 
    # 
    #   # Create ports
    #   set enable [ create_bd_port -dir O enable ]
    #   set gpio0_i [ create_bd_port -dir I -from 31 -to 0 gpio0_i ]
    #   set gpio0_o [ create_bd_port -dir O -from 31 -to 0 gpio0_o ]
    #   set gpio0_t [ create_bd_port -dir O -from 31 -to 0 gpio0_t ]
    #   set gpio1_i [ create_bd_port -dir I -from 31 -to 0 gpio1_i ]
    #   set gpio1_o [ create_bd_port -dir O -from 31 -to 0 gpio1_o ]
    #   set gpio1_t [ create_bd_port -dir O -from 31 -to 0 gpio1_t ]
    #   set rx_clk_in_n [ create_bd_port -dir I rx_clk_in_n ]
    #   set rx_clk_in_p [ create_bd_port -dir I rx_clk_in_p ]
    #   set rx_data_in_n [ create_bd_port -dir I -from 5 -to 0 rx_data_in_n ]
    #   set rx_data_in_p [ create_bd_port -dir I -from 5 -to 0 rx_data_in_p ]
    #   set rx_frame_in_n [ create_bd_port -dir I rx_frame_in_n ]
    #   set rx_frame_in_p [ create_bd_port -dir I rx_frame_in_p ]
    #   set spi_clk_i [ create_bd_port -dir I spi_clk_i ]
    #   set spi_clk_o [ create_bd_port -dir O spi_clk_o ]
    #   set spi_csn_i [ create_bd_port -dir I -from 7 -to 0 spi_csn_i ]
    #   set spi_csn_o [ create_bd_port -dir O -from 7 -to 0 spi_csn_o ]
    #   set spi_sdi_i [ create_bd_port -dir I spi_sdi_i ]
    #   set spi_sdo_i [ create_bd_port -dir I spi_sdo_i ]
    #   set spi_sdo_o [ create_bd_port -dir O spi_sdo_o ]
    #   set sys_clk_n [ create_bd_port -dir I sys_clk_n ]
    #   set sys_clk_p [ create_bd_port -dir I sys_clk_p ]
    #   set sys_rst [ create_bd_port -dir I -type rst sys_rst ]
    #   set_property -dict [ list \
    #    CONFIG.POLARITY {ACTIVE_HIGH} \
    #  ] $sys_rst
    #   set tdd_sync_i [ create_bd_port -dir I tdd_sync_i ]
    #   set tdd_sync_o [ create_bd_port -dir O tdd_sync_o ]
    #   set tdd_sync_t [ create_bd_port -dir O tdd_sync_t ]
    #   set tx_clk_out_n [ create_bd_port -dir O tx_clk_out_n ]
    #   set tx_clk_out_p [ create_bd_port -dir O tx_clk_out_p ]
    #   set tx_data_out_n [ create_bd_port -dir O -from 5 -to 0 tx_data_out_n ]
    #   set tx_data_out_p [ create_bd_port -dir O -from 5 -to 0 tx_data_out_p ]
    #   set tx_frame_out_n [ create_bd_port -dir O tx_frame_out_n ]
    #   set tx_frame_out_p [ create_bd_port -dir O tx_frame_out_p ]
    #   set txnrx [ create_bd_port -dir O txnrx ]
    #   set uart_sin [ create_bd_port -dir I uart_sin ]
    #   set uart_sout [ create_bd_port -dir O uart_sout ]
    #   set up_enable [ create_bd_port -dir I up_enable ]
    #   set up_txnrx [ create_bd_port -dir I up_txnrx ]
    # 
    #   # Create instance: GND_1, and set properties
    #   set GND_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 GND_1 ]
    #   set_property -dict [ list \
    #    CONFIG.CONST_VAL {0} \
    #    CONFIG.CONST_WIDTH {1} \
    #  ] $GND_1
    # 
    #   # Create instance: GND_12, and set properties
    #   set GND_12 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 GND_12 ]
    #   set_property -dict [ list \
    #    CONFIG.CONST_VAL {0} \
    #    CONFIG.CONST_WIDTH {12} \
    #  ] $GND_12
    # 
    #   # Create instance: axi_ad9361, and set properties
    #   set axi_ad9361 [ create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361 ]
    #   set_property -dict [ list \
    #    CONFIG.ADC_INIT_DELAY {31} \
    #    CONFIG.DAC_DDS_CORDIC_DW {14} \
    #    CONFIG.DAC_DDS_TYPE {1} \
    #    CONFIG.ID {0} \
    #  ] $axi_ad9361
    # 
    #   # Create instance: axi_ad9361_adc_dma, and set properties
    #   set axi_ad9361_adc_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma ]
    #   set_property -dict [ list \
    #    CONFIG.AXI_SLICE_DEST {false} \
    #    CONFIG.AXI_SLICE_SRC {false} \
    #    CONFIG.CYCLIC {false} \
    #    CONFIG.DMA_2D_TRANSFER {false} \
    #    CONFIG.DMA_DATA_WIDTH_SRC {64} \
    #    CONFIG.DMA_TYPE_DEST {0} \
    #    CONFIG.DMA_TYPE_SRC {2} \
    #    CONFIG.SYNC_TRANSFER_START {true} \
    #  ] $axi_ad9361_adc_dma
    # 
    #   # Create instance: axi_ad9361_dac_dma, and set properties
    #   set axi_ad9361_dac_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma ]
    #   set_property -dict [ list \
    #    CONFIG.AXI_SLICE_DEST {false} \
    #    CONFIG.AXI_SLICE_SRC {false} \
    #    CONFIG.CYCLIC {true} \
    #    CONFIG.DMA_2D_TRANSFER {false} \
    #    CONFIG.DMA_DATA_WIDTH_DEST {64} \
    #    CONFIG.DMA_TYPE_DEST {1} \
    #    CONFIG.DMA_TYPE_SRC {0} \
    #  ] $axi_ad9361_dac_dma
    # 
    #   # Create instance: axi_ad9361_dac_fifo, and set properties
    #   set axi_ad9361_dac_fifo [ create_bd_cell -type ip -vlnv analog.com:user:util_rfifo:1.0 axi_ad9361_dac_fifo ]
    #   set_property -dict [ list \
    #    CONFIG.DIN_ADDRESS_WIDTH {4} \
    #    CONFIG.DIN_DATA_WIDTH {16} \
    #    CONFIG.DOUT_DATA_WIDTH {16} \
    #  ] $axi_ad9361_dac_fifo
    # 
    #   # Create instance: axi_cpu_interconnect, and set properties
    #   set axi_cpu_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect ]
    #   set_property -dict [ list \
    #    CONFIG.NUM_MI {14} \
    #  ] $axi_cpu_interconnect
    # 
    #   # Create instance: axi_ddr_cntrl, and set properties
    #   set axi_ddr_cntrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.2 axi_ddr_cntrl ]
    # 
    #   # Generate the PRJ File for MIG
    #   set str_mig_folder [get_property IP_DIR [ get_ips [ get_property CONFIG.Component_Name $axi_ddr_cntrl ] ] ]
    #   set str_mig_file_name kc705_system_mig.prj
    #   set str_mig_file_path ${str_mig_folder}/${str_mig_file_name}
    # 
    #   write_mig_file_system_axi_ddr_cntrl_0 $str_mig_file_path
    # 
    #   set_property -dict [ list \
    #    CONFIG.XML_INPUT_FILE {kc705_system_mig.prj} \
    #  ] $axi_ddr_cntrl
    # 
    #   # Create instance: axi_ethernet, and set properties
    #   set axi_ethernet [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernetlite:3.0 axi_ethernet ]
    #   set_property -dict [ list \
    #    CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc} \
    #    CONFIG.MII_BOARD_INTERFACE {mii} \
    #    CONFIG.USE_BOARD_FLOW {true} \
    #  ] $axi_ethernet
    # 
    #   # Create instance: axi_gpio, and set properties
    #   set axi_gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio ]
    #   set_property -dict [ list \
    #    CONFIG.C_GPIO2_WIDTH {32} \
    #    CONFIG.C_GPIO_WIDTH {32} \
    #    CONFIG.C_INTERRUPT_PRESENT {1} \
    #    CONFIG.C_IS_DUAL {1} \
    #  ] $axi_gpio
    # 
    #   # Create instance: axi_gpio_lcd, and set properties
    #   set axi_gpio_lcd [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_lcd ]
    #   set_property -dict [ list \
    #    CONFIG.C_GPIO_WIDTH {7} \
    #    CONFIG.C_INTERRUPT_PRESENT {1} \
    #  ] $axi_gpio_lcd
    # 
    #   # Create instance: axi_iic_main, and set properties
    #   set axi_iic_main [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main ]
    # 
    #   # Create instance: axi_intc, and set properties
    #   set axi_intc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc ]
    #   set_property -dict [ list \
    #    CONFIG.C_HAS_FAST {0} \
    #  ] $axi_intc
    # 
    #   # Create instance: axi_linear_flash, and set properties
    #   set axi_linear_flash [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_emc:3.0 axi_linear_flash ]
    #   set_property -dict [ list \
    #    CONFIG.C_MEM0_TYPE {2} \
    #    CONFIG.C_S_AXI_MEM_ID_WIDTH {0} \
    #    CONFIG.C_TAVDV_PS_MEM_0 {100000} \
    #    CONFIG.C_TCEDV_PS_MEM_0 {100000} \
    #    CONFIG.C_THZCE_PS_MEM_0 {20000} \
    #    CONFIG.C_THZOE_PS_MEM_0 {15000} \
    #    CONFIG.C_TLZWE_PS_MEM_0 {0} \
    #    CONFIG.C_TPACC_PS_FLASH_0 {25000} \
    #    CONFIG.C_TWC_PS_MEM_0 {19000} \
    #    CONFIG.C_TWPH_PS_MEM_0 {20000} \
    #    CONFIG.C_TWP_PS_MEM_0 {50000} \
    #    CONFIG.C_WR_REC_TIME_MEM_0 {0} \
    #    CONFIG.EMC_BOARD_INTERFACE {linear_flash} \
    #    CONFIG.USE_BOARD_FLOW {true} \
    #  ] $axi_linear_flash
    # 
    #   # Create instance: axi_mem_interconnect, and set properties
    #   set axi_mem_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_mem_interconnect ]
    #   set_property -dict [ list \
    #    CONFIG.NUM_CLKS {2} \
    #    CONFIG.NUM_MI {1} \
    #    CONFIG.NUM_SI {4} \
    #  ] $axi_mem_interconnect
    # 
    #   # Create instance: axi_spi, and set properties
    #   set axi_spi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_spi ]
    #   set_property -dict [ list \
    #    CONFIG.C_NUM_SS_BITS {8} \
    #    CONFIG.C_SCK_RATIO {8} \
    #    CONFIG.C_USE_STARTUP {0} \
    #  ] $axi_spi
    # 
    #   # Create instance: axi_sysid_0, and set properties
    #   set axi_sysid_0 [ create_bd_cell -type ip -vlnv analog.com:user:axi_sysid:1.0 axi_sysid_0 ]
    #   set_property -dict [ list \
    #    CONFIG.ROM_ADDR_BITS {9} \
    #  ] $axi_sysid_0
    # 
    #   # Create instance: axi_timer, and set properties
    #   set axi_timer [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer ]
    # 
    #   # Create instance: axi_uart, and set properties
    #   set axi_uart [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart ]
    #   set_property -dict [ list \
    #    CONFIG.C_BAUDRATE {115200} \
    #  ] $axi_uart
    # 
    #   # Create instance: rom_sys_0, and set properties
    #   set rom_sys_0 [ create_bd_cell -type ip -vlnv analog.com:user:sysid_rom:1.0 rom_sys_0 ]
    #   set_property -dict [ list \
    #    CONFIG.PATH_TO_FILE {/export/data/workspace/ws5/hdl/projects/fmcomms2/kc705/mem_init_sys.txt} \
    #    CONFIG.ROM_ADDR_BITS {9} \
    #  ] $rom_sys_0
    # 
    #   # Create instance: sys_200m_rstgen, and set properties
    #   set sys_200m_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_200m_rstgen ]
    #   set_property -dict [ list \
    #    CONFIG.C_EXT_RST_WIDTH {1} \
    #  ] $sys_200m_rstgen
    # 
    #   # Create instance: sys_concat_intc, and set properties
    #   set sys_concat_intc [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc ]
    #   set_property -dict [ list \
    #    CONFIG.NUM_PORTS {16} \
    #  ] $sys_concat_intc
    # 
    #   # Create instance: sys_dlmb, and set properties
    #   set sys_dlmb [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_dlmb ]
    # 
    #   # Create instance: sys_dlmb_cntlr, and set properties
    #   set sys_dlmb_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_dlmb_cntlr ]
    #   set_property -dict [ list \
    #    CONFIG.C_ECC {0} \
    #  ] $sys_dlmb_cntlr
    # 
    #   # Create instance: sys_ilmb, and set properties
    #   set sys_ilmb [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_ilmb ]
    # 
    #   # Create instance: sys_ilmb_cntlr, and set properties
    #   set sys_ilmb_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr ]
    #   set_property -dict [ list \
    #    CONFIG.C_ECC {0} \
    #  ] $sys_ilmb_cntlr
    # 
    #   # Create instance: sys_lmb_bram, and set properties
    #   set sys_lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 sys_lmb_bram ]
    #   set_property -dict [ list \
    #    CONFIG.Memory_Type {True_Dual_Port_RAM} \
    #    CONFIG.use_bram_block {BRAM_Controller} \
    #  ] $sys_lmb_bram
    # 
    #   # Create instance: sys_mb, and set properties
    #   set sys_mb [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:11.0 sys_mb ]
    #   set_property -dict [ list \
    #    CONFIG.G_TEMPLATE_LIST {4} \
    #  ] $sys_mb
    # 
    #   # Create instance: sys_mb_debug, and set properties
    #   set sys_mb_debug [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 sys_mb_debug ]
    #   set_property -dict [ list \
    #    CONFIG.C_USE_UART {1} \
    #  ] $sys_mb_debug
    # 
    #   # Create instance: sys_rstgen, and set properties
    #   set sys_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen ]
    #   set_property -dict [ list \
    #    CONFIG.C_EXT_RST_WIDTH {1} \
    #  ] $sys_rstgen
    # 
    #   # Create instance: util_ad9361_adc_fifo, and set properties
    #   set util_ad9361_adc_fifo [ create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 util_ad9361_adc_fifo ]
    #   set_property -dict [ list \
    #    CONFIG.DIN_ADDRESS_WIDTH {4} \
    #    CONFIG.DIN_DATA_WIDTH {16} \
    #    CONFIG.DOUT_DATA_WIDTH {16} \
    #    CONFIG.NUM_OF_CHANNELS {4} \
    #  ] $util_ad9361_adc_fifo
    # 
    #   # Create instance: util_ad9361_adc_pack, and set properties
    #   set util_ad9361_adc_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack2:1.0 util_ad9361_adc_pack ]
    #   set_property -dict [ list \
    #    CONFIG.NUM_OF_CHANNELS {4} \
    #    CONFIG.SAMPLE_DATA_WIDTH {16} \
    #  ] $util_ad9361_adc_pack
    # 
    #   # Create instance: util_ad9361_dac_upack, and set properties
    #   set util_ad9361_dac_upack [ create_bd_cell -type ip -vlnv analog.com:user:util_upack2:1.0 util_ad9361_dac_upack ]
    #   set_property -dict [ list \
    #    CONFIG.NUM_OF_CHANNELS {4} \
    #    CONFIG.SAMPLE_DATA_WIDTH {16} \
    #  ] $util_ad9361_dac_upack
    # 
    #   # Create instance: util_ad9361_divclk, and set properties
    #   set util_ad9361_divclk [ create_bd_cell -type ip -vlnv analog.com:user:util_clkdiv:1.0 util_ad9361_divclk ]
    # 
    #   # Create instance: util_ad9361_divclk_reset, and set properties
    #   set util_ad9361_divclk_reset [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 util_ad9361_divclk_reset ]
    # 
    #   # Create instance: util_ad9361_divclk_sel, and set properties
    #   set util_ad9361_divclk_sel [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 util_ad9361_divclk_sel ]
    #   set_property -dict [ list \
    #    CONFIG.C_SIZE {2} \
    #  ] $util_ad9361_divclk_sel
    # 
    #   # Create instance: util_ad9361_divclk_sel_concat, and set properties
    #   set util_ad9361_divclk_sel_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 util_ad9361_divclk_sel_concat ]
    #   set_property -dict [ list \
    #    CONFIG.NUM_PORTS {2} \
    #  ] $util_ad9361_divclk_sel_concat
    # 
    #   # Create instance: util_ad9361_tdd_sync, and set properties
    #   set util_ad9361_tdd_sync [ create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync ]
    #   set_property -dict [ list \
    #    CONFIG.TDD_SYNC_PERIOD {10000000} \
    #  ] $util_ad9361_tdd_sync
    # 
    #   # Create interface connections
    #   connect_bd_intf_net -intf_net Conn [get_bd_intf_pins sys_dlmb/LMB_Sl_0] [get_bd_intf_pins sys_dlmb_cntlr/SLMB]
    #   connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins sys_ilmb/LMB_Sl_0] [get_bd_intf_pins sys_ilmb_cntlr/SLMB]
    #   connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DP]
    #   connect_bd_intf_net -intf_net axi_ad9361_adc_dma_m_dest_axi [get_bd_intf_pins axi_ad9361_adc_dma/m_dest_axi] [get_bd_intf_pins axi_mem_interconnect/S02_AXI]
    #   connect_bd_intf_net -intf_net axi_ad9361_dac_dma_m_axis [get_bd_intf_pins axi_ad9361_dac_dma/m_axis] [get_bd_intf_pins util_ad9361_dac_upack/s_axis]
    #   connect_bd_intf_net -intf_net axi_ad9361_dac_dma_m_src_axi [get_bd_intf_pins axi_ad9361_dac_dma/m_src_axi] [get_bd_intf_pins axi_mem_interconnect/S03_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M00_AXI [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins sys_mb_debug/S_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M01_AXI [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_ethernet/S_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M02_AXI [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins axi_gpio_lcd/S_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M03_AXI [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_intc/s_axi]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M04_AXI [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_timer/S_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M05_AXI [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins axi_uart/S_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M06_AXI [get_bd_intf_pins axi_cpu_interconnect/M06_AXI] [get_bd_intf_pins axi_iic_main/S_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M07_AXI [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_sysid_0/s_axi]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M08_AXI [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_gpio/S_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M09_AXI [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_spi/AXI_LITE]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M10_AXI [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_linear_flash/S_AXI_MEM]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M11_AXI [get_bd_intf_pins axi_ad9361/s_axi] [get_bd_intf_pins axi_cpu_interconnect/M11_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M12_AXI [get_bd_intf_pins axi_ad9361_adc_dma/s_axi] [get_bd_intf_pins axi_cpu_interconnect/M12_AXI]
    #   connect_bd_intf_net -intf_net axi_cpu_interconnect_M13_AXI [get_bd_intf_pins axi_ad9361_dac_dma/s_axi] [get_bd_intf_pins axi_cpu_interconnect/M13_AXI]
    #   connect_bd_intf_net -intf_net axi_ddr_cntrl_DDR3 [get_bd_intf_ports ddr3] [get_bd_intf_pins axi_ddr_cntrl/DDR3]
    #   connect_bd_intf_net -intf_net axi_ethernet_MDIO [get_bd_intf_ports mdio] [get_bd_intf_pins axi_ethernet/MDIO]
    #   connect_bd_intf_net -intf_net axi_ethernet_MII [get_bd_intf_ports mii] [get_bd_intf_pins axi_ethernet/MII]
    #   connect_bd_intf_net -intf_net axi_gpio_lcd_GPIO [get_bd_intf_ports gpio_lcd] [get_bd_intf_pins axi_gpio_lcd/GPIO]
    #   connect_bd_intf_net -intf_net axi_iic_main_IIC [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_main/IIC]
    #   connect_bd_intf_net -intf_net axi_intc_interrupt [get_bd_intf_pins axi_intc/interrupt] [get_bd_intf_pins sys_mb/INTERRUPT]
    #   connect_bd_intf_net -intf_net axi_linear_flash_EMC_INTF [get_bd_intf_ports linear_flash] [get_bd_intf_pins axi_linear_flash/EMC_INTF]
    #   connect_bd_intf_net -intf_net axi_mem_interconnect_M00_AXI [get_bd_intf_pins axi_ddr_cntrl/S_AXI] [get_bd_intf_pins axi_mem_interconnect/M00_AXI]
    #   connect_bd_intf_net -intf_net sys_dlmb_cntlr_BRAM_PORT [get_bd_intf_pins sys_dlmb_cntlr/BRAM_PORT] [get_bd_intf_pins sys_lmb_bram/BRAM_PORTA]
    #   connect_bd_intf_net -intf_net sys_ilmb_cntlr_BRAM_PORT [get_bd_intf_pins sys_ilmb_cntlr/BRAM_PORT] [get_bd_intf_pins sys_lmb_bram/BRAM_PORTB]
    #   connect_bd_intf_net -intf_net sys_mb_DLMB [get_bd_intf_pins sys_dlmb/LMB_M] [get_bd_intf_pins sys_mb/DLMB]
    #   connect_bd_intf_net -intf_net sys_mb_ILMB [get_bd_intf_pins sys_ilmb/LMB_M] [get_bd_intf_pins sys_mb/ILMB]
    #   connect_bd_intf_net -intf_net sys_mb_M_AXI_DC [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DC]
    #   connect_bd_intf_net -intf_net sys_mb_M_AXI_IC [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins sys_mb/M_AXI_IC]
    #   connect_bd_intf_net -intf_net sys_mb_debug_MBDEBUG_0 [get_bd_intf_pins sys_mb/DEBUG] [get_bd_intf_pins sys_mb_debug/MBDEBUG_0]
    #   connect_bd_intf_net -intf_net util_ad9361_adc_pack_packed_fifo_wr [get_bd_intf_pins axi_ad9361_adc_dma/fifo_wr] [get_bd_intf_pins util_ad9361_adc_pack/packed_fifo_wr]
    # 
    #   # Create port connections
    #   connect_bd_net -net GND_12_dout [get_bd_pins GND_12/dout] [get_bd_pins axi_ddr_cntrl/device_temp_i]
    #   connect_bd_net -net GND_1_dout [get_bd_pins GND_1/dout] [get_bd_pins sys_concat_intc/In2] [get_bd_pins sys_concat_intc/In3] [get_bd_pins sys_concat_intc/In6] [get_bd_pins sys_concat_intc/In7] [get_bd_pins sys_concat_intc/In8] [get_bd_pins sys_concat_intc/In14] [get_bd_pins sys_concat_intc/In15]
    #   connect_bd_net -net axi_ad9361_adc_data_i0 [get_bd_pins axi_ad9361/adc_data_i0] [get_bd_pins util_ad9361_adc_fifo/din_data_0]
    #   connect_bd_net -net axi_ad9361_adc_data_i1 [get_bd_pins axi_ad9361/adc_data_i1] [get_bd_pins util_ad9361_adc_fifo/din_data_2]
    #   connect_bd_net -net axi_ad9361_adc_data_q0 [get_bd_pins axi_ad9361/adc_data_q0] [get_bd_pins util_ad9361_adc_fifo/din_data_1]
    #   connect_bd_net -net axi_ad9361_adc_data_q1 [get_bd_pins axi_ad9361/adc_data_q1] [get_bd_pins util_ad9361_adc_fifo/din_data_3]
    #   connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In12]
    #   connect_bd_net -net axi_ad9361_adc_enable_i0 [get_bd_pins axi_ad9361/adc_enable_i0] [get_bd_pins util_ad9361_adc_fifo/din_enable_0]
    #   connect_bd_net -net axi_ad9361_adc_enable_i1 [get_bd_pins axi_ad9361/adc_enable_i1] [get_bd_pins util_ad9361_adc_fifo/din_enable_2]
    #   connect_bd_net -net axi_ad9361_adc_enable_q0 [get_bd_pins axi_ad9361/adc_enable_q0] [get_bd_pins util_ad9361_adc_fifo/din_enable_1]
    #   connect_bd_net -net axi_ad9361_adc_enable_q1 [get_bd_pins axi_ad9361/adc_enable_q1] [get_bd_pins util_ad9361_adc_fifo/din_enable_3]
    #   connect_bd_net -net axi_ad9361_adc_r1_mode [get_bd_pins axi_ad9361/adc_r1_mode] [get_bd_pins util_ad9361_divclk_sel_concat/In0]
    #   connect_bd_net -net axi_ad9361_adc_valid_i0 [get_bd_pins axi_ad9361/adc_valid_i0] [get_bd_pins util_ad9361_adc_fifo/din_valid_0]
    #   connect_bd_net -net axi_ad9361_adc_valid_i1 [get_bd_pins axi_ad9361/adc_valid_i1] [get_bd_pins util_ad9361_adc_fifo/din_valid_2]
    #   connect_bd_net -net axi_ad9361_adc_valid_q0 [get_bd_pins axi_ad9361/adc_valid_q0] [get_bd_pins util_ad9361_adc_fifo/din_valid_1]
    #   connect_bd_net -net axi_ad9361_adc_valid_q1 [get_bd_pins axi_ad9361/adc_valid_q1] [get_bd_pins util_ad9361_adc_fifo/din_valid_3]
    #   connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In13]
    #   connect_bd_net -net axi_ad9361_dac_enable_i0 [get_bd_pins axi_ad9361/dac_enable_i0] [get_bd_pins axi_ad9361_dac_fifo/dout_enable_0]
    #   connect_bd_net -net axi_ad9361_dac_enable_i1 [get_bd_pins axi_ad9361/dac_enable_i1] [get_bd_pins axi_ad9361_dac_fifo/dout_enable_2]
    #   connect_bd_net -net axi_ad9361_dac_enable_q0 [get_bd_pins axi_ad9361/dac_enable_q0] [get_bd_pins axi_ad9361_dac_fifo/dout_enable_1]
    #   connect_bd_net -net axi_ad9361_dac_enable_q1 [get_bd_pins axi_ad9361/dac_enable_q1] [get_bd_pins axi_ad9361_dac_fifo/dout_enable_3]
    #   connect_bd_net -net axi_ad9361_dac_fifo_din_enable_0 [get_bd_pins axi_ad9361_dac_fifo/din_enable_0] [get_bd_pins util_ad9361_dac_upack/enable_0]
    #   connect_bd_net -net axi_ad9361_dac_fifo_din_enable_1 [get_bd_pins axi_ad9361_dac_fifo/din_enable_1] [get_bd_pins util_ad9361_dac_upack/enable_1]
    #   connect_bd_net -net axi_ad9361_dac_fifo_din_enable_2 [get_bd_pins axi_ad9361_dac_fifo/din_enable_2] [get_bd_pins util_ad9361_dac_upack/enable_2]
    #   connect_bd_net -net axi_ad9361_dac_fifo_din_enable_3 [get_bd_pins axi_ad9361_dac_fifo/din_enable_3] [get_bd_pins util_ad9361_dac_upack/enable_3]
    #   connect_bd_net -net axi_ad9361_dac_fifo_din_valid_0 [get_bd_pins axi_ad9361_dac_fifo/din_valid_0] [get_bd_pins util_ad9361_dac_upack/fifo_rd_en]
    #   connect_bd_net -net axi_ad9361_dac_fifo_dout_data_0 [get_bd_pins axi_ad9361/dac_data_i0] [get_bd_pins axi_ad9361_dac_fifo/dout_data_0]
    #   connect_bd_net -net axi_ad9361_dac_fifo_dout_data_1 [get_bd_pins axi_ad9361/dac_data_q0] [get_bd_pins axi_ad9361_dac_fifo/dout_data_1]
    #   connect_bd_net -net axi_ad9361_dac_fifo_dout_data_2 [get_bd_pins axi_ad9361/dac_data_i1] [get_bd_pins axi_ad9361_dac_fifo/dout_data_2]
    #   connect_bd_net -net axi_ad9361_dac_fifo_dout_data_3 [get_bd_pins axi_ad9361/dac_data_q1] [get_bd_pins axi_ad9361_dac_fifo/dout_data_3]
    #   connect_bd_net -net axi_ad9361_dac_fifo_dout_unf [get_bd_pins axi_ad9361/dac_dunf] [get_bd_pins axi_ad9361_dac_fifo/dout_unf]
    #   connect_bd_net -net axi_ad9361_dac_r1_mode [get_bd_pins axi_ad9361/dac_r1_mode] [get_bd_pins util_ad9361_divclk_sel_concat/In1]
    #   connect_bd_net -net axi_ad9361_dac_valid_i0 [get_bd_pins axi_ad9361/dac_valid_i0] [get_bd_pins axi_ad9361_dac_fifo/dout_valid_0]
    #   connect_bd_net -net axi_ad9361_dac_valid_i1 [get_bd_pins axi_ad9361/dac_valid_i1] [get_bd_pins axi_ad9361_dac_fifo/dout_valid_2]
    #   connect_bd_net -net axi_ad9361_dac_valid_q0 [get_bd_pins axi_ad9361/dac_valid_q0] [get_bd_pins axi_ad9361_dac_fifo/dout_valid_1]
    #   connect_bd_net -net axi_ad9361_dac_valid_q1 [get_bd_pins axi_ad9361/dac_valid_q1] [get_bd_pins axi_ad9361_dac_fifo/dout_valid_3]
    #   connect_bd_net -net axi_ad9361_enable [get_bd_ports enable] [get_bd_pins axi_ad9361/enable]
    #   connect_bd_net -net axi_ad9361_l_clk [get_bd_pins axi_ad9361/clk] [get_bd_pins axi_ad9361/l_clk] [get_bd_pins axi_ad9361_dac_fifo/dout_clk] [get_bd_pins util_ad9361_adc_fifo/din_clk] [get_bd_pins util_ad9361_divclk/clk]
    #   connect_bd_net -net axi_ad9361_rst [get_bd_pins axi_ad9361/rst] [get_bd_pins axi_ad9361_dac_fifo/dout_rst] [get_bd_pins util_ad9361_adc_fifo/din_rst]
    #   connect_bd_net -net axi_ad9361_tdd_sync_cntr [get_bd_ports tdd_sync_t] [get_bd_pins axi_ad9361/tdd_sync_cntr] [get_bd_pins util_ad9361_tdd_sync/sync_mode]
    #   connect_bd_net -net axi_ad9361_tx_clk_out_n [get_bd_ports tx_clk_out_n] [get_bd_pins axi_ad9361/tx_clk_out_n]
    #   connect_bd_net -net axi_ad9361_tx_clk_out_p [get_bd_ports tx_clk_out_p] [get_bd_pins axi_ad9361/tx_clk_out_p]
    #   connect_bd_net -net axi_ad9361_tx_data_out_n [get_bd_ports tx_data_out_n] [get_bd_pins axi_ad9361/tx_data_out_n]
    #   connect_bd_net -net axi_ad9361_tx_data_out_p [get_bd_ports tx_data_out_p] [get_bd_pins axi_ad9361/tx_data_out_p]
    #   connect_bd_net -net axi_ad9361_tx_frame_out_n [get_bd_ports tx_frame_out_n] [get_bd_pins axi_ad9361/tx_frame_out_n]
    #   connect_bd_net -net axi_ad9361_tx_frame_out_p [get_bd_ports tx_frame_out_p] [get_bd_pins axi_ad9361/tx_frame_out_p]
    #   connect_bd_net -net axi_ad9361_txnrx [get_bd_ports txnrx] [get_bd_pins axi_ad9361/txnrx]
    #   connect_bd_net -net axi_ddr_cntrl_mmcm_locked [get_bd_pins axi_ddr_cntrl/mmcm_locked] [get_bd_pins sys_200m_rstgen/dcm_locked] [get_bd_pins sys_rstgen/dcm_locked]
    #   connect_bd_net -net axi_ethernet_ip2intc_irpt [get_bd_pins axi_ethernet/ip2intc_irpt] [get_bd_pins sys_concat_intc/In1]
    #   connect_bd_net -net axi_gpio_gpio2_io_o [get_bd_ports gpio1_o] [get_bd_pins axi_gpio/gpio2_io_o]
    #   connect_bd_net -net axi_gpio_gpio2_io_t [get_bd_ports gpio1_t] [get_bd_pins axi_gpio/gpio2_io_t]
    #   connect_bd_net -net axi_gpio_gpio_io_o [get_bd_ports gpio0_o] [get_bd_pins axi_gpio/gpio_io_o]
    #   connect_bd_net -net axi_gpio_gpio_io_t [get_bd_ports gpio0_t] [get_bd_pins axi_gpio/gpio_io_t]
    #   connect_bd_net -net axi_gpio_ip2intc_irpt [get_bd_pins axi_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In11]
    #   connect_bd_net -net axi_gpio_lcd_ip2intc_irpt [get_bd_pins axi_gpio_lcd/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5]
    #   connect_bd_net -net axi_iic_main_iic2intc_irpt [get_bd_pins axi_iic_main/iic2intc_irpt] [get_bd_pins sys_concat_intc/In9]
    #   connect_bd_net -net axi_spi_io0_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_spi/io0_o]
    #   connect_bd_net -net axi_spi_ip2intc_irpt [get_bd_pins axi_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In10]
    #   connect_bd_net -net axi_spi_sck_o [get_bd_ports spi_clk_o] [get_bd_pins axi_spi/sck_o]
    #   connect_bd_net -net axi_spi_ss_o [get_bd_ports spi_csn_o] [get_bd_pins axi_spi/ss_o]
    #   connect_bd_net -net axi_sysid_0_rom_addr [get_bd_pins axi_sysid_0/rom_addr] [get_bd_pins rom_sys_0/rom_addr]
    #   connect_bd_net -net axi_timer_interrupt [get_bd_pins axi_timer/interrupt] [get_bd_pins sys_concat_intc/In0]
    #   connect_bd_net -net axi_uart_interrupt [get_bd_pins axi_uart/interrupt] [get_bd_pins sys_concat_intc/In4]
    #   connect_bd_net -net axi_uart_tx [get_bd_ports uart_sout] [get_bd_pins axi_uart/tx]
    #   connect_bd_net -net gpio0_i_1 [get_bd_ports gpio0_i] [get_bd_pins axi_gpio/gpio_io_i]
    #   connect_bd_net -net gpio1_i_1 [get_bd_ports gpio1_i] [get_bd_pins axi_gpio/gpio2_io_i]
    #   connect_bd_net -net rom_sys_0_rom_data [get_bd_pins axi_sysid_0/sys_rom_data] [get_bd_pins rom_sys_0/rom_data]
    #   connect_bd_net -net rx_clk_in_n_1 [get_bd_ports rx_clk_in_n] [get_bd_pins axi_ad9361/rx_clk_in_n]
    #   connect_bd_net -net rx_clk_in_p_1 [get_bd_ports rx_clk_in_p] [get_bd_pins axi_ad9361/rx_clk_in_p]
    #   connect_bd_net -net rx_data_in_n_1 [get_bd_ports rx_data_in_n] [get_bd_pins axi_ad9361/rx_data_in_n]
    #   connect_bd_net -net rx_data_in_p_1 [get_bd_ports rx_data_in_p] [get_bd_pins axi_ad9361/rx_data_in_p]
    #   connect_bd_net -net rx_frame_in_n_1 [get_bd_ports rx_frame_in_n] [get_bd_pins axi_ad9361/rx_frame_in_n]
    #   connect_bd_net -net rx_frame_in_p_1 [get_bd_ports rx_frame_in_p] [get_bd_pins axi_ad9361/rx_frame_in_p]
    #   connect_bd_net -net spi_clk_i_1 [get_bd_ports spi_clk_i] [get_bd_pins axi_spi/sck_i]
    #   connect_bd_net -net spi_csn_i_1 [get_bd_ports spi_csn_i] [get_bd_pins axi_spi/ss_i]
    #   connect_bd_net -net spi_sdi_i_1 [get_bd_ports spi_sdi_i] [get_bd_pins axi_spi/io1_i]
    #   connect_bd_net -net spi_sdo_i_1 [get_bd_ports spi_sdo_i] [get_bd_pins axi_spi/io0_i]
    #   connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9361/delay_clk] [get_bd_pins axi_ddr_cntrl/ui_clk] [get_bd_pins axi_mem_interconnect/aclk] [get_bd_pins sys_200m_rstgen/slowest_sync_clk]
    #   connect_bd_net -net sys_200m_reset [get_bd_pins sys_200m_rstgen/peripheral_reset]
    #   connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/aresetn] [get_bd_pins sys_200m_rstgen/peripheral_aresetn]
    #   connect_bd_net -net sys_200m_rst [get_bd_pins axi_ddr_cntrl/ui_clk_sync_rst] [get_bd_pins sys_200m_rstgen/ext_reset_in]
    #   connect_bd_net -net sys_clk_n_1 [get_bd_ports sys_clk_n] [get_bd_pins axi_ddr_cntrl/sys_clk_n]
    #   connect_bd_net -net sys_clk_p_1 [get_bd_ports sys_clk_p] [get_bd_pins axi_ddr_cntrl/sys_clk_p]
    #   connect_bd_net -net sys_concat_intc_dout [get_bd_pins axi_intc/intr] [get_bd_pins sys_concat_intc/dout]
    #   connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ad9361/s_axi_aclk] [get_bd_pins axi_ad9361_adc_dma/m_dest_axi_aclk] [get_bd_pins axi_ad9361_adc_dma/s_axi_aclk] [get_bd_pins axi_ad9361_dac_dma/m_src_axi_aclk] [get_bd_pins axi_ad9361_dac_dma/s_axi_aclk] [get_bd_pins axi_cpu_interconnect/ACLK] [get_bd_pins axi_cpu_interconnect/M00_ACLK] [get_bd_pins axi_cpu_interconnect/M01_ACLK] [get_bd_pins axi_cpu_interconnect/M02_ACLK] [get_bd_pins axi_cpu_interconnect/M03_ACLK] [get_bd_pins axi_cpu_interconnect/M04_ACLK] [get_bd_pins axi_cpu_interconnect/M05_ACLK] [get_bd_pins axi_cpu_interconnect/M06_ACLK] [get_bd_pins axi_cpu_interconnect/M07_ACLK] [get_bd_pins axi_cpu_interconnect/M08_ACLK] [get_bd_pins axi_cpu_interconnect/M09_ACLK] [get_bd_pins axi_cpu_interconnect/M10_ACLK] [get_bd_pins axi_cpu_interconnect/M11_ACLK] [get_bd_pins axi_cpu_interconnect/M12_ACLK] [get_bd_pins axi_cpu_interconnect/M13_ACLK] [get_bd_pins axi_cpu_interconnect/S00_ACLK] [get_bd_pins axi_ddr_cntrl/ui_addn_clk_0] [get_bd_pins axi_ethernet/s_axi_aclk] [get_bd_pins axi_gpio/s_axi_aclk] [get_bd_pins axi_gpio_lcd/s_axi_aclk] [get_bd_pins axi_iic_main/s_axi_aclk] [get_bd_pins axi_intc/s_axi_aclk] [get_bd_pins axi_linear_flash/rdclk] [get_bd_pins axi_linear_flash/s_axi_aclk] [get_bd_pins axi_mem_interconnect/aclk1] [get_bd_pins axi_spi/ext_spi_clk] [get_bd_pins axi_spi/s_axi_aclk] [get_bd_pins axi_sysid_0/s_axi_aclk] [get_bd_pins axi_timer/s_axi_aclk] [get_bd_pins axi_uart/s_axi_aclk] [get_bd_pins rom_sys_0/clk] [get_bd_pins sys_dlmb/LMB_Clk] [get_bd_pins sys_dlmb_cntlr/LMB_Clk] [get_bd_pins sys_ilmb/LMB_Clk] [get_bd_pins sys_ilmb_cntlr/LMB_Clk] [get_bd_pins sys_mb/Clk] [get_bd_pins sys_mb_debug/S_AXI_ACLK] [get_bd_pins sys_rstgen/slowest_sync_clk] [get_bd_pins util_ad9361_tdd_sync/clk]
    #   connect_bd_net -net sys_cpu_reset [get_bd_pins sys_rstgen/peripheral_reset]
    #   connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_ad9361/s_axi_aresetn] [get_bd_pins axi_ad9361_adc_dma/m_dest_axi_aresetn] [get_bd_pins axi_ad9361_adc_dma/s_axi_aresetn] [get_bd_pins axi_ad9361_dac_dma/m_src_axi_aresetn] [get_bd_pins axi_ad9361_dac_dma/s_axi_aresetn] [get_bd_pins axi_cpu_interconnect/ARESETN] [get_bd_pins axi_cpu_interconnect/M00_ARESETN] [get_bd_pins axi_cpu_interconnect/M01_ARESETN] [get_bd_pins axi_cpu_interconnect/M02_ARESETN] [get_bd_pins axi_cpu_interconnect/M03_ARESETN] [get_bd_pins axi_cpu_interconnect/M04_ARESETN] [get_bd_pins axi_cpu_interconnect/M05_ARESETN] [get_bd_pins axi_cpu_interconnect/M06_ARESETN] [get_bd_pins axi_cpu_interconnect/M07_ARESETN] [get_bd_pins axi_cpu_interconnect/M08_ARESETN] [get_bd_pins axi_cpu_interconnect/M09_ARESETN] [get_bd_pins axi_cpu_interconnect/M10_ARESETN] [get_bd_pins axi_cpu_interconnect/M11_ARESETN] [get_bd_pins axi_cpu_interconnect/M12_ARESETN] [get_bd_pins axi_cpu_interconnect/M13_ARESETN] [get_bd_pins axi_cpu_interconnect/S00_ARESETN] [get_bd_pins axi_ddr_cntrl/aresetn] [get_bd_pins axi_ethernet/s_axi_aresetn] [get_bd_pins axi_gpio/s_axi_aresetn] [get_bd_pins axi_gpio_lcd/s_axi_aresetn] [get_bd_pins axi_iic_main/s_axi_aresetn] [get_bd_pins axi_intc/s_axi_aresetn] [get_bd_pins axi_linear_flash/s_axi_aresetn] [get_bd_pins axi_spi/s_axi_aresetn] [get_bd_pins axi_sysid_0/s_axi_aresetn] [get_bd_pins axi_timer/s_axi_aresetn] [get_bd_pins axi_uart/s_axi_aresetn] [get_bd_pins sys_mb_debug/S_AXI_ARESETN] [get_bd_pins sys_rstgen/peripheral_aresetn] [get_bd_pins util_ad9361_divclk_reset/ext_reset_in] [get_bd_pins util_ad9361_tdd_sync/rstn]
    #   connect_bd_net -net sys_mb_debug_Debug_SYS_Rst [get_bd_pins sys_mb_debug/Debug_SYS_Rst] [get_bd_pins sys_rstgen/mb_debug_sys_rst]
    #   connect_bd_net -net sys_rst_1 [get_bd_ports sys_rst] [get_bd_pins axi_ddr_cntrl/sys_rst] [get_bd_pins sys_rstgen/ext_reset_in]
    #   connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_dlmb/SYS_Rst] [get_bd_pins sys_dlmb_cntlr/LMB_Rst] [get_bd_pins sys_ilmb/SYS_Rst] [get_bd_pins sys_ilmb_cntlr/LMB_Rst] [get_bd_pins sys_rstgen/bus_struct_reset]
    #   connect_bd_net -net sys_rstgen_mb_reset [get_bd_pins sys_mb/Reset] [get_bd_pins sys_rstgen/mb_reset]
    #   connect_bd_net -net tdd_sync_i_1 [get_bd_ports tdd_sync_i] [get_bd_pins util_ad9361_tdd_sync/sync_in]
    #   connect_bd_net -net uart_sin_1 [get_bd_ports uart_sin] [get_bd_pins axi_uart/rx]
    #   connect_bd_net -net up_enable_1 [get_bd_ports up_enable] [get_bd_pins axi_ad9361/up_enable]
    #   connect_bd_net -net up_txnrx_1 [get_bd_ports up_txnrx] [get_bd_pins axi_ad9361/up_txnrx]
    #   connect_bd_net -net util_ad9361_adc_fifo_din_ovf [get_bd_pins axi_ad9361/adc_dovf] [get_bd_pins util_ad9361_adc_fifo/din_ovf]
    #   connect_bd_net -net util_ad9361_adc_fifo_dout_data_0 [get_bd_pins util_ad9361_adc_fifo/dout_data_0] [get_bd_pins util_ad9361_adc_pack/fifo_wr_data_0]
    #   connect_bd_net -net util_ad9361_adc_fifo_dout_data_1 [get_bd_pins util_ad9361_adc_fifo/dout_data_1] [get_bd_pins util_ad9361_adc_pack/fifo_wr_data_1]
    #   connect_bd_net -net util_ad9361_adc_fifo_dout_data_2 [get_bd_pins util_ad9361_adc_fifo/dout_data_2] [get_bd_pins util_ad9361_adc_pack/fifo_wr_data_2]
    #   connect_bd_net -net util_ad9361_adc_fifo_dout_data_3 [get_bd_pins util_ad9361_adc_fifo/dout_data_3] [get_bd_pins util_ad9361_adc_pack/fifo_wr_data_3]
    #   connect_bd_net -net util_ad9361_adc_fifo_dout_enable_0 [get_bd_pins util_ad9361_adc_fifo/dout_enable_0] [get_bd_pins util_ad9361_adc_pack/enable_0]
    #   connect_bd_net -net util_ad9361_adc_fifo_dout_enable_1 [get_bd_pins util_ad9361_adc_fifo/dout_enable_1] [get_bd_pins util_ad9361_adc_pack/enable_1]
    #   connect_bd_net -net util_ad9361_adc_fifo_dout_enable_2 [get_bd_pins util_ad9361_adc_fifo/dout_enable_2] [get_bd_pins util_ad9361_adc_pack/enable_2]
    #   connect_bd_net -net util_ad9361_adc_fifo_dout_enable_3 [get_bd_pins util_ad9361_adc_fifo/dout_enable_3] [get_bd_pins util_ad9361_adc_pack/enable_3]
    #   connect_bd_net -net util_ad9361_adc_fifo_dout_valid_0 [get_bd_pins util_ad9361_adc_fifo/dout_valid_0] [get_bd_pins util_ad9361_adc_pack/fifo_wr_en]
    #   connect_bd_net -net util_ad9361_adc_pack_fifo_wr_overflow [get_bd_pins util_ad9361_adc_fifo/dout_ovf] [get_bd_pins util_ad9361_adc_pack/fifo_wr_overflow]
    #   connect_bd_net -net util_ad9361_dac_upack_fifo_rd_data_0 [get_bd_pins axi_ad9361_dac_fifo/din_data_0] [get_bd_pins util_ad9361_dac_upack/fifo_rd_data_0]
    #   connect_bd_net -net util_ad9361_dac_upack_fifo_rd_data_1 [get_bd_pins axi_ad9361_dac_fifo/din_data_1] [get_bd_pins util_ad9361_dac_upack/fifo_rd_data_1]
    #   connect_bd_net -net util_ad9361_dac_upack_fifo_rd_data_2 [get_bd_pins axi_ad9361_dac_fifo/din_data_2] [get_bd_pins util_ad9361_dac_upack/fifo_rd_data_2]
    #   connect_bd_net -net util_ad9361_dac_upack_fifo_rd_data_3 [get_bd_pins axi_ad9361_dac_fifo/din_data_3] [get_bd_pins util_ad9361_dac_upack/fifo_rd_data_3]
    #   connect_bd_net -net util_ad9361_dac_upack_fifo_rd_underflow [get_bd_pins axi_ad9361_dac_fifo/din_unf] [get_bd_pins util_ad9361_dac_upack/fifo_rd_underflow]
    #   connect_bd_net -net util_ad9361_dac_upack_fifo_rd_valid [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_0] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_1] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_2] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_3] [get_bd_pins util_ad9361_dac_upack/fifo_rd_valid]
    #   connect_bd_net -net util_ad9361_divclk_clk_out [get_bd_pins axi_ad9361_adc_dma/fifo_wr_clk] [get_bd_pins axi_ad9361_dac_dma/m_axis_aclk] [get_bd_pins axi_ad9361_dac_fifo/din_clk] [get_bd_pins util_ad9361_adc_fifo/dout_clk] [get_bd_pins util_ad9361_adc_pack/clk] [get_bd_pins util_ad9361_dac_upack/clk] [get_bd_pins util_ad9361_divclk/clk_out] [get_bd_pins util_ad9361_divclk_reset/slowest_sync_clk]
    #   connect_bd_net -net util_ad9361_divclk_reset_peripheral_aresetn [get_bd_pins axi_ad9361_dac_fifo/din_rstn] [get_bd_pins util_ad9361_adc_fifo/dout_rstn] [get_bd_pins util_ad9361_divclk_reset/peripheral_aresetn]
    #   connect_bd_net -net util_ad9361_divclk_reset_peripheral_reset [get_bd_pins util_ad9361_adc_pack/reset] [get_bd_pins util_ad9361_dac_upack/reset] [get_bd_pins util_ad9361_divclk_reset/peripheral_reset]
    #   connect_bd_net -net util_ad9361_divclk_sel_Res [get_bd_pins util_ad9361_divclk/clk_sel] [get_bd_pins util_ad9361_divclk_sel/Res]
    #   connect_bd_net -net util_ad9361_divclk_sel_concat_dout [get_bd_pins util_ad9361_divclk_sel/Op1] [get_bd_pins util_ad9361_divclk_sel_concat/dout]
    #   connect_bd_net -net util_ad9361_tdd_sync_sync_out [get_bd_ports tdd_sync_o] [get_bd_pins axi_ad9361/tdd_sync] [get_bd_pins util_ad9361_tdd_sync/sync_out]
    # 
    #   # Create address segments
    #   assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces axi_ad9361_adc_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] -force
    #   assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces axi_ad9361_dac_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] -force
    #   assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] -force
    #   assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] -force
    #   assign_bd_address -offset 0x79020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ad9361/s_axi/axi_lite] -force
    #   assign_bd_address -offset 0x7C400000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ad9361_adc_dma/s_axi/axi_lite] -force
    #   assign_bd_address -offset 0x7C420000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ad9361_dac_dma/s_axi/axi_lite] -force
    #   assign_bd_address -offset 0x40E00000 -range 0x00002000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ethernet/S_AXI/Reg] -force
    #   assign_bd_address -offset 0x40000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_gpio/S_AXI/Reg] -force
    #   assign_bd_address -offset 0x40010000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_gpio_lcd/S_AXI/Reg] -force
    #   assign_bd_address -offset 0x41600000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_iic_main/S_AXI/Reg] -force
    #   assign_bd_address -offset 0x41200000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_intc/S_AXI/Reg] -force
    #   assign_bd_address -offset 0x60000000 -range 0x02000000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_linear_flash/S_AXI_MEM/Mem0] -force
    #   assign_bd_address -offset 0x44A70000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_spi/AXI_LITE/Reg] -force
    #   assign_bd_address -offset 0x45000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_sysid_0/s_axi/axi_lite] -force
    #   assign_bd_address -offset 0x41C00000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_timer/S_AXI/Reg] -force
    #   assign_bd_address -offset 0x40600000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_uart/S_AXI/Reg] -force
    #   assign_bd_address -offset 0x41400000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs sys_mb_debug/S_AXI/Reg] -force
    #   assign_bd_address -offset 0x00000000 -range 0x00020000 -target_address_space [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] -force
    #   assign_bd_address -offset 0x00000000 -range 0x00020000 -target_address_space [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] -force
    # 
    # 
    #   # Restore current instance
    #   current_bd_instance $oldCurInst
    # 
    #   validate_bd_design
    #   save_bd_design
    # }
    # create_root_design ""
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vck190/es/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.0 available at /home/lnagy/.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2020.1/boards/Xilinx/vmk180/es/1.0/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
    WARNING: [BD 41-1753] The name 'util_ad9361_divclk_sel_concat' you have specified is long. The Windows OS has path length limitations. It is recommended you use shorter names(less than 25 characters) to reduce the likelihood of issues when/if running on windows OS.
    WARNING: [BD 41-1306] The connection to interface pin /axi_gpio/gpio2_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO2
    WARNING: [BD 41-1306] The connection to interface pin /axi_gpio/gpio2_io_t is being overridden by the user. This pin will not be connected as a part of interface connection GPIO2
    WARNING: [BD 41-1306] The connection to interface pin /axi_gpio/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
    WARNING: [BD 41-1306] The connection to interface pin /axi_gpio/gpio_io_t is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
    WARNING: [BD 41-1306] The connection to interface pin /axi_spi/io0_o is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    WARNING: [BD 41-1306] The connection to interface pin /axi_spi/sck_o is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    WARNING: [BD 41-1306] The connection to interface pin /axi_spi/ss_o is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    WARNING: [BD 41-1306] The connection to interface pin /axi_uart/tx is being overridden by the user. This pin will not be connected as a part of interface connection UART
    WARNING: [BD 41-1306] The connection to interface pin /axi_gpio/gpio_io_i is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
    WARNING: [BD 41-1306] The connection to interface pin /axi_gpio/gpio2_io_i is being overridden by the user. This pin will not be connected as a part of interface connection GPIO2
    WARNING: [BD 41-1306] The connection to interface pin /axi_spi/sck_i is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    WARNING: [BD 41-1306] The connection to interface pin /axi_spi/ss_i is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    WARNING: [BD 41-1306] The connection to interface pin /axi_spi/io1_i is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    WARNING: [BD 41-1306] The connection to interface pin /axi_spi/io0_i is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
    WARNING: [BD 41-1306] The connection to interface pin /axi_ddr_cntrl/sys_clk_n is being overridden by the user. This pin will not be connected as a part of interface connection SYS_CLK
    WARNING: [BD 41-1306] The connection to interface pin /axi_ddr_cntrl/sys_clk_p is being overridden by the user. This pin will not be connected as a part of interface connection SYS_CLK
    WARNING: [BD 41-1306] The connection to interface pin /axi_uart/rx is being overridden by the user. This pin will not be connected as a part of interface connection UART
    Slave segment '/axi_ddr_cntrl/memmap/memaddr' is being assigned into address space '/axi_ad9361_adc_dma/m_dest_axi' at <0x8000_0000 [ 1G ]>.
    Slave segment '/axi_ddr_cntrl/memmap/memaddr' is being assigned into address space '/axi_ad9361_dac_dma/m_src_axi' at <0x8000_0000 [ 1G ]>.
    Slave segment '/axi_ddr_cntrl/memmap/memaddr' is being assigned into address space '/sys_mb/Data' at <0x8000_0000 [ 1G ]>.
    Slave segment '/axi_ddr_cntrl/memmap/memaddr' is being assigned into address space '/sys_mb/Instruction' at <0x8000_0000 [ 1G ]>.
    Slave segment '/axi_ad9361/s_axi/axi_lite' is being assigned into address space '/sys_mb/Data' at <0x7902_0000 [ 64K ]>.
    Slave segment '/axi_ad9361_adc_dma/s_axi/axi_lite' is being assigned into address space '/sys_mb/Data' at <0x7C40_0000 [ 4K ]>.
    Slave segment '/axi_ad9361_dac_dma/s_axi/axi_lite' is being assigned into address space '/sys_mb/Data' at <0x7C42_0000 [ 4K ]>.
    Slave segment '/axi_ethernet/S_AXI/Reg' is being assigned into address space '/sys_mb/Data' at <0x40E0_0000 [ 8K ]>.
    Slave segment '/axi_gpio/S_AXI/Reg' is being assigned into address space '/sys_mb/Data' at <0x4000_0000 [ 4K ]>.
    Slave segment '/axi_gpio_lcd/S_AXI/Reg' is being assigned into address space '/sys_mb/Data' at <0x4001_0000 [ 4K ]>.
    Slave segment '/axi_iic_main/S_AXI/Reg' is being assigned into address space '/sys_mb/Data' at <0x4160_0000 [ 4K ]>.
    Slave segment '/axi_intc/S_AXI/Reg' is being assigned into address space '/sys_mb/Data' at <0x4120_0000 [ 4K ]>.
    Slave segment '/axi_linear_flash/S_AXI_MEM/Mem0' is being assigned into address space '/sys_mb/Data' at <0x6000_0000 [ 32M ]>.
    Slave segment '/axi_spi/AXI_LITE/Reg' is being assigned into address space '/sys_mb/Data' at <0x44A7_0000 [ 4K ]>.
    Slave segment '/axi_sysid_0/s_axi/axi_lite' is being assigned into address space '/sys_mb/Data' at <0x4500_0000 [ 64K ]>.
    Slave segment '/axi_timer/S_AXI/Reg' is being assigned into address space '/sys_mb/Data' at <0x41C0_0000 [ 4K ]>.
    Slave segment '/axi_uart/S_AXI/Reg' is being assigned into address space '/sys_mb/Data' at <0x4060_0000 [ 4K ]>.
    Slave segment '/sys_mb_debug/S_AXI/Reg' is being assigned into address space '/sys_mb/Data' at <0x4140_0000 [ 4K ]>.
    Slave segment '/sys_dlmb_cntlr/SLMB/Mem' is being assigned into address space '/sys_mb/Data' at <0x0000_0000 [ 128K ]>.
    Slave segment '/sys_ilmb_cntlr/SLMB/Mem' is being assigned into address space '/sys_mb/Instruction' at <0x0000_0000 [ 128K ]>.
    INFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /axi_spi 
                       #######################################################################################
                       INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are synchronous to each other.
                       ########################################################################################
    INFO: [xilinx.com:ip:microblaze:11.0-16] /sys_mb: Setting D-cache cacheable area base address C_DCACHE_BASEADDR to 0x80000000 and high address C_DCACHE_HIGHADDR to 0xBFFFFFFF.
    INFO: [xilinx.com:ip:microblaze:11.0-16] /sys_mb: Setting I-cache cacheable area base address C_ICACHE_BASEADDR to 0x80000000 and high address C_ICACHE_HIGHADDR to 0xBFFFFFFF.
    WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_intc: Property SENSITIVITY = "NULL" for interrupt input 15 not recognized - using default interrupt type Rising Edge. Please change this manually if necessary.
    WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_intc: Property SENSITIVITY = "NULL" for interrupt input 14 not recognized - using default interrupt type Rising Edge. Please change this manually if necessary.
    WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_intc: Property SENSITIVITY = "NULL" for interrupt input 8 not recognized - using default interrupt type Rising Edge. Please change this manually if necessary.
    WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_intc: Property SENSITIVITY = "NULL" for interrupt input 7 not recognized - using default interrupt type Rising Edge. Please change this manually if necessary.
    WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_intc: Property SENSITIVITY = "NULL" for interrupt input 6 not recognized - using default interrupt type Rising Edge. Please change this manually if necessary.
    WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_intc: Property SENSITIVITY = "NULL" for interrupt input 3 not recognized - using default interrupt type Rising Edge. Please change this manually if necessary.
    WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_intc: Property SENSITIVITY = "NULL" for interrupt input 2 not recognized - using default interrupt type Rising Edge. Please change this manually if necessary.
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/delay_clk have been updated from connected ip, but BD cell '/axi_ad9361' does not accept parameter changes, so they may not be synchronized with cell properties:
    	PHASE = 0 
    Please resolve any mismatches by directly setting properties on BD cell </axi_ad9361> to completely resolve these warnings.
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361/s_axi_aclk have been updated from connected ip, but BD cell '/axi_ad9361' does not accept parameter changes, so they may not be synchronized with cell properties:
    	PHASE = 0 
    Please resolve any mismatches by directly setting properties on BD cell </axi_ad9361> to completely resolve these warnings.
    WARNING: [BD 41-927] Following properties on pin /axi_ad9361_dac_fifo/dout_rst have been updated from connected ip, but BD cell '/axi_ad9361_dac_fifo' does not accept parameter changes, so they may not be synchronized with cell properties:
    	POLARITY = ACTIVE_HIGH 
    Please resolve any mismatches by directly setting properties on BD cell </axi_ad9361_dac_fifo> to completely resolve these warnings.
    WARNING: [BD 41-927] Following properties on pin /axi_sysid_0/s_axi_aclk have been updated from connected ip, but BD cell '/axi_sysid_0' does not accept parameter changes, so they may not be synchronized with cell properties:
    	PHASE = 0 
    Please resolve any mismatches by directly setting properties on BD cell </axi_sysid_0> to completely resolve these warnings.
    WARNING: [BD 41-927] Following properties on pin /rom_sys_0/clk have been updated from connected ip, but BD cell '/rom_sys_0' does not accept parameter changes, so they may not be synchronized with cell properties:
    	PHASE = 0 
    Please resolve any mismatches by directly setting properties on BD cell </rom_sys_0> to completely resolve these warnings.
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_adc_fifo/din_rst have been updated from connected ip, but BD cell '/util_ad9361_adc_fifo' does not accept parameter changes, so they may not be synchronized with cell properties:
    	POLARITY = ACTIVE_HIGH 
    Please resolve any mismatches by directly setting properties on BD cell </util_ad9361_adc_fifo> to completely resolve these warnings.
    WARNING: [BD 41-927] Following properties on pin /util_ad9361_tdd_sync/clk have been updated from connected ip, but BD cell '/util_ad9361_tdd_sync' does not accept parameter changes, so they may not be synchronized with cell properties:
    	PHASE = 0 
    Please resolve any mismatches by directly setting properties on BD cell </util_ad9361_tdd_sync> to completely resolve these warnings.
    WARNING: [BD 41-1771] Block interface /axi_ethernet/MDIO has associated board param 'MDIO_BOARD_INTERFACE', which is set to board part interface 'mdio_mdc'. This interface is connected to an external interface /mdio, whose name 'mdio' does not match with the board interface name 'mdio_mdc'.
    This is a visual-only issue - this interface /axi_ethernet/MDIO will be connected to board interface 'mdio_mdc'. If desired, please change the name of this port /mdio manually.
    validate_bd_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 9050.668 ; gain = 0.000 ; free physical = 3071 ; free virtual = 60119
    Wrote  : </export/data/test/write_bd_Tcl_test/project_1/project_1.srcs/sources_1/bd/BLABLA/BLABLA.bd> 
    Wrote  : </export/data/test/write_bd_Tcl_test/project_1/project_1.srcs/sources_1/bd/BLABLA/ui/bd_b3bac500.ui> 
    

Children
  • Thank you for the details, I appreciate it!!!!  I will give that a shot this afternoon.  So you just pointed to where you had all the IP using that command and hit refresh?  Because I //think// that is the same thing I did (I did it via the gui) yet got that weird error (which to me doesn't look like an IP catalogue issue).  I'll report back either way though. Thanks again.

    I actually I just tried it and it wasn't happy.  Here is a snippet of the end of the output after re-sourcing:

    <<<begin snip>>>
    # } else {
    #    # USE CASES:
    #    #    8) No opened design, design_name not in project.
    #    #    9) Current opened design, has components, but diff names, design_name not in project.
    # 
    #    common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
    # 
    #    create_bd_design $design_name
    # 
    #    common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
    #    current_bd_design $design_name
    # 
    # }
    # common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
    INFO: [BD::TCL 103-2005] Currently the variable <design_name> is equal to "BLAHBLAHBLAH".
    # if { $nRet != 0 } {
    #    catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
    #    return $nRet
    # }
    ERROR: [BD::TCL 103-2006] Design <BLAHBLAHBLAH> already exists in your project, please set the variable <design_name> to another value.
    1

  • 0
    •  Analog Employees 
    on May 3, 2021 6:22 AM in reply to GarEngLLC

    ERROR: [BD::TCL 103-2006] Design <BLAHBLAHBLAH> already exists in your project, please set the variable <design_name> to another value.

    try to clean up the workspace before you source the tcl file.

    Laszlo

  • Hello.
    Do you mean manually?  Or is there a tcl command that should do the trick?

  • 0
    •  Analog Employees 
    on May 3, 2021 6:37 PM in reply to GarEngLLC

    Well,  you could delete manually the block design, but this is more a Vivado flow question.  If you encounter such issues please open a question on the Xilinx forums. 

    Laszlo

  • Good point, I will. Last question for you.  Did the design pass timing when you tried it?  While getting the design to work in a new folder, I went back to the original one and was curious why it didn't pass timing out of the box for me.