IP core for AXI streaming with IIO support

How do you want data to flow in your system? Can you just put the core inline with the current DMA and interface core?

-Travis

Sorry for the confusion.  This other AXIS device is completely independent from the ad7768.

I want data to stream from linux/zynq via libiio to an AXIS device as though it were a DAC.  I was thinking there might be an existing core for some other DAC that I could repurpose for this.

I would look at the different reference designs with DAC parts: https://github.com/analogdevicesinc/hdl/tree/master/projects

Then the different associated devices trees to show how the drivers are enumerated.

-Travis

Thanks Travis.  It looks like the ad9739a might have the simplest setup and the shortest driver code.  And, like you mentioned before, I can just pick off the stream right after the DMA that goes along with the ad9739a.

I imagine that a driver like ad9739a.c is going to fail to load unless its actually able to find the chip over spi, and find the ip core over axi-lite.

My plan is likely going to be making a modified version of ad9739a.c to bypass those checks, but can you think of anything clever I could do in hardware to be able to leave the driver exactly as-is without actually having an ad9739a on the board?

I searched the reference designs for instances of "CONFIG.DMA_TYPE_DEST 1" which correspond to a DMA engine having an AXIS output.

It seems there are a number of projects (i.e. fmccoms and dac_fmc_ezb) that use this setup.  And it appears that all of those are JESD based transmitters.  Modifying the block designs to get rid of the JESD components seems pretty easy.

The dac_fmc_ezb project supports a number of JESD based eval boards, like the one for the ad9172.  The iio subsytem driver for these components (like iio/ad9172.c) are pretty big, seemingly because of jesd setup.  So those drivers might be less than ideal to modify because of their complexity, but it seems like its the easiest path overall.

So I'm currently thinking of modifying:

This hdl project: github.com/.../dac_fmc_ebz

This dts: github.com/.../zynq-zc706-adv7511-ad9172-fmc-ebz.dts

This linux driver: github.com/.../ad9172.c

OR using teh ad9162 from the fmcomms11 project, which has a slightly easier driver:

This hdl project: github.com/.../fmcomms11

This dts file: github.com/.../zynq-zc706-adv7511-fmcomms11.dts

This linux driver: github.com/.../ad9162.c

So I started making a modified version of the ad9144 (mixed a bit with the ad9122 and ad9361).  Primarily this means making a new c file for my driver (based on ad9122.c, ad9144.c etc.) and also modifying cf_axi_dds.c to have the apporpraite references to my new driver.

Getting rid of jesd in the driver wasn't really an issue.  And even getting rid of spi doesnt seem to be a big deal as I can just pretend that my device has no spi requirements.  This seems to be made easier by setting my driver to 'standalone' mode inside cf_axi_dds.c.

The bigger issue are the standard registers for the cf_axi_dds framework.  Like the ADI_DRP_LOCKED bit in the ADI_REG_DRP_STATUS register.  It seems that there are only a handful of registers that have to be read.

I could make something from scratch to mimic these and give the driver what it wants, but do you know of some common code in the HDL repo that could make this easier? Or maybe some other solution?

Right now I'm thinking of using a combination of up_axi.v (which converts AXI lite to uP) and up_dac_common.v (which contains the register map in uP format), and up_dac_channel.v.  All of which are mentioned in wiki.analog.com/.../axi_dac_ip

So I started making a modified version of the ad9144 (mixed a bit with the ad9122 and ad9361).  Primarily this means making a new c file for my driver (based on ad9122.c, ad9144.c etc.) and also modifying cf_axi_dds.c to have the apporpraite references to my new driver.

Getting rid of jesd in the driver wasn't really an issue.  And even getting rid of spi doesnt seem to be a big deal as I can just pretend that my device has no spi requirements.  This seems to be made easier by setting my driver to 'standalone' mode inside cf_axi_dds.c.

The bigger issue are the standard registers for the cf_axi_dds framework.  Like the ADI_DRP_LOCKED bit in the ADI_REG_DRP_STATUS register.  It seems that there are only a handful of registers that have to be read.

I could make something from scratch to mimic these and give the driver what it wants, but do you know of some common code in the HDL repo that could make this easier? Or maybe some other solution?

Right now I'm thinking of using a combination of up_axi.v (which converts AXI lite to uP) and up_dac_common.v (which contains the register map in uP format), and up_dac_channel.v.  All of which are mentioned in wiki.analog.com/.../axi_dac_ip