IP core for AXI streaming with IIO support

I have a board with an ad7768 adc, and I'm using the ad7768evb demo project to access that devices via libiio.  This works well.

My fpga design also has a custom IP core that accepts an AXIS stream.  I'd also like to use libiio to send data to this device.

Is there an HDL core I could use that would do this, and has iio support in the kernel?



fixed title
[edited by: jay_col at 9:42 PM (GMT -4) on 28 Apr 2021]
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  • So I started making a modified version of the ad9144 (mixed a bit with the ad9122 and ad9361).  Primarily this means making a new c file for my driver (based on ad9122.c, ad9144.c etc.) and also modifying cf_axi_dds.c to have the apporpraite references to my new driver.

    Getting rid of jesd in the driver wasn't really an issue.  And even getting rid of spi doesnt seem to be a big deal as I can just pretend that my device has no spi requirements.  This seems to be made easier by setting my driver to 'standalone' mode inside cf_axi_dds.c.

    The bigger issue are the standard registers for the cf_axi_dds framework.  Like the ADI_DRP_LOCKED bit in the ADI_REG_DRP_STATUS register.  It seems that there are only a handful of registers that have to be read.

    I could make something from scratch to mimic these and give the driver what it wants, but do you know of some common code in the HDL repo that could make this easier? Or maybe some other solution?

    Right now I'm thinking of using a combination of up_axi.v (which converts AXI lite to uP) and up_dac_common.v (which contains the register map in uP format), and up_dac_channel.v.  All of which are mentioned in wiki.analog.com/.../axi_dac_ip