ADRV9002: axi_adrv9001 CSSI

Hello, 

yes it supports 1 lane and 4 lane modes,   SDR and DDR modes.  The driver/software needs to configure it accordingly.

See the documentation here, fields NUM_LANES  and SDR_DDR_N.

Laszlo

Hello, 

Thank you. I found that 1lane and 4lane are supported.

Right now I'm implementing axi_adrv9001 IP on an Intel SoC.

In CSSI 1Lane, it didn't work with rate = 7 of the adrv9002_axi_interface_set () function.

When I change it to rate = 31, CSSI 1 Lane works. Why is this?

Hello, 

the driver you are using is not yet updated to support also Intel, 

the 'rate' must be set according the 'DDS rate' from the following document: https://wiki.analog.com/resources/eval/user-guides/adrv9002/axi_adrv9002

You can observe the values you must set for Intel must be 4x of the Xilinx version. 

This is due the internal clock divider the design is using, that is different between the two implementations.  For Xilinx we divide the SSI clock with 4 in all the cases but for Intel we use the clock as is. 

Laszlo