Access to util_adxcvr qpll1 for usxgmii 10G ethernet

Xilinx UltrascaIe+ supports quad GTHE4 with two QPLLs (0 and 1) where the GTH common is used for configuring two protocols (different clock frequencies) within one quad GTH.

I am  using QPLL0 for  ADRV9009 FPGA reference design but now I need to share the GTH common block to implement 10G using USXGMII IP.

Even though, the "2018 r2" rtl shows the ports for qpll1_refclk and qpll2,3,4 .. 7_refclk, I don't see them in the BD instantiation.

Is there documentation that shows how to enable QPLL1?

I will be needing to use two QPLLs since the clock frequencies are higher than they are supported by util_adxcvr's CPLL ports.



typo
[edited by: luis at 10:47 PM (GMT -4) on 19 Apr 2021]

Top Replies

    •  Analog Employees 
    Apr 28, 2021 in reply to luis +1 verified

    Hi luis,

    unfortunately I do not see an easier path. Your plan looks good however pay attention to the QPLL power down signals, since currently the unused QPLL is powered down

    Laszlo

  • 0
    •  Analog Employees 
    on Apr 20, 2021 7:31 AM

    Hello,

    Support for QPLL1 is available only from 2019_r2, added with this commit (https://github.com/analogdevicesinc/hdl/commit/47f78948817ae19bc96f6fc689141414d7b397dc#diff-4d3011a96de97fc44acca736c541974cfd5d05312c32dbadb04e92abc3241ef5

    In our designs, we are using QPLL0 or QPLL1, not in parallel (not even sure if it's possible to have both running in parallel). 

    qpll_ref_clk_0[4/8/12] is the reference clock for each quad, not for each QPLL. If you have more than one quad (number of channels > 4 on either Rx or TX), an additional qpll_ref_clk port will appear.

    To my knowledge CPLL should support rates up to 12.5Gbps (depending on the FPGA). 

    Util_adxcvr is documented https://wiki.analog.com/resources/fpga/docs/axi_adxcvr 

    Regards,

    Adrian

  • Thank you for the quick response.

    Let me clarify.

    Within one GTH Quad there is one GTH Common cell and four GTH channels.   Each GTH quad supports two clocks using the GTH Common cell.  So that GTH Common cell will need to be "shared" using a "Shared Logic" in an example design.

    I would like to use one clock for your reference design (MGT_REF_CLK0 for JESD's util_adxcvr - 204.8 Mhz used by two GTH transceivers) and the other clock (MGT_REF_CLK1) for the 10G Ethernet clock (156.25 Mhz used in one GTH transceiver)

    The GTH Common cell is instantiated within the reference design's util_adxcvr (util_adxcvr -> util_adxcvr_xcm -> GTH4_COMMON).

    My question is how do I get access to that GTH Common cell so that I am able to provide a second reference clock but yet leave the current reference design working as it is now?

    The following xilinx thread describes a way that two different protocols share the GTH transceiver COMMON block:
    https://www.xilinx.com/support/answers/65228.html

    It seems that the only way to have the reference design and another protocol (i.e. 10 GE) coexist in the same GTH quad is to:

    1. Manually edit  hdl/library/xilinx/util_adxcvr/util_adxcvr.v to:
        -add qpll1_clk_ref input port
        -add separate QPLL1 parameters definitions to module util_adxcvr_xcm since currently they use QPLL0 parameters. 
        -change the util_adxcvr_xcm instantiation to configure the QPLL1 as needed to generate tx_out_clk_1
    2. Use tx_out_clk_1 to connect to 10G IP.

    Do you know if there is an easier way?  Or if there are signals/connections that I should be careful with as they relate to the reference design?

  • +1
    •  Analog Employees 
    on Apr 28, 2021 12:42 PM in reply to luis

    Hi ,

    unfortunately I do not see an easier path. Your plan looks good however pay attention to the QPLL power down signals, since currently the unused QPLL is powered down

    Laszlo