Xilinx UltrascaIe+ supports quad GTHE4 with two QPLLs (0 and 1) where the GTH common is used for configuring two protocols (different clock frequencies) within one quad GTH.
I am using QPLL0 for ADRV9009 FPGA reference design but now I need to share the GTH common block to implement 10G using USXGMII IP.
Even though, the "2018 r2" rtl shows the ports for qpll1_refclk and qpll2,3,4 .. 7_refclk, I don't see them in the BD instantiation.
Is there documentation that shows how to enable QPLL1?
I will be needing to use two QPLLs since the clock frequencies are higher than they are supported by util_adxcvr's CPLL ports.
[edited by: luis at 10:47 PM (GMT -4) on 19 Apr 2021]